WO2008025036A3 - Data processing systems utilizing secure memory - Google Patents

Data processing systems utilizing secure memory Download PDF

Info

Publication number
WO2008025036A3
WO2008025036A3 PCT/US2007/076919 US2007076919W WO2008025036A3 WO 2008025036 A3 WO2008025036 A3 WO 2008025036A3 US 2007076919 W US2007076919 W US 2007076919W WO 2008025036 A3 WO2008025036 A3 WO 2008025036A3
Authority
WO
WIPO (PCT)
Prior art keywords
ram
secure
data processing
executed
processor
Prior art date
Application number
PCT/US2007/076919
Other languages
French (fr)
Other versions
WO2008025036A2 (en
Inventor
Mehdi-Laurent Akkar
Aymeric Stephane Vial
Olivier Charles Schuepbach
Original Assignee
Texas Instruments Inc
Mehdi-Laurent Akkar
Aymeric Stephane Vial
Olivier Charles Schuepbach
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/531,043 external-priority patent/US8959311B2/en
Application filed by Texas Instruments Inc, Mehdi-Laurent Akkar, Aymeric Stephane Vial, Olivier Charles Schuepbach filed Critical Texas Instruments Inc
Publication of WO2008025036A2 publication Critical patent/WO2008025036A2/en
Publication of WO2008025036A3 publication Critical patent/WO2008025036A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
    • G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
    • G06F12/1425—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block
    • G06F12/1441—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block for a range
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/74—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information operating in dual or compartmented mode, i.e. at least one secure mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory

Abstract

A system (100) is provided that includes a processor (102) and a random access memory (RAM) (108) coupled to the processor. The RAM is divided into non-secure RAM (110) and secure RAM (112). The system also includes a system memory (106) coupled to the processor, wherein the system memory stores RAM resize instructions (120) that, when executed, enable the non-secure RAM and the secure RAM to be dynamically resized. The system memory may also store save/restore secure RAM instructions (122) that, when executed, perform a save operation that saves the secure RAM to non-volatile memory and a restore operation that restores the secure RAM from the non-volatile memory. The system memory may also store arbitration instructions (124) that, when executed, enable a cryptographic hardware accelerator (HWA) (130) to be shared by a secure application and a non-secure application.
PCT/US2007/076919 2006-08-25 2007-08-27 Data processing systems utilizing secure memory WO2008025036A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
EP06291368 2006-08-25
EP06291368.6 2006-08-25
US11/531,043 2006-09-12
US11/531,043 US8959311B2 (en) 2006-08-25 2006-09-12 Methods and systems involving secure RAM

Publications (2)

Publication Number Publication Date
WO2008025036A2 WO2008025036A2 (en) 2008-02-28
WO2008025036A3 true WO2008025036A3 (en) 2008-07-10

Family

ID=39107757

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/076919 WO2008025036A2 (en) 2006-08-25 2007-08-27 Data processing systems utilizing secure memory

Country Status (1)

Country Link
WO (1) WO2008025036A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2387752A1 (en) * 2008-12-18 2011-11-23 Nxp B.V. Establishing a secure memory path in a unitary memory architecture

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6192477B1 (en) * 1999-02-02 2001-02-20 Dagg Llc Methods, software, and apparatus for secure communication over a computer network
US20040177261A1 (en) * 2002-11-18 2004-09-09 Watt Simon Charles Control of access to a memory by a device
US20050132211A1 (en) * 2003-08-01 2005-06-16 Mamoon Yunus Java cryptographic engine to crypto acceleration integration
US20050216651A1 (en) * 2003-08-07 2005-09-29 Masamoto Tanabiki Information storage device having a divided area in memory area

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6192477B1 (en) * 1999-02-02 2001-02-20 Dagg Llc Methods, software, and apparatus for secure communication over a computer network
US20040177261A1 (en) * 2002-11-18 2004-09-09 Watt Simon Charles Control of access to a memory by a device
US20050132211A1 (en) * 2003-08-01 2005-06-16 Mamoon Yunus Java cryptographic engine to crypto acceleration integration
US20050216651A1 (en) * 2003-08-07 2005-09-29 Masamoto Tanabiki Information storage device having a divided area in memory area

Also Published As

Publication number Publication date
WO2008025036A2 (en) 2008-02-28

Similar Documents

Publication Publication Date Title
WO2007002804A3 (en) Wide-port context cache apparatus, systems, and methods
WO2010004243A3 (en) Interrupt processing
WO2004046920A3 (en) Processor cache memory as ram for execution of boot code
TW200617666A (en) System and method for extending the cross-memory descriptor to describe another partition's memory
TW200802082A (en) Shared nonvolatile memory architecture
WO2009023629A3 (en) Memory device and method having on-board address protection system for facilitating interface with multiple processors, and computer system using same
EP1736871A3 (en) System for executing code during operating system initialization
WO2007141206A3 (en) System, method and computer program product for secure access control to a storage device
WO2006095184A3 (en) Data processing system
WO2006044743A3 (en) Method and apparatus for initiating cpu data prefetches by an external agent
WO2007003370A3 (en) A memory arrangement for multi-processor systems
WO2009023637A3 (en) Memory device and method having on-board processing logic for facilitating interface with multiple processors, and computer system using same
WO2004051444A3 (en) Providing a secure execution mode in a pre-boot environment
WO2006082091A8 (en) Low latency massive parallel data processing device
AU2003213840A1 (en) Memory system with burst length shorter than prefetch length
EP1835389A3 (en) Storage system comprising microprocessor load distribution function
EP1860560A3 (en) Storage control method and system for performing backup and/or restoration
JP2005520247A5 (en)
WO2009140631A3 (en) Distributed computing system with universal address system and method
WO2004057479A3 (en) Page descriptors for prefetching and memory management
WO2008085787A3 (en) Multi buffer asynchronous scheme for processing incoming information
WO2008058154A3 (en) Using shared memory with an execute-in-place processor and a co-processor
WO2007076340A3 (en) Methods and systems to restrict usage of a dma channel
TW200643955A (en) Semiconductor memory device and information processing system
WO2007109707A3 (en) Method and system for rendering harmless a locked pestware executable object

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07841427

Country of ref document: EP

Kind code of ref document: A2

NENP Non-entry into the national phase

Ref country code: DE

NENP Non-entry into the national phase

Ref country code: RU

122 Ep: pct application non-entry in european phase

Ref document number: 07841427

Country of ref document: EP

Kind code of ref document: A2