WO2002077817A3 - Fault tolerant hybrid switching architecture coupling pci buses and processors - Google Patents

Fault tolerant hybrid switching architecture coupling pci buses and processors Download PDF

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Publication number
WO2002077817A3
WO2002077817A3 PCT/US2002/000917 US0200917W WO02077817A3 WO 2002077817 A3 WO2002077817 A3 WO 2002077817A3 US 0200917 W US0200917 W US 0200917W WO 02077817 A3 WO02077817 A3 WO 02077817A3
Authority
WO
WIPO (PCT)
Prior art keywords
hybrid switching
data channel
processors
switching module
fault tolerant
Prior art date
Application number
PCT/US2002/000917
Other languages
French (fr)
Other versions
WO2002077817A2 (en
Inventor
Johni Chan
Original Assignee
I Bus Phoenix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by I Bus Phoenix Inc filed Critical I Bus Phoenix Inc
Priority to AU2002235363A priority Critical patent/AU2002235363A1/en
Publication of WO2002077817A2 publication Critical patent/WO2002077817A2/en
Publication of WO2002077817A3 publication Critical patent/WO2002077817A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2043—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant where the redundant components share a common memory address space
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2023—Failover techniques
    • G06F11/2033—Failover techniques switching over of hardware resources

Abstract

A hybrid switching module includes a hybrid switching module processor data channel; a hybrid switching module main data channel; an input/output link data channel; a switch coupled to the hybrid switching module processor data channel; and a bridge coupled to the hybrid switching module main data channel; wherein the switch is selectively coupled to the bridge and selectively coupled to the input/output link data channel, wherein the hybrid switching module processor data channel is thereby selectively coupled to the bridge and selectively coupled to the input/output link data channel.
PCT/US2002/000917 2001-03-22 2002-01-14 Fault tolerant hybrid switching architecture coupling pci buses and processors WO2002077817A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002235363A AU2002235363A1 (en) 2001-03-22 2002-01-14 Fault tolerant hybrid switching architecture coupling pci buses and processors

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/815,772 2001-03-22
US09/815,772 US6950893B2 (en) 2001-03-22 2001-03-22 Hybrid switching architecture

Publications (2)

Publication Number Publication Date
WO2002077817A2 WO2002077817A2 (en) 2002-10-03
WO2002077817A3 true WO2002077817A3 (en) 2004-01-15

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/000917 WO2002077817A2 (en) 2001-03-22 2002-01-14 Fault tolerant hybrid switching architecture coupling pci buses and processors

Country Status (3)

Country Link
US (2) US6950893B2 (en)
AU (1) AU2002235363A1 (en)
WO (1) WO2002077817A2 (en)

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Also Published As

Publication number Publication date
US20040225785A1 (en) 2004-11-11
AU2002235363A1 (en) 2002-10-08
US20060031625A1 (en) 2006-02-09
US6950893B2 (en) 2005-09-27
WO2002077817A2 (en) 2002-10-03

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