WO2001079962A3 - Fault-tolerant maintenance bus, protocol, and method for using the same - Google Patents

Fault-tolerant maintenance bus, protocol, and method for using the same Download PDF

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Publication number
WO2001079962A3
WO2001079962A3 PCT/US2001/011804 US0111804W WO0179962A3 WO 2001079962 A3 WO2001079962 A3 WO 2001079962A3 US 0111804 W US0111804 W US 0111804W WO 0179962 A3 WO0179962 A3 WO 0179962A3
Authority
WO
WIPO (PCT)
Prior art keywords
command
bridge
maintenance bus
maintenance
protocol
Prior art date
Application number
PCT/US2001/011804
Other languages
French (fr)
Other versions
WO2001079962A2 (en
Inventor
A Charles Suffin
Joseph S Amato
Paul Joyce
Original Assignee
Stratus Technologies Internati
A Charles Suffin
Joseph S Amato
Paul Joyce
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/548,202 external-priority patent/US6691257B1/en
Priority claimed from US09/548,536 external-priority patent/US6633996B1/en
Application filed by Stratus Technologies Internati, A Charles Suffin, Joseph S Amato, Paul Joyce filed Critical Stratus Technologies Internati
Priority to AU2001251536A priority Critical patent/AU2001251536A1/en
Publication of WO2001079962A2 publication Critical patent/WO2001079962A2/en
Publication of WO2001079962A3 publication Critical patent/WO2001079962A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2002—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant
    • G06F11/2007—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant using redundant communication media

Abstract

A fault-tolerant maintenance bus architecture and protocol for use therewith provides dual maintenance buses interconnecting each of a plurality of parent circuit boards. The two maintenance buses are each connected to a pair of system management modules (SMMs) that are configured to perform a variety of maintenance bus activities. Within each parent board are a pair of redundant bridges each having a unique address. One bridge is connected to the first maintenance bus while a second bridge is connected to the second maintenance bus of the pair. A child maintenance bus interconnects the two bridges on child circuit board. The child maintenance bus is interconnected to a bridge assembly that itself directs messages formatted in the protocol between the subsystem components and the command module through the bridge. The protocol includes a command message structure that uniquely addresses the bridge assembly. It also includes a command string, a command data string for communicating with one of the subsystem components and a command error-checking string. A response message structure is generated by the bridge in response to a command message. The response message uniquely addresses the command module. It includes error and status strings with respect to execution of the command message, a response data string for communicating with the command module and a response error-checking string.
PCT/US2001/011804 2000-04-13 2001-04-11 Fault-tolerant maintenance bus, protocol, and method for using the same WO2001079962A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001251536A AU2001251536A1 (en) 2000-04-13 2001-04-11 Fault-tolerant maintenance bus, protocol, and method for using the same

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US09/548,202 2000-04-13
US09/548,202 US6691257B1 (en) 2000-04-13 2000-04-13 Fault-tolerant maintenance bus protocol and method for using the same
US09/548,536 US6633996B1 (en) 2000-04-13 2000-04-13 Fault-tolerant maintenance bus architecture
US09/548,536 2000-04-13

Publications (2)

Publication Number Publication Date
WO2001079962A2 WO2001079962A2 (en) 2001-10-25
WO2001079962A3 true WO2001079962A3 (en) 2003-02-27

Family

ID=27068796

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/011804 WO2001079962A2 (en) 2000-04-13 2001-04-11 Fault-tolerant maintenance bus, protocol, and method for using the same

Country Status (2)

Country Link
AU (1) AU2001251536A1 (en)
WO (1) WO2001079962A2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100369003C (en) * 2001-11-16 2008-02-13 中兴通讯股份有限公司 Method for carrying out distribution function of multiple objects
US7304950B2 (en) * 2003-12-15 2007-12-04 Finisar Corporation Two-wire interface having dynamically adjustable data fields depending on operation code
EP2228725A1 (en) * 2009-03-13 2010-09-15 Giga-Byte Technology Co., Ltd. Motherboard with backup chipset
US8635500B2 (en) * 2011-08-09 2014-01-21 Alcatel Lucent System and method for powering redundant components
CN113190395B (en) * 2021-03-15 2023-08-18 新华三信息技术有限公司 State monitoring method and device

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4128883A (en) * 1977-09-30 1978-12-05 Ncr Corporation Shared busy means in a common bus environment
WO1997024677A1 (en) * 1995-12-28 1997-07-10 Intel Corporation A method and apparatus for interfacing a device compliant to first bus protocol to an external bus
WO1998021660A1 (en) * 1996-11-14 1998-05-22 Data General Corporation Dynamically upgradeable disk array system and method
US5884027A (en) * 1995-06-15 1999-03-16 Intel Corporation Architecture for an I/O processor that integrates a PCI to PCI bridge
US5892928A (en) * 1997-05-13 1999-04-06 Micron Electronics, Inc. Method for the hot add of a network adapter on a system including a dynamically loaded adapter driver
WO1999059066A1 (en) * 1998-05-14 1999-11-18 Motorola, Inc. Controlling a bus with multiple system hosts
WO1999066410A1 (en) * 1998-06-15 1999-12-23 Sun Microsystems, Inc. Direct memory access in a bridge for a multi-processor system

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4128883A (en) * 1977-09-30 1978-12-05 Ncr Corporation Shared busy means in a common bus environment
US5884027A (en) * 1995-06-15 1999-03-16 Intel Corporation Architecture for an I/O processor that integrates a PCI to PCI bridge
WO1997024677A1 (en) * 1995-12-28 1997-07-10 Intel Corporation A method and apparatus for interfacing a device compliant to first bus protocol to an external bus
WO1998021660A1 (en) * 1996-11-14 1998-05-22 Data General Corporation Dynamically upgradeable disk array system and method
US5892928A (en) * 1997-05-13 1999-04-06 Micron Electronics, Inc. Method for the hot add of a network adapter on a system including a dynamically loaded adapter driver
WO1999059066A1 (en) * 1998-05-14 1999-11-18 Motorola, Inc. Controlling a bus with multiple system hosts
WO1999066410A1 (en) * 1998-06-15 1999-12-23 Sun Microsystems, Inc. Direct memory access in a bridge for a multi-processor system

Also Published As

Publication number Publication date
WO2001079962A2 (en) 2001-10-25
AU2001251536A1 (en) 2001-10-30

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