WO1997043712A3 - Triple modular redundant computer system - Google Patents

Triple modular redundant computer system Download PDF

Info

Publication number
WO1997043712A3
WO1997043712A3 PCT/US1997/008320 US9708320W WO9743712A3 WO 1997043712 A3 WO1997043712 A3 WO 1997043712A3 US 9708320 W US9708320 W US 9708320W WO 9743712 A3 WO9743712 A3 WO 9743712A3
Authority
WO
WIPO (PCT)
Prior art keywords
bus
transaction information
processor
system module
computer system
Prior art date
Application number
PCT/US1997/008320
Other languages
French (fr)
Other versions
WO1997043712A2 (en
Inventor
James L Petivan
Donald C Lundell
Jonathan K Lundell
Original Assignee
Resilience Corp
James L Petivan
Donald C Lundell
Jonathan K Lundell
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Resilience Corp, James L Petivan, Donald C Lundell, Jonathan K Lundell filed Critical Resilience Corp
Priority to DE69708881T priority Critical patent/DE69708881T2/en
Priority to EP97926550A priority patent/EP0916119B1/en
Priority to AU31288/97A priority patent/AU3128897A/en
Priority to AT97926550T priority patent/ATE210316T1/en
Priority to IL12705997A priority patent/IL127059A0/en
Priority to JP54114297A priority patent/JP2002515146A/en
Publication of WO1997043712A2 publication Critical patent/WO1997043712A2/en
Publication of WO1997043712A3 publication Critical patent/WO1997043712A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G06F11/181—Eliminating the failing redundant component
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G06F11/182—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits based on mutual exchange of the output between redundant processing components
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G06F11/187—Voting techniques
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/165—Error detection by comparing the output of redundant processing systems with continued operation after detection of the error
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing

Abstract

A fault tolerant computer system is provided which includes a first system module with a first processor and a first processor bus and a first I/O bus; a second system module with a second processor and a second processor bus and a second I/O bus; a third system module with a third processor and a third processor bus and a third I/O bus; wherein the first system module further includes a first control device which coordinates transfer of first transaction information between the first processor bus and each of the first I/O bus or the second I/O bus or the third I/O bus; and wherein the first system module includes first comparison logic which compares first transaction information with corresponding second transaction information; wherein the second system module further includes a second control device which coordinates transfer of second transaction information between the second processor bus and each of the first I/O bus or the second I/O bus or the third I/O bus; and wherein the second system module includes second comparison logic which compares second transaction information with corresponding third transaction information; wherein the third system module futher includes a third control device which coordinates transfer of third transaction information between the third processor bus and each of the first I/O bus or the second I/O bus or the third I/O bus; and wherein the third system module includes third comparison logic which compares third transaction information with corresponding first transaction information; and transfer circuitry which transfers the first, second and third transaction information among the first, second and third system modules.
PCT/US1997/008320 1996-05-16 1997-05-15 Triple modular redundant computer system WO1997043712A2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
DE69708881T DE69708881T2 (en) 1996-05-16 1997-05-15 TRIPLE REDUNDANT MODULAR COMPUTER SYSTEM
EP97926550A EP0916119B1 (en) 1996-05-16 1997-05-15 Triple modular redundant computer system
AU31288/97A AU3128897A (en) 1996-05-16 1997-05-15 Triple modular redundant computer system
AT97926550T ATE210316T1 (en) 1996-05-16 1997-05-15 TRIPLE REDUNDANT MODULAR COMPUTER SYSTEM
IL12705997A IL127059A0 (en) 1996-05-16 1997-05-15 Computer system
JP54114297A JP2002515146A (en) 1996-05-16 1997-05-15 Triple module redundant computer system

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US1720196P 1996-05-16 1996-05-16
US60/017,201 1996-05-16
US60/037,363 1997-01-31
US08/853,670 1997-05-09

Publications (2)

Publication Number Publication Date
WO1997043712A2 WO1997043712A2 (en) 1997-11-20
WO1997043712A3 true WO1997043712A3 (en) 1998-05-14

Family

ID=21781294

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1997/008320 WO1997043712A2 (en) 1996-05-16 1997-05-15 Triple modular redundant computer system

Country Status (3)

Country Link
AU (1) AU3128897A (en)
TW (1) TW320701B (en)
WO (1) WO1997043712A2 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6260159B1 (en) * 1998-06-15 2001-07-10 Sun Microsystems, Inc. Tracking memory page modification in a bridge for a multi-processor system
US6148348A (en) * 1998-06-15 2000-11-14 Sun Microsystems, Inc. Bridge interfacing two processing sets operating in a lockstep mode and having a posted write buffer storing write operations upon detection of a lockstep error
US6141718A (en) * 1998-06-15 2000-10-31 Sun Microsystems, Inc. Processor bridge with dissimilar data registers which is operable to disregard data differences for dissimilar data direct memory accesses
US6587961B1 (en) * 1998-06-15 2003-07-01 Sun Microsystems, Inc. Multi-processor system bridge with controlled access
DE19844562B4 (en) * 1998-09-29 2006-06-01 Dr. Johannes Heidenhain Gmbh Method for the safe monitoring of clock rates in a redundant system
JP3349983B2 (en) * 1999-05-14 2002-11-25 エヌイーシーマイクロシステム株式会社 Semiconductor integrated circuit device
DE10023166A1 (en) * 2000-05-11 2001-11-15 Alcatel Sa Multi-computer system for generating a master clock to synchronize a cluster of computers forms a real-time system requiring the master clock to fix the system's cycle time.
FR2819598B1 (en) * 2001-01-16 2003-04-11 Thomson Csf FAULT-TOLERANT SYNCHRONIZATION DEVICE FOR A REAL-TIME COMPUTER NETWORK
US7725618B2 (en) * 2004-07-29 2010-05-25 International Business Machines Corporation Memory barriers primitives in an asymmetric heterogeneous multiprocessor environment
US10353767B2 (en) * 2017-09-14 2019-07-16 Bae Systems Controls Inc. Use of multicore processor to mitigate common mode computing faults

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0447577A1 (en) * 1988-12-09 1991-09-25 Tandem Computers Incorporated High-performance computer system with fault-tolerant capability
WO1992003787A1 (en) * 1990-08-14 1992-03-05 Siemens Aktiengesellschaft Highly safe multi-computer system with three computers
JPH05204692A (en) * 1992-01-30 1993-08-13 Nec Corp Failure detecting/separating system for information processor
JPH06250867A (en) * 1993-03-01 1994-09-09 Nippon Telegr & Teleph Corp <Ntt> Failure resisting computer and failure resisting calculation processing method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0447577A1 (en) * 1988-12-09 1991-09-25 Tandem Computers Incorporated High-performance computer system with fault-tolerant capability
WO1992003787A1 (en) * 1990-08-14 1992-03-05 Siemens Aktiengesellschaft Highly safe multi-computer system with three computers
JPH05204692A (en) * 1992-01-30 1993-08-13 Nec Corp Failure detecting/separating system for information processor
JPH06250867A (en) * 1993-03-01 1994-09-09 Nippon Telegr & Teleph Corp <Ntt> Failure resisting computer and failure resisting calculation processing method

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
OZGUNER F ET AL: "A RECONFIGURABLE MULTIPROCESSOR ARCHITECTURE FOR RELIABLE CONTROL OF ROBOTIC SYSTEMS", 1985 IEEE INTERNATIONAL CONFERENCE ON ROBOTICS AND AUTOMATION, 25 March 1985 (1985-03-25) - 28 March 1985 (1985-03-28), ST. LOUIS, MO, US, pages 802 - 806, XP000647411 *
PATENT ABSTRACTS OF JAPAN vol. 017, no. 634 (P - 1649) 24 November 1993 (1993-11-24) *
PATENT ABSTRACTS OF JAPAN vol. 018, no. 645 (P - 1839) 7 December 1994 (1994-12-07) *

Also Published As

Publication number Publication date
AU3128897A (en) 1997-12-05
TW320701B (en) 1997-11-21
WO1997043712A2 (en) 1997-11-20

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