WO1994009437A1 - Signal handling system with a shared data memory - Google Patents

Signal handling system with a shared data memory Download PDF

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Publication number
WO1994009437A1
WO1994009437A1 PCT/SE1993/000840 SE9300840W WO9409437A1 WO 1994009437 A1 WO1994009437 A1 WO 1994009437A1 SE 9300840 W SE9300840 W SE 9300840W WO 9409437 A1 WO9409437 A1 WO 9409437A1
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WO
WIPO (PCT)
Prior art keywords
bus
processors
access
control processor
signal processors
Prior art date
Application number
PCT/SE1993/000840
Other languages
French (fr)
Inventor
Lars Svensson
Johan Zeberg
Original Assignee
Telefonaktiebolaget Lm Ericsson
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget Lm Ericsson filed Critical Telefonaktiebolaget Lm Ericsson
Priority to EP93923104A priority Critical patent/EP0616710A1/en
Priority to AU52900/93A priority patent/AU5290093A/en
Publication of WO1994009437A1 publication Critical patent/WO1994009437A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1663—Access to shared memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox

Definitions

  • Si ⁇ nal handling system with a shared data memory Si ⁇ nal handling system with a shared data memory.
  • the present invention relates to a signal processing system, including a superior control processor, a number of digital signal processors, which are controlled by the control processor and normally operate internally with real time applications, a shared data memory with a bus, on which the control processor normally is bus master, and to which the signal processors have access, and an arbitration logic, which controls the access of the processors to the shared data memory.
  • SE-B-442,352 a data processing system of essentially the kind indicated by way of introduction is known.
  • the system includes a central computer, a bus, a memory, a plurality of peripheral computers, and an arbitration logic controlling the access of the computers to the memory.
  • a central computer As appears from page 2, from line 14, in this document, has normally, however, in this system only the central computer access to the memory via the bus, whereas the peripheral computers are disconnected from the bus line.
  • a processor system including a superior control processor and a number of subordinate processors.
  • An arbitration circuit controls all access to a common memory from buses connecting together the subordinate processors and includes address lines and data lines.
  • a bus assigning function in the arbitration circuit provides sequencial bus access for the subordinate processors.
  • a bus access logic in each such processor controls request for access to the bus.
  • US-A-5,067,071 describes and shows a multiprocessor system with a memory shared by all processor modules.
  • a bus arbitration function is arranged in a system control module for controlling the access of the processors to the common memory.
  • the data buses and address buses of the processor modules are connected via tranceivers to the common system bus.
  • the system handles request and access.
  • ES-A-4,499,538 relates to access arbitration for a system with several processors and a common bus.
  • a common resource consists of a number of memories.
  • a plurality of processors can via a bus obtain access to the common resource.
  • Each one of the processors has assigned thereto an own arbitration function.
  • EP-Al-464,708 there is described a bus system with a number of processors and a common memory.
  • a central circuit includes arbitration logic for handling access of the processors to the common memory.
  • US-A-4,803,617 describes a multiprocessor system with a common mass memory. Each processor emits a request when it needs access to a position in the main memory via the bus. During the time data transaction is performed all other processors must wait for the bus being free. An arbitrator arranges access of the processors to the bus.
  • the object of the present invention is to minimize, in a signal processing system of the kind defined by way of introduction, the number of necessary components, and suggest a solution where access to the shared memory can be attained with short delay and without master-slave configuration and external buffers.
  • the system shown in Fig. 1 includes five microprocessors, viz. one superior control processor 2 and four digital signal processors 4, 6, 8 and 10.
  • the processors 2-10 have a common link 12, having as a first function to serve as a signalling channel, via which the control processor 2 performs operation and maintainance functions as well as certain real time operations.
  • the digital signal processors 4, 6, 8 and 10 perform real time operations and execute programs internally.
  • the control processor 2 has an external program memory in the form of a PROM 14.
  • This PROM 14 also includes application programs for the digital signal processors 4, 6, 8 and 10.
  • the link 12 also serves for transferring the application program from the processor 2 to the digital signal processors, one at a time.
  • a RAM 18 is a shared memory between the control processor 2 and the signal processors 4-10. To this RAM 18 a bus 20, indicated with dashed lines, leads, that includes data buses and address buses as well as read strobes and write strobes.
  • the control processor 2 is normally bus master for the bus 20 and the signal processors are directly connected to the bus 20 by means of their own buses 22.
  • the signal processors 4, 6, 8 and 10 have an inner RAM (not shown) for programs and data, as well as an inner ROM (not shown) for start up programs. This implies that each signal processor can operate internally with its own application program. This application program contains instructions for keeping the bus 22 of the corresponding signal processor on a high impedance level. No external data access occurs except when the signal processor desires to use the shared memory 18.
  • the signal processors 4-10 keep their buses 22 on a high impedance level and are directly connected to the bus 20 without mediation by any external buffer.
  • the four signal processors are designed to send, in case of desired access to the memory 18, an inquiry signal to an arbitration logic 28 for the bus 20 via each an inquiry line 30.1, 30.2, 30.3 and 30.4, respectively, and to receive a confirmation, if any, on the request from the arbitration logic via each a confirmation line 32.1, 32.2, 32.3 and 32.4, respectively.
  • One purpose of the arbitration logic 28 is to send, at receipt of a demand for bus access in the form of such an inquiry signal from any of the signal processors, a corresponding demand to the control processor via a line 34. If the bus 20 is available the control processor replies via a line 36 to the arbitration logic 28 with a signal implying that the demand has been accepted. The arbitration logic then informs this to the inquiring signal processor via the confirmation line of the latter. Thereby the ownership to the bus 20 is transferred to the signal processor in question.
  • the arbitration logic 28 will let the request wait until the bus becomes free. If more signal processors simultaneously have requested the bus it is assigned by rotating assignment.
  • the block diagram on the drawing also includes a time slot assignment logic 38 controlled from the control processor 2 and distributing the time slots of the PCM channels to the different signal processors 4-10.
  • the distribution is completely free which implies that a time slot can be taken care of by any of the four signal processors.
  • the logic 38 generates synchronization pulses, one for each time slot, both for the sending and for the receiving direction. The pulses are generated to all signal processors working in the configuration in question. If no time slot is active no pulses are generated by the logic 38.

Abstract

A signal processing system includes a superior control processor (2) and a number of digital signal processors (4-10), which are controlled by the control processor and normally operate internally with real time applications. A shared data memory (18) is included with a bus (20), on which the control processor normally is bus master, and to which the signal processors have access. An arbitration logic (28) controls the access of the processors (4-10) to the shared data memory. The signal processors (4-10) are directly connected to the bus (20) and normally keep their data and address buses (22) on a high impedance level with respect thereto.

Description

Siσnal handling system with a shared data memory.
Technical field of the invention.
The present invention relates to a signal processing system, including a superior control processor, a number of digital signal processors, which are controlled by the control processor and normally operate internally with real time applications, a shared data memory with a bus, on which the control processor normally is bus master, and to which the signal processors have access, and an arbitration logic, which controls the access of the processors to the shared data memory.
Description of related art.
Common to known earlier circuits of the kind defined by way of introduction is that they require external buffers between each signal processor and the bus.
Through SE-B-442,352 a data processing system of essentially the kind indicated by way of introduction is known. The system includes a central computer, a bus, a memory, a plurality of peripheral computers, and an arbitration logic controlling the access of the computers to the memory. As appears from page 2, from line 14, in this document, has normally, however, in this system only the central computer access to the memory via the bus, whereas the peripheral computers are disconnected from the bus line.
Through GB-A-1,600,756 a processor system is known including a superior control processor and a number of subordinate processors. An arbitration circuit controls all access to a common memory from buses connecting together the subordinate processors and includes address lines and data lines. A bus assigning function in the arbitration circuit provides sequencial bus access for the subordinate processors. A bus access logic in each such processor controls request for access to the bus.
US-A-5,067,071 describes and shows a multiprocessor system with a memory shared by all processor modules. A bus arbitration function is arranged in a system control module for controlling the access of the processors to the common memory.
The data buses and address buses of the processor modules are connected via tranceivers to the common system bus. The system handles request and access.
ES-A-4,499,538 relates to access arbitration for a system with several processors and a common bus. A common resource consists of a number of memories. A plurality of processors can via a bus obtain access to the common resource.
Each one of the processors has assigned thereto an own arbitration function.
In EP-Al-464,708 there is described a bus system with a number of processors and a common memory. A central circuit includes arbitration logic for handling access of the processors to the common memory.
US-A-4,803,617 describes a multiprocessor system with a common mass memory. Each processor emits a request when it needs access to a position in the main memory via the bus. During the time data transaction is performed all other processors must wait for the bus being free. An arbitrator arranges access of the processors to the bus.
From US-A-4,924,380 a similar system as that just described is known. Beyond this, technique is described for providing a better bus effectivity by means of an arbitration system consisting of two rotating queues with a fixed priority between the queues.
Summary of the invention.
The object of the present invention is to minimize, in a signal processing system of the kind defined by way of introduction, the number of necessary components, and suggest a solution where access to the shared memory can be attained with short delay and without master-slave configuration and external buffers.
This object has been attained in that, in accordance with the invention, the signal processors are directly connected to the bus and normally keep their data and adress buses on a high impedance level with respect thereto.
Brief description of the drawing.
The invention will now be described more closely with reference to a schematic block diagram of a signal handling system shown on the attached drawing. Preferred embodiment.
The system shown in Fig. 1 includes five microprocessors, viz. one superior control processor 2 and four digital signal processors 4, 6, 8 and 10. The processors 2-10 have a common link 12, having as a first function to serve as a signalling channel, via which the control processor 2 performs operation and maintainance functions as well as certain real time operations. The digital signal processors 4, 6, 8 and 10 perform real time operations and execute programs internally.
The control processor 2 has an external program memory in the form of a PROM 14. This PROM 14 also includes application programs for the digital signal processors 4, 6, 8 and 10. The link 12 also serves for transferring the application program from the processor 2 to the digital signal processors, one at a time.
A RAM 18 is a shared memory between the control processor 2 and the signal processors 4-10. To this RAM 18 a bus 20, indicated with dashed lines, leads, that includes data buses and address buses as well as read strobes and write strobes. The control processor 2 is normally bus master for the bus 20 and the signal processors are directly connected to the bus 20 by means of their own buses 22.
The signal processors 4, 6, 8 and 10 have an inner RAM (not shown) for programs and data, as well as an inner ROM (not shown) for start up programs. This implies that each signal processor can operate internally with its own application program. This application program contains instructions for keeping the bus 22 of the corresponding signal processor on a high impedance level. No external data access occurs except when the signal processor desires to use the shared memory 18.
Data from/to a PCM channel 24 with an input PCMA and an output PCMB are clocked in/out via serial ports 26 of the signal processors.
As mentioned the signal processors 4-10 keep their buses 22 on a high impedance level and are directly connected to the bus 20 without mediation by any external buffer. The four signal processors are designed to send, in case of desired access to the memory 18, an inquiry signal to an arbitration logic 28 for the bus 20 via each an inquiry line 30.1, 30.2, 30.3 and 30.4, respectively, and to receive a confirmation, if any, on the request from the arbitration logic via each a confirmation line 32.1, 32.2, 32.3 and 32.4, respectively.
One purpose of the arbitration logic 28 is to send, at receipt of a demand for bus access in the form of such an inquiry signal from any of the signal processors, a corresponding demand to the control processor via a line 34. If the bus 20 is available the control processor replies via a line 36 to the arbitration logic 28 with a signal implying that the demand has been accepted. The arbitration logic then informs this to the inquiring signal processor via the confirmation line of the latter. Thereby the ownership to the bus 20 is transferred to the signal processor in question.
If the bus 20 is requested by any signal processor when it is owned by the control processor 2 and not available, i.e. the latter uses the bus, the arbitration logic 28 will let the request wait until the bus becomes free. If more signal processors simultaneously have requested the bus it is assigned by rotating assignment.
The block diagram on the drawing also includes a time slot assignment logic 38 controlled from the control processor 2 and distributing the time slots of the PCM channels to the different signal processors 4-10. The distribution is completely free which implies that a time slot can be taken care of by any of the four signal processors. The logic 38 generates synchronization pulses, one for each time slot, both for the sending and for the receiving direction. The pulses are generated to all signal processors working in the configuration in question. If no time slot is active no pulses are generated by the logic 38.
At 40 and 42 input and output signalling channels to the control processor are indicated.
Certain details and functions in the system shown and described have not been described in more detail above. In such cases it has been presumed that it is the question either of matter, about which the man of the art does not need any closer information for being able to practice the invention, or matter not having any relationship with the invention.

Claims

Claims.
1. A signal processing system, including a superior control processor (2) , a number of digital signal processors (4-10) , which are controlled by the control processor and normally operate internally with real time applications, a shared data memory (18) with a bus (20) , on which the control processor normally is bus master, and to which the signal processors have access, and an arbitration logic (28) , which controls the access of the processors (4-10) to the shared data memory, characterized in that the signal processors (4-10) are directly connected to the bus (20) and normally keep their data and address buses (22) on a high impedance level with respect thereto.
PCT/SE1993/000840 1992-10-14 1993-10-14 Signal handling system with a shared data memory WO1994009437A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP93923104A EP0616710A1 (en) 1992-10-14 1993-10-14 Signal handling system with a shared data memory
AU52900/93A AU5290093A (en) 1992-10-14 1993-10-14 Signal handling system with a shared data memory

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9203016A SE9203016L (en) 1992-10-14 1992-10-14 Signal processing system with shared data memory
SE9203016-2 1992-10-14

Publications (1)

Publication Number Publication Date
WO1994009437A1 true WO1994009437A1 (en) 1994-04-28

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PCT/SE1993/000840 WO1994009437A1 (en) 1992-10-14 1993-10-14 Signal handling system with a shared data memory

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EP (1) EP0616710A1 (en)
AU (1) AU5290093A (en)
SE (1) SE9203016L (en)
WO (1) WO1994009437A1 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2283596A (en) * 1993-11-01 1995-05-10 Ericsson Ge Mobile Communicat Multiprocessor system with data memory sharing
WO1996008774A1 (en) * 1994-09-16 1996-03-21 Ionica International Limited Bus assignment system for dsp processors
EP1220103A1 (en) * 2000-12-29 2002-07-03 Zarlink Semiconductor Limited Arbiter for a queue management system
EP1239374A1 (en) * 2000-11-08 2002-09-11 Texas Instruments Incorporated Shared program memory for use in multicore DSP devices

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4504906A (en) * 1982-11-30 1985-03-12 Anritsu Electric Company Limited Multiprocessor system
US4523274A (en) * 1980-04-04 1985-06-11 Hitachi, Ltd. Data processing system with processors having different processing speeds sharing a common bus
US4611275A (en) * 1979-07-30 1986-09-09 Jeumont-Schneider Time sharing device for access to a main memory through to a single bus connected between a central computer and a plurality of peripheral computers
US5067071A (en) * 1985-02-27 1991-11-19 Encore Computer Corporation Multiprocessor computer system employing a plurality of tightly coupled processors with interrupt vector bus

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4611275A (en) * 1979-07-30 1986-09-09 Jeumont-Schneider Time sharing device for access to a main memory through to a single bus connected between a central computer and a plurality of peripheral computers
US4523274A (en) * 1980-04-04 1985-06-11 Hitachi, Ltd. Data processing system with processors having different processing speeds sharing a common bus
US4504906A (en) * 1982-11-30 1985-03-12 Anritsu Electric Company Limited Multiprocessor system
US5067071A (en) * 1985-02-27 1991-11-19 Encore Computer Corporation Multiprocessor computer system employing a plurality of tightly coupled processors with interrupt vector bus

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2283596A (en) * 1993-11-01 1995-05-10 Ericsson Ge Mobile Communicat Multiprocessor system with data memory sharing
GB2283596B (en) * 1993-11-01 1998-07-01 Ericsson Ge Mobile Communicat Multiprocessor data memory sharing
WO1996008774A1 (en) * 1994-09-16 1996-03-21 Ionica International Limited Bus assignment system for dsp processors
EP1239374A1 (en) * 2000-11-08 2002-09-11 Texas Instruments Incorporated Shared program memory for use in multicore DSP devices
US6691216B2 (en) 2000-11-08 2004-02-10 Texas Instruments Incorporated Shared program memory for use in multicore DSP devices
EP1220103A1 (en) * 2000-12-29 2002-07-03 Zarlink Semiconductor Limited Arbiter for a queue management system
US6898649B2 (en) * 2000-12-29 2005-05-24 Zarlink Semiconductor Limited Arbiter for queue management system for allocating bus mastership as a percentage of total bus time

Also Published As

Publication number Publication date
SE9203016L (en) 1994-04-15
EP0616710A1 (en) 1994-09-28
SE9203016D0 (en) 1992-10-14
AU5290093A (en) 1994-05-09

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