WO1991005418A1

WO1991005418A1 - Parallel control for a packet/fast packet switch

Info

Publication number: WO1991005418A1
Application number: PCT/US1990/004758
Authority: WO
Inventors: Inc. Motorola; Roy T. Ogasawara; Richard E. White; Thomas A. Freeburg
Original assignee: Motorola Inc
Priority date: 1989-09-29
Filing date: 1990-08-23
Publication date: 1991-04-18
Also published as: HU906259D0; IL95206A0; AU6600490A

Abstract

A voice/data packet switch with an improved bus architecture is provided. Accordingly, a parallel control architecture for a packet/fast packet switch, according to the invention, is disclosed herein. This invention provides a voice/data packet/fast packet switch bus architecture with parallel bus structures for control (203) and data (201). Moreover, the present invention provides for a synchronization between the control of the devices sending and receiving packets in a voice/data packet switch. It also provides the capability of having multiple packet devices on a common bus sending/receiving packets from one another. It allows packet devices to send as much or as little information by modifying the control memory. The control of the packet devices can be controlled at a very high bit rate such as, for example, 40 Mbps.

Description

PARALLEL CONTROL FOR A PACKET/FAST PACKET SWITCH

Technical Field

This invention pertains to voice/data packet switches and, more particularly, to a bus architecture for such switches.

Background of the Invention

Voice and data switches are known in the prior art. Packet switching is also known. In the past, however, synchronization for the control of the devices sending and receiving information packets in a voice/data packet switch has been a problem. This problem has been related to the problem of dynamically allocating the packet bandwidth between the various peripheral devices attached to the switch for voice information and data information. Another related factor has been the bus architecture for the switch. Past switches have used the same bus for both data and control. When coupled with the problem of dynamically allocating bandwidth on the bus, this bus architecture has resulted in the switch having a low switching capacity and throughput. These performance problems become even more significant in the context of modern fast packet protocols. It would be desirable, therefore, to provide a voice/data packet switch with an improved bus architecture. Summarv of the Invention

It is an object of this invention, therefore, to provide a voice/data packet switch with an improved bus architecture. As a result, a parallel control architecture for a packet/fast packet switch for time division multiple access (hereinafter "TDMA") voice/data packets, according to the invention, is disclosed herein. This invention provides a voice/data packet/fast packet switch bus architecture with parallel bus structures for control and data. Moreover, the present invention provides for a synchronization between the control of the devices sending and receiving packets in a voice/data packet switch. It also provides the capability of having multiple packet devices on a common bus sending/receiving packets from one another. It allows packet devices to send as much or as little information by modifying the control memory. The control of the packet devices can be controlled at a very high bit rate such as, for example, 40 Mbps.

The parallel control architecture for a packet/fast packet switch, according to the invention, allows for the data packets and the control of bandwidth allocation to be controlled by a single switching device. By synchronizing the transfer of the data and the allocation of bus bandwidth, the inventors have discovered the control of the packet devices can be controlled at a very high bit rate such as, for example, 40 Mbps.

Brief Description of the Figures

Fig. 1 is a block diagram of a first embodiment of a parallel control for a packet/fast packet switch, according to the invention. Fig. 2 shows the Network Interface Bus for the first embodiment.

Fig. 3 shows the Network Interface Bus configuration. Fig. 4 shows a control byte for the control bus 203. Fig. 5 shows an address byte for the control bus 203. Fig. 6 shows a command byte for the control bus 203. Fig. 7 shows a control data byte for the control bus 203.

Fig. 8 is a tirring diagram showing the control clock timing.

Fig. 9 is a timing diagram showing the packet start and data clock timing. Fig. 10 is a timing diagram showing the packet end and packet start timing for a valid packet with additional bytes.

Fig. 11 is a timing diagram showing the packet end and packet start timing for a valid packet with no additional bytes.

Fig. 12 is a timing diagram showing the packet end and packet start timing with a maximum packet size error.

Fig. 13 is a timing diagram showing the packet end and packet start timing with a CRC error.

Detailed Description ςf the Invention

Referring now to Fig. 1 , it is seen that the Network Interface 105 is the focus of the LAN device (both Node and UIM). It connects the various interfaces on the LAN (both cable and radio) to one another and to the Control Processor 107, providing time-division and fast-packet switching. Information is transferred among these interfaces via the Network Interface Memory 209 that is accessible both by the control sections of the Network Interface (both input and output), and by the Control Processor 107. Information flow on the LAN side is via the Network Interface Bus (Nl-Bus) 101, which is designed to pass data at rates up to, for example, 5 million bytes per second, and to handle the corresponding control information at a similar rate. The microprocessor bus 103 couples the network interface 105 to the control processor 107. Referring now to Fig. 2, the interaction between the Network Interface Memory 209 and the Nl-Bus 101 is shown. The Output Control circuitry, part of the Network Interface chip 109, sequentially steps through the Control memory 211 and presents address and command bytes to the Control Bus 203. This information controls which device is driving the Nl-Bus 101 and which device is listening. All Nl-Bus devices, iπcluding the Network Interface 105, listen to the Control Bus 203 to determine what the activity is on the Data Bus 201. The Output Control circuitry also sequentially steps through the Data memory. If the Network Interface 105 is driving the bus 101 , the information in the Data memory 213 will be output to the Data Bus 201. If the Network Interface 105 is listening to the Data Bus 201 , the Input Control 205 will accept the data and put it in the proper area of Network Interface Memory 209. The Network Interface 105 can both listen and drive the bus 101 at the same time. This allows the Network Interface 105 to be put in a ioopback mode.

Referring now to Fig. 3, the definition of the 20 lines in the Network Interface Bus 101 is shown. (Timing information for the Nl-Bus is given below in Figs. 8-13.) The 8 lines comprising the Data Bus 201 can be either input or output. Any device on the Nl-Bus 101 can be a source or a destination. In the Output state, data is clocked out at the primary data rate; data valid is indicated by a low-to-high transition on the Data Clock 301 line. This signal meets the requirements set forth in the timing diagrams, Figs. 8-13. In the Input state, data will be read by the Input Control section at each low-to-high transition of the Data Clock line. Note that this signal is the responsibility of the driving peripheral.

A low-to-high transition on the Packet Start line 305 indicates to the Input Section, if the Nl 105 is the destination, that the Data Bus 201 should be read on the next low-to-high transition of the Data Clock 301. Bytes will be read on each low-to-high transition of this clock until the Packet Start 305 line goes low. The Packet End 307 line is normally low. It will be driven high by the Input Control when one of three things occurs: 1 ) the Network Interface has received the entire packet based on the packet length contained in the header; 2) Max Packet Size is less than the Packet Length; or 3) the packet header has a CRC error. Referring now to Fig. 4, the definition of the bits in the Control Bus

203 are shown. Bit 7 (401) is an address flag; if this bit is a 'one', the low- order bits are interpreted as a Nl-Bus Peripheral address. If it is a 'zero', the byte is a command, or associated data. Address Bytes are therefore those bytes in which bit 7 is a 'one'. Referring now to Fig. 5, the layout of an Address Byte is shown. Bit 6 (501) is a 'use and clear" flag; if this bit is set, the Network Interface will output the entire byte to the Control Bus 203, and then clear bit 7. Thus, the associated Nl-Bus command (to some peripheral) will only be executed once. If bit 6 is a 'zero' bit, bit 7 will not be altered, causing the associated command to be executed on each cycle of the frame.

Bits 5 through 0 (503) form a peripheral address that is to be recognized by a Nl-Bus device. The address 'zero' (binary '000000') is reserved as an 'all call', and therefore is to be recognized by all Nl-Bus devices. The address One' (binary '000001') is to be recognized by all Nl-Bus devices except for the Network Interface 105. This can be used by the Nl 105 to reset all devices on the Nl-Bus101 except for itself.

Table 1 contains the currently-defined device addresses.

Device Binary Value

Broadcast Address 000000

Broadcast Address excluding Nl 000001

Network Interface 000010

Primary Radio 000100

Secondary Radio 000101

Primary LAN 0001 10

Secondary LAN 0001 1 1

Phone Interface 001000

Table 1 Nl-Bus Control Addresses

Fig. 6 shows the layout of a Command Byte 600. A Command Byte is a byte that is immediately preceded by an Address Byte. Bit 7 is 'zero'. The remaining 7 bits 601 may be used to form any command appropriate to the peripheral addressed; the commands recognized by the Network Interface are shown in Table 2 below. Note that "No-op" and "Reset" commands should be recognized by all devices; this will allow al! Nl-Bus Devices to be reset by a single instruction composed of an address of OOOOOO' and a command of '000001 '. If all devices except for the Nl are to be reset, an address of '000001' would be used.

Table 2 contains possible commands that all devices on the Nl- Bus may recognize.

Description Binary Value Comments No Operation 000000 Reset 000001 Reset the specified Nl-Bus device.

Bus Source 000010 Specifies the Nl-Bus device that will drive the Nl Data Bus. Bus Destination 000100 Specifies the Nl-Bus device that will listen to the Nl Data Bus. Clear Nl Bus 000101 Tells Nl-Bus device or devices not to listen to the Nl Data Bus. Skip 'n' Clock Cycles 000110 Wait 'n' clocks before next instr. Address will always be the Nl. 'n' is contained in two Control Data Bytes following the command.

Table 2 - Nl-Bus Control Commands

The above commands, along with the addresses, control the Data Bus 201. The addresses and commands are stored in the Control Memory 211 by the Control Processor 107. The output control portion of the Network Interface cycles through the Control Memory 211 and puts the addresses and commands on the Control Bus 203. The timing of the output of control information to the frame is based on where in the Control Memory 211 an address/command is placed and the 'Skip 'n' Clocks' command.

There may be additional commands that are specific to a given device. These may include special commands for the radio such as antenna selection, turning the transmitter on and off, etc. These commands may be defined by the specifications for each of the Nl-Bus devices.

Fig. 7 depicts the layout of a Control Data Byte 700. The Control Data Byte is used to pass additional information to a Nl-Bus device. It looks much the same as a Command Byte 600; bit 7 is zero, but bits 0 through 6 (701 ) are used to pass specific data to a Nl-Bus device. The Control Data Byte(s) will always follow a Command Byte, but not all Command Bytes are followed by a Control Data Byte. There can be any number of Control Data Bytes following a Command Byte. A given Command has a specific number of Control Data Bytes following it.

The 'Skip 'n' Clocks' command uses two Control Data Bytes to tell the Network Interface 105 how many clocks to wait. N is 12 bits. The first Control Data Byte contains the lower 6 bits of the c©unt and the second, the upper 6 bits. The number of clocks that the 'Skip' instructions skips begins after the second Control Data Byte. In other words, a 'Skip 'n' Clocks' where 'n' is zero will skip 4 clocks.

A simple example of what may be in the Control Memory 211 is shown in Table 3.

Description Binary Value Nl-Bus Destination 10000010 00000101

Radio - Bus Source 10000100 00000100 Skip 200 Clocks 10000010 00000111 00001000 00000011

Clear Nl Bus 10000000 00000110

Radio - Bus Destination 10000100 10000010

Nl - Bus Source 10000010 00000100

Table 3 - Control Memory Example

The Network Interface Specifications are shown in Figs. 8-13.

The Network Interface Bus (Nl-Bus) Signals are described below.

The Data Bus 201 comprises 8 lines designated ND0 through

ND7. - These 8 three-state, bi-directional lines are the path for transferring data between the Network Interface 105 and peripheral devices connected to the Nl-Bus 101. The Control Bus 203 comprises 8 lines designated NC0 through

NC7 - These 8 three-state output lines are for addressing/commanding devices connected to the Nl-Bus 101.

The Control Clock (CCLK) line 303's output signal, when high, indicates that there is valid Control information on the Control Bus 203. The Data Clcck (DCLK) line 301 's signal, when high, indicates that there is valid data on the Nl Data Bus 201. The device driving the Nl Data Bus 201 is responsible for driving this signal.

The Packet Start (PS) 305's input signal goes high and remains high while data is being sent from a peripheral device. The signal 305 will go low after Packet End 307 signal goes low. The device driving the Data Bus 201 drives the Packet Start signal.

The Packet End (PE) 307's output signal goes high to inform the peripheral device that all valid packet data has been received and that extra data bytes, if any exist, may be transmitted. The signal 307 goes low when all additional bytes have been received. The signal will go high if a Max Packet Size or CRC error occurs.

The Timing Specification is described as follows: Refer to Figs. 8-13.

Fig. 8 shows ".he control clock 303 timing.

Fig. 9 s.iows he packet start 305 and data clock 301 timing.

Fig. 10 shows the packet end 307 and packet start 305 timing, for the case of a va.'d packet with additional bytes. Fig. 11 shows the packet end 307 and packet start 305 timing, for the case of a valid packet with no additional bytes.

Fig. 12 shows the packet end 307 and packet start 305 timing, for the case of a maximum packet size error.

Fig. 13 shows the packet end 307 and packet start 305 timing, for the case of a CRC error.

The maximum rise and fall times for CCLK 303, DCLK 301 , PS 305, and PE 307 ai 5 nanoseconds. Rise and fall times are from 10% to 90%. All times are ypical unless otherwise noted.

While various embodiments of a parallel control for a packet/fast packet switch, according to the invention, have been described herein, the scope of the invention is defined by the following claims.

Claims

What is claimed is:Claims:

1. A parallel control arrangement for a packet/fast packet switch comprising a network interface (105) that is arranged for providing time- division and fast-packet switching for voice/data packets coupled to at least one peripheral device via a network interface (Nl) bus (101 ), said Nl bus (101 ) comprising at least a control bus (203) and a data bus (201 ).

2. The parallel control arrangement for a packet/fast packet switch of claim 1 wherein said control bus (203) is uni-directional.

3. The parallel control arrangement for a packet/fast packet switch of claim 2 wherein said data bus (201) is bi-directional.

4. The parallel control arrangement for a packet/fast packet switch of claim 3 wherein the control bus (203) controls which of said peripheral devices is driving the Nl bus (101) and which is listening.

5. The parallel control arrangement for a packet/fast packet switch of claim 4 wherein said Nl bus (101) includes a control clock line (303) and a data clock line (301).

6. The parallel control arrangement for a packet/fast packet switch of claim 5 wherein said Nl bus (101) includes a packet start line (305) and a packet end line (307).

7. The parallel control arrangement for a packet/fast packet switch of claim 6, said data bus (201 ) further arranged for passing time division multiple access (TDMA) packets at a rate of up to 40 MBps, each packet containing both voice and data information.

8. The parallel control arrangement for a packet/fast packet switch of claim 7, said data bus (201 ) being further arranged for passing TDMA packets that comprise the following fields: a circuit identification (ID) field, a packet length field, an address type field, an address length field, an address field, a frame-check sequence (CRC) field, and, an information field.

9. The parallel control arrangement for a packet/fast packet switch of claim 8, said data bus (201) further including 8 lines.

10. The parallel control arrangement for a packet/fast packet switch of claim 9, said control bus (203) further including 8 lines.