US9710399B2 - Systems and methods for flushing a cache with modified data - Google Patents
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- US9710399B2 US9710399B2 US13/561,491 US201213561491A US9710399B2 US 9710399 B2 US9710399 B2 US 9710399B2 US 201213561491 A US201213561491 A US 201213561491A US 9710399 B2 US9710399 B2 US 9710399B2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/12—Replacement control
- G06F12/121—Replacement control using replacement algorithms
- G06F12/128—Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/12—Replacement control
- G06F12/121—Replacement control using replacement algorithms
- G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0808—Multiuser, multiprocessor or multiprocessing cache systems with cache invalidating means
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- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/12—Replacement control
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- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/28—Using a specific disk cache architecture
- G06F2212/283—Plural cache memories
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- G06F2212/60—Details of cache memory
- G06F2212/608—Details relating to cache mapping
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Definitions
- a cache in a central processing unit is a data storage structure that is used by the central processing unit of a computer to reduce the average time that it takes to access memory. It is a memory which stores copies of data that is located in the most frequently used main memory locations. Cache memory is memory that is smaller in storage capacity than main memory but is memory that can be accessed much more quickly.
- a cache is considered to be full when it does not have space available to accommodate incoming data.
- writes to the cache can be prevented from proceeding. Accordingly, write stalls can occur until a successful write-back or flushing of data that is maintained in the cache is executed and space is created to accommodate the incoming data.
- Cache flushing removes an entry or entries from the cache such that space is freed for incoming data.
- the removal can be from the cache to a next level cache. This can be done either manually or automatically.
- Some conventional caches are organized such that the contents of a lower level cache are contained in a next higher level cache. Such organization can provide performance advantages and disadvantages.
- some higher level caches may not include the contents of the lower level cache.
- the cache line entries of a lower level cache with modified data may not be included in the next level cache.
- a problem can arise when cache line entries of a cache with modified data that are not included in a next level cache needs to be flushed from the cache with modified data to the next level cache. If a lower level cache is included in a higher level cache, it is enough to flush the higher level cache to the next higher level cache (relative to itself) or main memory. When a lower level cache is not included in a higher level cache, the flush operation of this higher level cache cannot simultaneously effect the flushing of the lower level cache as well.
- a conventional approach to flushing cache line entries from a cache with modified data to a next level cache in such circumstances is to stop the traffic on one of the ports of the cache with modified data and to inject flush requests from that port to write-back cache line entries from the cache with modified data one index and way at a time.
- this approach can have adverse timing impacts and has the potential to degrade performance.
- this approach can require a complex implementation.
- a method for flushing data from a lower level cache (a cache with modified data in one embodiment) to a higher level (e.g., a next level cache) is disclosed that addresses these shortcomings.
- the claimed embodiments are not limited to implementations that address any or all of the aforementioned shortcomings.
- the cache with modified data is accessed using an index and a way to secure the address associated with that index and the way.
- the cache with modified data is accessed a second time and an entry that is associated with the address is retrieved from the cache with modified data.
- the entry is placed into a location of the next level cache.
- FIG. 1A shows an exemplary operating environment of a system for flushing a cache with modified data according to one embodiment.
- FIG. 1B illustrates, responsive to a request to access a level two cache, the accessing of a store coalescing cache using an index and a way to obtain an address corresponding to data that is to be flushed to a level two cache according to one embodiment.
- FIG. 1C illustrates operations performed by a system for flushing a cache with modified data according to one embodiment.
- FIG. 2 shows components of a system for flushing a cache with modified data according to one embodiment.
- FIG. 3 shows a flowchart of the steps performed in a method for flushing a cache with modified data according to one embodiment.
- references within the specification to “one embodiment” or “an embodiment” are intended to indicate that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention.
- the appearance of the phrase “in one embodiment” in various places within the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments.
- various features are described which may be exhibited by some embodiments and not by others.
- various requirements are described which may be requirements for some embodiments but not other embodiments.
- FIG. 1A shows an exemplary operating environment 100 of a system 101 for flushing a cache with modified data according to one embodiment.
- System 101 directs, in response to a periodic request to flush data from a cache with modified data to a next level cache that does not include the cache with modified data, an access of the cache with modified data based on an index and way to secure (e.g., identify) an address associated with the data to be flushed. Subsequently, the address is used to access the cache with modified data a second time to obtain the data to be flushed, which is then written into a location (e.g., index) of the next level cache.
- L1 cache 103 shows system 101 , L1 cache 103 , L1 store coalescing cache 103 a (e.g., cache with modified data), load cache 103 b , CPU 105 , L2 cache 107 (e.g., next level cache), L2 cache controller 107 a , main memory 109 and system interface 111 .
- store coalescing cache 103 a is termed “cache with modified data” as it maintains data that can be modified by stores that update or modify the data.
- L1 cache 103 is a level 1 cache and L2 cache 107 is a level 2 cache.
- L1 cache 103 includes store coalescing cache 103 a and load cache 103 b .
- Store coalescing cache 103 a maintains entries that are accessed by store request and load cache 103 b maintains entries that are accessed by load requests.
- store coalescing cache 103 a is a part of L1 cache 103 but is not included in L2 cache 107 (e.g., the next level cache).
- Requests to flush data from store coalescing cache 103 a to L2 cache 107 which are received by L2 cache 107 involve obtaining an address from store coalescing cache 103 a before store coalescing cache 103 a can be probed for the information associated with the address.
- the access of store coalescing cache 103 a is facilitated by a probe that couples L2 cache 207 and store coalescing cache 103 a (see FIG. 1B ).
- requests to flush store coalescing cache 103 a to L2 cache 107 can cause stalls in the absence of a mechanism for facilitating the acquisition by L2 cache 107 of information that is needed to flush data from store coalescing cache 103 a to L2 cache 107 .
- this mechanism is provided by system 101 , which as a part of its operation directs a securing of information from store coalescing cache 103 a that is needed to access store coalescing cache 103 a at the pipeline speed of L2 cache 107 .
- L2 cache 107 controls the probe that is used to access and read data from store coalescing cache 103 a.
- system 101 responsive to a request to flush data from store coalescing cache 103 a to L2 cache 107 , directs a probe of store coalescing cache 103 a using an index and a way to secure an address corresponding to data that is to be flushed to L2 cache 107 (see arrows corresponding to pipeline in FIG. 1B ).
- the access of store coalescing cache 103 a is facilitated by probe 113 that is controlled by L2 cache 107 .
- the address is provided to L2 cache 107 .
- system 101 can be located in cache controller 107 a . In other embodiments, system 101 can be separate from cache controller 107 a , but operate cooperatively therewith.
- main memory 109 includes physical addresses that store the information that is copied into cache memory.
- the corresponding cached information is updated to reflect the changes made to the information stored in main memory.
- system interface 111 Also shown in FIG. 1A is system interface 111 .
- FIG. 1C illustrates operations performed by a system for flushing a cache with modified data according to one embodiment. These operations, which relate to flushing a cache with modified data are illustrated for purposes of clarity and brevity. It should be appreciated that other operations not illustrated by FIG. 1C can be performed in accordance with one embodiment.
- a request to flush data that is present in a cache with modified data (e.g., store coalescing cache 103 a in FIG. 1A ) that corresponds to a specific address is received.
- a probe of the cache with modified data (e.g., store coalescing cache 103 a in FIG. 1A ), using the index and way where the data is located in the cache with modified data, is executed.
- the address in the cache with modified data (e.g., store coalescing cache 103 a in FIG. 1A ) residing at the aforementioned index and way is secured (e.g., identified) and provided to a next level cache (e.g., L2 cache 107 in FIG. 1A ).
- the address is used to probe the cache with modified data a second time to obtain the data associated with the address.
- the data associated with the address in the cache with modified data is obtained and provided to the next level cache.
- the data is placed into a location of the next level cache.
- the flushing of a cache with modified data can be done periodically while the cache is idling and no stores are incoming.
- FIG. 2 shows components of a system 101 for flushing a cache with modified data according to one embodiment.
- components of system 101 implement an algorithm for flushing a cache with modified data.
- components of system 101 include flush request accessor 201 , cache probe 203 and writing component 205 .
- Flush request accessor 201 accesses a request to flush data from a cache with modified data to a next level cache.
- the request can be one of an on-going series of periodic requests to flush data from the cache with modified data.
- the flushing of data from the cache with modified data can be done to free up space for newer data based on the expectation that newer data will be received.
- the request is directed to the next level cache (e.g., an L2 cache).
- Cache probe 203 responsive to the request to flush data from a cache with modified data, accesses (e.g., probes) the cache with modified data using an index and a way and identifies an address associated with the index and way. Subsequently, using the address, cache probe 203 accesses (e.g., probes) the cache with modified data a second time and retrieves data that is located at the location that is indicated by the index and way.
- cache probe 203 accesses (e.g., probes) the cache with modified data a second time and retrieves data that is located at the location that is indicated by the index and way.
- Writing component 205 places the data that is retrieved into a location of the next level cache.
- the contents of the cache with modified data are not included in the next level cache and thus before an entry (e.g., cache line entry with data) from the cache with modified data can be flushed to the next level cache, the address associated with the entry is obtained such that the entry can be identified and flushed to the next level cache and placed into a location there as a new entry.
- components and operations of system 101 can be implemented in hardware or software or in a combination of both.
- components and operations of system 101 can be encompassed by components and operations of one or more computer components or programs (e.g., cache controller 107 a in FIG. 1A ).
- components and operations of system 101 can be separate from the aforementioned one or more computer components or programs but can operate cooperatively with components and operations thereof.
- FIG. 3 shows a flowchart 300 of the steps performed in a method for flushing a cache with modified data according to one embodiment.
- the flowchart includes processes that, in one embodiment can be carried out by processors and electrical components under the control of computer-readable and computer-executable instructions. Although specific steps are disclosed in the flowchart, such steps are exemplary. That is the present embodiment is well suited to performing various other steps or variations of the steps recited in the flowchart.
- a request to flush data from a cache with modified data to a next level cache is accessed.
- the request can be one of an on-going series of periodic requests that flush data from the cache with modified data.
- a cache with modified data is accessed using an index and a way.
- the index and way is used because the address associated with the desired entry is not available.
- an address associated with said index and said way is secured (e.g., identified) from the cache with modified data.
- the securing of the address enables a subsequent retrieval of the entry associated with the address.
- the cache with modified data is accessed a second time.
- the access of the cache with modified data (in both 305 and 307 ) is executed using a probe that is controlled by the next level cache.
- data is retrieved that is associated with the address. And, at 311 , the data is written into a location of the next level cache.
- systems and methods for flushing a cache with modified data are disclosed. Responsive to a request to flush data from a cache with modified data to a next level cache that does not include the cache with modified data, the cache with modified data is accessed using an index and a way and an address associated with the index and the way is secured. Using the address, the cache with modified data is accessed a second time and an entry that is associated with the address is retrieved from the cache with modified data. The entry is placed into a location of the next level cache.
Abstract
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US13/561,491 US9710399B2 (en) | 2012-07-30 | 2012-07-30 | Systems and methods for flushing a cache with modified data |
PCT/US2013/051128 WO2014022115A1 (en) | 2012-07-30 | 2013-07-18 | Systems and methods for supporting a plurality of load accesses of a cache in a single cycle |
TW102127066A TWI537731B (en) | 2012-07-30 | 2013-07-29 | Systems and methods for supporting a plurality of load accesses of a cache in a single cycle |
US15/353,053 US9858206B2 (en) | 2012-07-30 | 2016-11-16 | Systems and methods for flushing a cache with modified data |
US15/823,432 US10210101B2 (en) | 2012-07-30 | 2017-11-27 | Systems and methods for flushing a cache with modified data |
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US10210101B2 (en) | 2019-02-19 |
US20140032844A1 (en) | 2014-01-30 |
US20180081822A1 (en) | 2018-03-22 |
US20170228323A1 (en) | 2017-08-10 |
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