US7240250B2 - Head degradation characterization for a data storage device - Google Patents
Head degradation characterization for a data storage device Download PDFInfo
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- US7240250B2 US7240250B2 US10/458,633 US45863303A US7240250B2 US 7240250 B2 US7240250 B2 US 7240250B2 US 45863303 A US45863303 A US 45863303A US 7240250 B2 US7240250 B2 US 7240250B2
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- gain control
- vga
- control value
- head
- read channel
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
Definitions
- This invention relates generally to the field of magnetic data storage devices, and more particularly, but not by way of limitation, to identifying degradation of a head of a data storage device based on a change in gain applied to a read signal by a variable gain amplifier.
- Data storage devices are used for data storage in modern electronic products ranging from digital cameras to network systems.
- a data storage device includes a mechanical portion, or head disc assembly, and electronics, or printed circuit board assembly, mounted to the head disc assembly.
- the printed circuit board assembly controls functions of the head disc assembly while providing a communication interface between the data storage device and its host.
- the head disc assembly has a disc rotated at a constant speed by a spindle motor assembly and a position controllable actuator assembly, which supports a data transducing head that selectively writes data to and reads data from the disc.
- the data storage device market continues to place pressure on the industry for data storage devices with improved reliability. Degradation in read/write head performance at customer sites continues to pose a reliability issue for customers.
- a method and apparatus are provided for characterizing whether a head of a data storage device exhibits excessive performance degradation.
- the method preferably includes determining a baseline variable gain amplifier (VGA) gain control value for the head, the baseline VGA gain control value operatively normalizing an amplitude of a readback signal from the head to a selected range suitable for decoding by read channel circuitry.
- VGA variable gain amplifier
- the read channel circuitry is next parametrically adapted to optimize read error performance, and an adaptive VGA gain control value for the head is obtained.
- the head is thereafter characterized as exhibiting excessive degradation when the adaptive VGA gain control value exceeds a predetermined VGA value threshold, else when a difference between the adaptive VGA gain control value and the baseline VGA gain control value exceeds a predetermined delta VGA value threshold.
- the head is removed and replaced with a second head when the original head is found to exhibit excessive degradation.
- the head is adjudged as a good head (i.e., exhibiting non-degradation) when the magnitude of the VGA gain control value, and the difference, do not exceed the respective thresholds.
- the method is preferably carried out in a manufacturing environment prior to shipment of the device to a customer.
- the apparatus preferably comprises a data storage device having a data transducing head adjacent a recording medium.
- Read channel circuitry is coupled to the head and comprises a variable gain amplifier and a gain control block.
- the gain control block operably supplies VGA gain control values to the VGA to nominally maintain amplitudes of readback signals obtained from the head within a selected range suitable for remaining portions of the read channel circuitry.
- a controller coupled to the read channel circuitry operates to determine a baseline VGA gain control value, perform a parametric adaptation of the read channel circuitry, and then obtain an adaptive VGA gain control value.
- the controller further operates to characterize the head as exhibiting excessive degradation in relation to a magnitude of the adaptive VGA gain control value and in relation to a difference between the adaptive VGA gain control value and the baseline VGA gain control value.
- the device operates in conjunction with a monitoring system and the results of the characterization operation are displayed on a monitor.
- the characterization preferably occurs during device manufacturing, enabling the device manufacturer to remove and replace degraded heads prior to shipment of the device to the customer.
- FIG. 1 is a top plan view of a data storage device constructed and operated in accordance with preferred embodiments of the present invention to identify heads exhibiting excessive head degradation.
- FIG. 2 is a functional block diagram of the device of FIG. 1 in conjunction with a host computer.
- FIG. 3 is a disproportionately scaled, elevational view of a combination for characterizing levels of degradation of the heads of the device of FIG. 1 .
- FIG. 4 is a flow chart generally representative of steps carried out in accordance with preferred embodiments to characterize the heads of the device of FIG. 1 .
- FIG. 1 provides a top plan view of a data storage device 100 .
- the data storage device 100 includes a rigid base deck 102 , which cooperates with a top cover 104 (shown in partial cutaway) to form a sealed housing for a mechanical portion of the data storage device 100 (also referred to as disc drive 100 ).
- a mechanical portion of the data storage device 100 also referred to as disc drive 100
- the mechanical portion of the data storage device 100 is referred to as a head-disc assembly 106 .
- a spindle motor 108 rotates a number of magnetic data storage discs 110 at a constant high speed, each disc 110 having at least one recording surface 111 .
- a rotary actuator 112 supports a number of data transducing heads 114 adjacent the discs 110 . The actuator 112 is rotated through application of current to a coil 116 of a voice coil motor (VCM) 118 .
- VCM voice coil motor
- the actuator 112 moves the heads 114 to data tracks 120 , one shown (also referred to as an information track) on the surfaces of the discs 110 to write data to and read data from the discs 110 .
- the actuator 112 removes the heads 114 from the data tracks 120 to a home position 122 of the disc 110 ; the actuator 112 is then confined by latching a toggle latch 124 .
- Command and control electronics as well as other interface and control circuitry for the data storage device 100 , are provided on a printed circuit board assembly 126 mounted to the underside of the base deck 102 .
- a preamplifier/driver circuit (preamp) 128 conditions read/write signals passed between the command and control electronics of the printed circuit board assembly 126 and the head 114 .
- the preamp 128 is attached to a flex circuit 130 , which conducts signals between the printed circuit board assembly 126 and the head 114 during data transfer operations.
- FIG. 2 shown therein is a functional block diagram of the device 100 .
- Position-controlling of the head 114 is provided by the VCM 118 ( FIG. 1 ) operating under the control of a closed-loop servo control circuit 132 programmed with servo control code.
- the servo control circuit 132 generally includes a microprocessor controller 134 , associated memory 136 with buffer 138 , a demodulator (DEMOD) circuit 140 , a servo engine 142 , a digital to analog converter (DAC) 144 and a motor driver circuit 146 .
- the controller 134 , the memory 136 , and the servo engine 142 are incorporated into an application specific integrated circuit (ASIC).
- the buffer 138 is used to store information collected or calculated during operation of the data storage device 100 .
- the demodulator 140 conditions head position control information transduced from the information track 120 of the disc 110 to provide position information of the head 114 relative to the disc 110 .
- the servo engine 142 generates servo control loop values used by the controller 134 in generating command signals such as seek signals used by the voice coil motor 118 in executing seek commands. Control loop values are also used to maintain a predetermined position of the actuator 112 during data transfer operations.
- the command signals generated by the controller 134 and passed by the servo engine 142 are converted by the DAC 144 to analog control signals.
- the analog control signals are used by the motor driver circuit 146 to control application of current to the coil 116 .
- Device control code is preferably provided to control data transfer functions between a host computer 148 and the data storage device 100 .
- Data received from the host 148 to be stored to the discs 110 are placed in the memory 136 for transfer to the disc 110 by write channel circuitry of a read/write (R/W) channel 150 , which operates under control of the controller 134 and interface hardware 152 .
- Read data requested by the host 148 are read by the head 114 from the associated track 120 , decoded by read channel circuitry of the R/W channel 150 and temporarily placed in the memory 136 awaiting subsequent transfer to the host.
- the device control code further preferably includes idle interface activated commands such as seek to improve reliability (STIR) control code.
- the STIR control code initiates a seek sequence during periods of inactivity of the data storage device 100 to carry out a number of operational enhancement functions such as clearing accumulated debris from the heads 114 and surfaces 111 , dithering to periodically move different heads to different tracks to minimize localized wear patterns, and so on.
- the device control code also preferably includes factory command code used for testing and certifying the data storage device 100 during the production process.
- the factory command code provides access to regions of the disc 110 unavailable to the customer, allows suspension of interface commands resident in the device control code and provides an ability to structure command sequences normally unavailable to customers.
- this operation serves to characterize whether or not a particular head 114 is likely to degrade and become inoperable over the life of the data storage device 100 , allowing such head to be removed and replaced prior to shipment of the device 100 to the customer.
- the head 114 provides a readback signal to the preamp 128 that, upon amplification of the readback signal, provides an input signal to the R/W channel 150 .
- the input signal is provided to an automatic gain control (AGC) stage comprising a variable gain amplifier (VGA) 160 and a gain control block 162 .
- AGC automatic gain control
- the AGC stage is used to normalize the gain (peak to peak amplitude) of the input signal during read operations to a nominal range suitable for subsequent sampling and decoding by the R/W channel 150 .
- the gain control block 162 evaluates and, as needed, adjusts the magnitude of a variable gain control value (herein “VGA value”) supplied to the VGA 160 .
- VGA value a variable gain control value supplied to the VGA 160 .
- the VGA 160 operates upon the amplified readback signal to provide a substantially constant amplitude output signal to facilitate decoding of information contained in the readback signal.
- the R/W channel 150 upon initialization of the data storage device 100 , performs a self-gain adaptation of an input signal to determine an initial VGA value, which is placed in a first register 164 . This is preferably carried out using a selected head 114 to read a prewritten data pattern on a selected track.
- An initial VGA value is provided to the VGA 160 , and a series of readback signals are provided to the VGA. The initial VGA gain value is thereafter converged to the final, baseline VGA value in relation to the detected peak-to-peak amplitudes of the series of readback signals.
- the head 114 If the head 114 is unable to sufficiently stay on track during the reading of the prewritten data pattern (due to servo errors or other conditions), the head 114 is repositioned over an alternate information track 120 and the process is repeated until an optimized VGA value is found.
- the self-gain adaptation procedure is repeated for each head 114 present in the data storage device 100 with the resulting baseline VGA values for each head stored in the buffer memory 138 .
- Table 1 provides an illustrative example of representative baseline VGA values obtained for a device (such as 100 ) having a total of four discs 108 and eight heads 114 (numerically denoted as heads 0-7).
- the baseline VGA values are unitless gain values. The particular ranges and magnitudes of VGA values will depend upon the configuration of a particular device.
- the baseline VGA values are obtained during initial stages of manufacturing test operations performed upon the assembled device 100 .
- the predetermined test patterns are preferably oscillatory (such as 2T) patterns written to guard tracks not normally accessed during operation, although other approaches can readily be used.
- R/W channel 150 will be sufficiently configured to self adjust during operation to achieve minimum readback errors.
- the head characterization process continues with the determination of so-called adaptive VGA values for each head.
- the adaptive VGA values preferably comprise average values determined after a relatively extensive reading of data from a number of different tracks across the radii of the discs 110 .
- the absolute magnitude of the resulting adaptive VGA values serve to allow characterization of a particular head as constituting a long term reliability risk for the device 100 , allowing replacement of the head prior to device shipment.
- the adaptive VGA value for each head 114 is determined as follows. A first head 114 is selected and positioned over a first track 120 , and the head is used to read a selected number of data sectors from the track. The resulting VGA value from the first track, denoted herein as VGA(track1, head1), is temporarily stored.
- ADP_VGA — 1 A first intermediate average VGA value, denoted herein as ADP_VGA — 1, is then preferably calculated in accordance with the following relationship:
- ADP_VGA ⁇ _ ⁇ 1 ⁇ [ VGA ⁇ ( trackn , head ⁇ ⁇ 1 ) ] n ( 1 )
- the process is preferably sequentially repeated N number of times for the first head, resulting in intermediate VGA values from ADP_VGA — 1 to ADP_VGA_N for the first head.
- a final adaptive VGA value for the first head is thereafter preferably calculated by dropping the highest and lowest intermediate values (min and max) and taking an average of the rest, such as by the following relationship:
- FINAL_ADP ⁇ _VGA ⁇ [ ADP_VGA ⁇ _N - min ⁇ ⁇ value - max ⁇ ⁇ value ] N - 2 ( 2 )
- This final adaptive VGA value is thereafter stored in a second register 166 ( FIG. 2 ), and the foregoing process is repeated for each of the remaining heads.
- Table 2 provides exemplary adaptive VGA values obtained for the heads of Table 1:
- the absolute magnitudes of the adaptive VGA values are compared to a predetermined threshold value, T1.
- T1 value is empirically determined and generally comprises an upper limit beyond which head performance is deemed to be excessively degraded.
- the next preferred step is to determine a delta, ⁇ (absolute magnitude difference) value for each head, as set forth by Table 3:
- the delta values are compared to a second predetermined threshold value, T2.
- T2 value is empirically determined and generally comprises an upper difference limit beyond which head performance is deemed to be excessively degraded.
- FIG. 3 shows the data storage device 100 configured for communication with a monitoring device 159 (it will be noted that the data storage device 100 and the monitoring device 159 are not drawn to the same scale).
- the monitoring device 159 includes an interface cable 163 secured between the data storage device 100 and a processing unit 165 .
- the processing unit 165 includes interface electronics (not shown separately), which communicates across the interface cable 163 with the data storage device 100 .
- the processing unit 165 also communicates with a display module 167 that is used to display the results from the execution of head degradation characterization code in accordance with the flow chart of FIG. 4 .
- FIG. 4 shows a HEAD DEGRADATION CHARACTERIZATION routine 200 , representative of the head degradation characterization code used to characterize a level of degradation of the heads 114 of the device 100 .
- the routine 200 is preferably carried out during device manufacturing, and is executed after the device 100 has been placed into an operational ready condition (i.e., the device electronics have been initialized, the discs 110 have been accelerated to a rotational velocity sufficient to aerodynamically support the heads 114 , the heads have been moved out over the associated disc surfaces 111 , etc.).
- factory commands are unlocked (activated), while functions of the device control code utilized during periods of idle time of the interface hardware 148 are suspended (i.e., commands that are activated when the interface or bus are idle are set to inactive). This prepares the device 100 for ensuring steps in the routine to be performed without interruption by active mode or idle mode commands.
- the head degradation characterization code instructs the controller to acquire a baseline VGA value (denoted as “VGA1” in FIG. 4 ) for each of the heads 114 in turn, in a manner as discussed above.
- the baseline VGA1 values for the heads are stored in the buffer 138 by the conclusion of this step.
- step 206 conventional certification and test routines are next carried out during step 206 to certify and establish proper parametric adaptation of various circuits of the device 100 , including the R/W channel 150 .
- Such parametric adaptation of the R/W channel 150 will depend upon the configuration of the channel, but will generally include operations such as setting adaptive filtering parameters in a low pass filter, selection of appropriate tap weights for a finite impulse response (FIR) filter, optimization of various Viterbi detector sampling threshold parameters, etc. It will be contemplated that at the conclusion of step 208 , the R/W channel 150 has configured to provide optimum error rate performance (i.e., to adaptively reduce read back errors to a sufficiently low level).
- a first head 114 is selected at step 208 , and at step 210 a final adaptive VGA value (denoted as “VGA2”) is determined for the selected head in a manner as discussed above. This value is stored in the second register 166 .
- the adaptive VGA value VGA2 is compared to the T1 threshold.
- VGA2 exceeds the T1 threshold, the head is characterized as having excessive degradation, as shown by step 214 .
- VGA2 does not exceed T1
- the flow continues to decision step 216 where the absolute magnitude of the difference between the VGA1 and VGA2 values is compared to the T2 threshold.
- the head When the T2 threshold is exceeded, the head is characterized as having excessive degradation (step 214 ), otherwise the head is characterized as exhibiting non-excessive degradation (i.e., a “good” head), as shown by step 218 .
- the routine determines at decision step 220 whether additional heads remain to be evaluated, and if so, the process selects the next head at step 222 and returns as described above for each additional head in turn. Once all the heads have been evaluated, the routine continues to step 224 where the baseline, adaptive and delta VGA values are displayed on the display module 167 .
- step 226 Any heads 114 exhibiting excessive degradation are thereafter removed and replaced, as shown by step 226 , and the routine ends at step 228 .
- embodiments of the present invention are generally directed to a method and apparatus for characterizing a data transducing head (such as 114 ) of a data storage device (such as 100 ) as exhibiting either excessive or non-excessive degradation.
- the method preferably includes determining a baseline variable gain amplifier (VGA) gain control value for the head (such as by step 204 ), the baseline VGA gain control value operatively normalizing an amplitude of a readback signal from the head to a selected range suitable for decoding by read channel circuitry.
- VGA variable gain amplifier
- the read channel circuitry is next parametrically adapted to optimize read error performance (such as by step 206 ), and an adaptive VGA gain control value for the head is obtained (such as by step 208 ).
- the head is thereafter characterized as exhibiting excessive degradation when the adaptive VGA gain control value exceeds a predetermined VGA value threshold (such as by steps 212 , 214 ), else when a difference between the adaptive VGA gain control value and the baseline VGA gain control value exceeds a predetermined delta VGA value threshold (such as by steps 216 , 214 ).
- the head is removed and replaced with a second head when the original head is found to exhibit excessive degradation (such as by step 226 ).
- the head is adjudged as a good head (i.e., exhibiting non-degradation) when the magnitude of the VGA gain control value, and the difference, do not exceed the respective thresholds.
- the method is preferably carried out in a manufacturing environment prior to shipment of the device to a customer.
- the apparatus preferably comprises a data storage device (such as 100 ) having a data transducing head (such as 114 ) adjacent a recording medium (such as 110 .
- Read channel circuitry (such as 150 ) is coupled to the head and comprises a variable gain amplifier (VGA, such as 160 ) and a gain control block (such as 162 ).
- the gain control block operably supplies VGA gain control values to the VGA to nominally maintain amplitudes of readback signals obtained from the head within a selected range suitable for remaining portions of the read channel circuitry.
- a controller (such as 136 ) coupled to the read channel circuitry operates to determine a baseline VGA gain control value, perform a parametric adaptation of the read channel circuitry, and then obtain an adaptive VGA gain control value.
- the controller further operates to characterize the head as exhibiting excessive degradation in relation to a magnitude of the adaptive VGA gain control value and in relation to a difference between the adaptive VGA gain control value and the baseline VGA gain control value.
- the device operates in conjunction with a monitoring system (such as 159 ) and the results of the characterization operation are displayed on a monitor (such as 167 ).
- a monitoring system such as 159
- a monitor such as 167
Abstract
Description
TABLE 1 | |||
BASELINE | |||
HEAD | VGA VALUE | ||
0 | 109 | ||
1 | 117 | ||
2 | 089 | ||
3 | 109 | ||
4 | 096 | ||
5 | 075 | ||
6 | 097 | ||
7 | 104 | ||
TABLE 2 | ||
BASELINE | ADAPTIVE | |
HEAD | VGA VALUE | VGA VALUE |
0 | 109 | 127 |
1 | 117 | 111 |
2 | 089 | 086 |
3 | 109 | 102 |
4 | 096 | 093 |
5 | 075 | 117 |
6 | 097 | 095 |
7 | 104 | 094 |
TABLE 3 | |||||
BASELINE | ADAPTIVE | DELTA | |||
HEAD | VGA VALUE | VGA VALUE | (Δ) | ||
0 | 109 | 127 | 18 | ||
1 | 117 | 111 | 06 | ||
2 | 089 | 086 | 03 | ||
3 | 109 | 102 | 07 | ||
4 | 096 | 093 | 03 | ||
5 | 075 | 117 | 42 | ||
6 | 097 | 095 | 02 | ||
7 | 104 | 094 | 10 | ||
Claims (9)
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US10/458,633 US7240250B2 (en) | 2002-08-29 | 2003-06-10 | Head degradation characterization for a data storage device |
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US40690302P | 2002-08-29 | 2002-08-29 | |
US10/458,633 US7240250B2 (en) | 2002-08-29 | 2003-06-10 | Head degradation characterization for a data storage device |
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US20040044939A1 US20040044939A1 (en) | 2004-03-04 |
US7240250B2 true US7240250B2 (en) | 2007-07-03 |
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Cited By (2)
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US20060259274A1 (en) * | 2005-05-10 | 2006-11-16 | International Business Machines (Ibm) Corporation | Monitoring and reporting normalized device system performance |
US8223448B1 (en) | 2010-04-22 | 2012-07-17 | Western Digital Technologies, Inc. | Disk drive calibrating preamp for servo sectors and data sectors |
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US7405893B2 (en) * | 2005-09-21 | 2008-07-29 | Seagate Technology Llc | Data storage medium with optimized servo format |
US8266426B2 (en) * | 2006-03-24 | 2012-09-11 | Red Hat, Inc. | Hardware certification based on certifying development processes |
JP2023531071A (en) | 2020-07-21 | 2023-07-20 | 株式会社アドバンテスト | Automated test equipment and method using device specific data |
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US8223448B1 (en) | 2010-04-22 | 2012-07-17 | Western Digital Technologies, Inc. | Disk drive calibrating preamp for servo sectors and data sectors |
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