US3654620A

US3654620A - Terminal device for data transmission with display facility and message format control

Info

Publication number: US3654620A
Application number: US868132A
Authority: US
Inventors: Antonio S Bartocci
Original assignee: Olivetti SpA
Current assignee: Telecom Italia SpA; Olivetti SpA
Priority date: 1968-10-23
Filing date: 1969-10-21
Publication date: 1972-04-04
Anticipated expiration: 1989-04-04
Also published as: DE1952175C3; DE1952175A1; DE1952175B2; FR2021395A1

Abstract

In a terminal device for the transmission of data, a display device is provided to display characters in a store contained in the terminal device. The position and format of displayed messages are adjustable by control of the location of storage of the data by means of a message format control. This latter is adapted to selectively generate a group of stop signals for defining a corresponding group of cells of the store; each one of said groups of cells corresponds to display positions defining a corresponding display format. The cells defined by the stop signals are decoded by decoder means and the characters are entered in them so that these characters are displayed in the positions of the display corresponding to the selected display format. Means are also provided which are operable for causing the characters following a predetermined flag signals to be shifted one step. Other means are provided for displacing the characters following said signal to be shifted to the next row of the display.

Description

United States Patent Bartocci [4 1 Apr. 4, 1972 [541 TERMINAL DEVICE FOR DATA 3,501,749 3/1970 Cuccio ..34o/172.5 TRANSMISSION WITH DISPLAY 3,516,069 6/1970 Bray et al v340/1125 FACILITY AND MESSAGE FORMAT CONTROL [72] inventor: Antonio S. Bartocci, lvrea, italy [73] Assignee: ing. C. Olivetti & C.,S.p.A., Torino, ltaly [22] Filed: Oct. 21, i969 [2i] Appl. No.: 868,i32

[30] Foreign Application Priority Data Oct. 23. i968 Italy ..S359l M68 [52] US. Cl ..340/172.5 [5 l int. Cl. ..G06i 3/14 [58] Field of Search ..340/l72.5, 324 A [56] References Cited UNITED STATES PATENTS 3,307,156 2/1967 Durr ..340/l72.5 3,382,487 5/1968 Sharon et al.... ..340/172.5 3,453,384 7/1969 Donner et al. ..340/172.5 X 3,466,645 9/1969 Granberg et al. ..340/l 72.5 X

SERIALIZER PARAliEllZE 16 Primary Examiner-Paul .l. Henon Assistant Examiner-Melvin B. Chapnick Attorney-Birch, Swindler, McKie and Beckett 5 7] ABSTRACT in a terminal device for the transmission of data, a display device is provided to display characters in a store contained in the terminal device. The position and format of displayed messages are adjustable by control of the location of storage of the data by means ofa message format control. This latter is adapted to selectively generate a group of stop signals for defining a corresponding group of cells of the store; each one of said groups of cells corresponds to display positions defin ing a corresponding display format. The cells defined by the stop signals are decoded by decoder means and the characters are entered in them so that these characters are displayed in the positions of the display corresponding to the selected display format. Means are also provided which are operable for causing the characters following a predetermined flag signals to be shifted one step. Other means are provided for displacing the characters following said signal to be shifted to the next row of the display.

8 Claims, 6 Drawing Figures TO CENTRA L P RDCESSOR Patented April 4, 1972 3,654,620

5 Shoots-Shut 1 r0 CENTRAL PROCESSOR v .7 PCS g5 c102 c1024 61 9 L A a M INVENTOR. ANTONIO BARTOCCI 5 Shasta-Shoot 5 Patented April 4, 1972 INVENTOR ANTONIO BARTOCCI Patented April 4, 1972 5 Shun-Shut 5 C335 ozrEmuzuo M306 an mm INVENTOR. ANTONIO BARTOCCI TERMINAL DEVICE FOR DATA TRANSMISSION WITH DISPLAY FACILITY AND MESSAGE FORMAT CONTROL GENERAL DESCRIPTION The present invention relates to a terminal interrogation and reply device, which can be connected to a central processor and is provided with means for displaying the information, for example a cathode ray tube.

In many known terminal devices of this type, the display on the luminous screen of the information emanating from the central processor connected through the transmission line, and of the replies given by the terminal device, is not subject to adequate means of control of the format allowing concise arrangement of the information displayed on the screen. On the other hand, known terminal devices with a display screen provided with a certain control over the format of the information displayed are weighed down by a superabundance of components and controlling members, which produce a consequent increase in the cost of the device and a certain operating slowness in the entire system.

The object of this invention is to overcome such disadvantages.

According to the present invention there is provided a terminal device for the transmission of data comprising a cyclic serial store and a timing device for producing timing signals which identify a succession of character cells in the store, a display device arranged to display characters in the store in an array of positions which are arranged in rows and correspond to predetermined character cells respectively, and selectively operable means responsive to the timing device to generate selectively two different combinations of stop signals which identify two different combinations of character cells and corresponding display positions defining two different display formats, and a control unit arranged to control the entry of characters in the store so that the characters are arranged in groups whose first or last characters are located in the cells identified by the stop signals.

According to the invention in another aspect there is provided a terminal device for the transmission of data comprising a cyclic serial store and a timing device for producing timing signals which identify a succession of character cells in the store, each consisting of a plurality of bit positions, a display device arranged to display characters in the store in an array of positions which are arranged in rows and correspond to predetermined character cells respectively, and a control unit arranged to introduce each character into the store in that cell which is marked by an identification bit and then to shift the identification bit automatically to the next cell, the control unit being further responsive to a key to shift by one cell all the characters in the store which follow the identification bit.

DETAILED DESCRIPTION The invention will be described in more detail, by way of example, with reference to the accompanying drawings, in which:

FIG. 1 shows the block diagram of an entire terminal device embodying the invention. FIG. 2 shows a time diagram relating to the division of the memory.

FIG. 3 shows a block diagram relating to the operations of extraction and insertion of data in the memory.

FIG. 4 shows a block diagram of the control and of the dis play device.

FIG. 5 shows a block diagram relating to the format functions with which the device embodying the invention is provided.

FIG. 6 shows a block diagram relating to the tabulating functions with which the device is provided.

With reference to FIG. 1, a keyboard 1 comprises alphabetical and numerical keys as well as function keys for the checking of the message. Each character issuing from the keyboard is transmitted on a channel 2 to a control unit 3 of the terminal unit. The control unit 3 interacts with a store 4 of the delay line type through the

channels

5 and 6, and with a control unit 7 for a cathode ray tube screen 10 through the

channels

8 and 9. A character is transmitted on the channel 5 to the store and at the same time on the channel 8 to the control unit 7 of the screen I0 in order to be displayed. A message thus inserted in the store 4 and displayed on the screen 10 remains at the disposal of a central processor connected through a transmission line 11 to the said terminal device.

When the central processor so requires, a line controller 12 commands the control unit 3 through the channel 13 to command the extraction of the message from the store 4. The message is extracted, character by character, through channel 6, passes through the control unit 3, and on the channel 14 it reaches the line controller 12, which transfers it through a channel 15 to a serializer-parallelizer 16. The message is serialized by the serializer l6 and is sent on a channel I7 to a modulator-demodulator or MODEM 18 which proceeds to modulate it and transmit it on the transmission line ll.

When, on the other hand, the central processor wishes to send a message to the terminal, the line control 12 establishes the reception mode, through which, when the terminal is ready to receive, the information bits received on the line I] and demodulated by the MODEM 18 are transmitted on a channel 19 to the parallelizer 16, which parallelizes them so as to recompose the individual characters which, via a channel 20, the line controller 12, the channel 13 and the control unit 3, reach the store 4 through the channel 5. The control unit 3 then has also the function of commanding the control unit 7 for the display of the characters on the screen 10.

The structure of the message exchanged between the ter minal and the central processor can be generally the same as already described in the specification of our U.S. Pat. application Ser. No. 764,708, filed Oct. 3, 1968, now U.S. Pat. No. 3,564,51 l.

The line controller 12 superintends the conversation procedure between processor and terminal. which can be in particular:

A "polling" procedure for the transmission of interrogatory messages from the terminal to the processor.

A selection procedure for the transmission of messages of reply from the processor to the terminal.

The two procedures being specified in the aforesaid Patent application, the description of them will not be repeated here. Also described in the aforesaid patent application is a line controller which is completely identical with the line controller 12. The store 4 is formed by a magnetostrictive delay line which has the capacity for a block of characters. In particular, FIG. 2, each memory cycle T comprises L024 digit periods from C1 to C1024, each comprising 10 bit periods from D1 to D10. Each character in the store is represented by seven bits stored respectively in the seven binary positions corresponding to the bit periods from D3 to D9. The binary position corresponding to the bit period D10 contains a parity bit for the character. The binary position corresponding to the bit period DI can contain a service bit bs=l, which, in the operation of writing in the store, is progressively shifted by one digit period (store cell) to the next, in order to indicate progressively which is the store cell (digit period) into which the next characters require to be inserted.

Similarly the binary position corresponding the second bit period D2 can contain a service bit b1=l, which in the reading operations from the store, is progressively shifted from one digit period to the next in order to indicate which is the store cell where the next character to be extracted from the store is to be read.

Present in front of the L024 times 10 binary positions of the store is a binary position adapted to contain a starting bit CS for the timing and a binary position containing the key parity bit PCS.

The screen of the cathode ray tube 10 permits the display in particular of 56 character positions in each of 16 rows. The individual character positions on the screen clearly correspond with the respective cells present in the delay line store. The store contains, as already mentioned, a total of [,024 cells.

The eight cells immediately following the 56 cells corresponding to a row of characters displayed on the screen are left vacant so as to permit the return to the initial value of the saw tooth signal which operates the horizontal scanning of the display screen.

The timing of the system (see FIG. 3) is given by a quartz oscillator 21, the output of which, when passed by a coincidence network 23, feeds a divider 22 adapted to furnish a signal CLOI at each bit period, and a counter 24 and a decoding network 25 which furnish trains of signals from D1 to D10 which identify the corresponding bit periods of each digit period.

The output transducer 26 from the delay line store feeds a flip-flop FRIV, the two outputs of which in rhythm with the signal CLOB, which represents the signal CLOI passed by a coincidence network 128, feed a flip-flop FIUL, the two outputs of which in their turn feed the first flip-flop REMO of a chain of ten flip-flops REM l-0 connected together to form a shift register 27. The two outputs of the last flip-flop REMI of the register feed in their turn a flip-flop RING which is directly connected to the input transducer 28 to the delay line. The shift register 27 and the flip-flop RING are clocked respectively in rhythm with the signals CLOB and CLOI.

TIMING ACTUATION The switching on of the terminal device embodying the invention produces a signal REZ which sets the flip-flops FISL and FACO. The output of the flip-flop FACO enables the coincidence gate 23, whereby the frequency divider 22 is free to emit the signal CLOI which scans the bit period. At the same time, the signal CLOB, the coincidence gate 128 being enabled, causes the stepping of the register 27. The counter 24, controlled by the negated output of the flip-flop FISL, is blocked. The direct output of the flip-flop FISL forces a bit at 1 into the flip-flop REM3 of the register 27, whereby the register having been stepped by the signal CLOB, the three flipflops REM1-2-3 are in one condition. At the same time the input flip-flop RING to the delay line is forced into the negative state by the signal FISL. After a period of time, naturally longer than the period of time corresponding to three bit periods, the signal REZ falls, whereby, at the first suitable front of the signal CLOI, the flip-flop FISL is reset, whereby the counter 24 is left free and at the same time there can be entered in the delay line three bits each one having a value of l in correspondence with the bit positions D9, D10, D1. In fact, the counter 24 commences its reckoning precisely from the bit interval 9. The three bits forced into the delay line memory are, in order, the bit CS, the parity of the same i.e., PCS, and the service bit bs=l.

The signal D3 which singles out the third bit period, feeds a counter 29, which counts l,024 number periods (memory cells) comprised in the delay line. The 1,024th position is decoded by the block 30, whereby the signal DUCA from the block 30 sets a flipflop FIME, the output of which at the time D8, signal STOP, resets the flip-flop FACO, removing the enablement from the circuit 23 and therefore from the divider 22. The bit CS circulates in the delay line and when it issues through the transducer 26 it sets the flip-flop FRIV, and through the flip-flop FIUL the bits present in the memory enter the register 27. At the same time, the bit CS sets the flipflop FACO which starts the timing and the stepping of the bits in the register 27.

INTRODUCTION INTO THE STORE BY KEYBOARD The states of the terminal, or rather the states of the store, are controlled by the line controller unit 12. The store can as sume the following different states: free, assigned to keyboard, and assigned to computer, states which are determined by the conversation procedure between terminal and central processor.

When a character is entered in the keyboard unit 31, eight bits TASI-8 are generated, seven effective bits plus one parity bit, representing the character. At the same time a signal RIC is generated which enters a coincidence gate 32, whereby, if there is enablement from the signal LITA, expressing the logi cal sum of the conditions of freedom and of assignment to the terminal keyboard, at the time D3, with the further enablement of the negated output of a flip-flop FIPR, a signal CRU3 is emitted, which enables, through the coincidence gate 33, the transfer of the bits TASI-S into a register 34 composed of eight flip-flops RU11-18. Furthermore, the signal CRU3 sets the flip-flop FIPR which staticizes the information as to the presence or not of a character in the register 34. The direct output of the flip-flop FIPR enters a coincidence gate 35, whereby, when the flip-flop REM7 of the input-output shift register 27 of the memory is at one in the time D5, thus attesting that the service bits bs is then present in the flip-flop REM7, a flip-flop FINT is set. The output of the flip-flop FINT, passed at the time D10 by a coincidence gate 74, generates the signal AZZE which puts the flip-flops REM3-4-5-6-7-8-9 of the shift register 27 into zero condition. After this zeroizing, at the following time DI, the direct output of the flip-flop FINT passes through a gate 73 to form the signal MINT which transfers in parallel the bits present in the flip-flops RU11-18 respectively into the flipflops REM3-0 of the shift register 27, by enabling a coincidence gate 135. At the same time, the signal MINT, after passing through an inverter 36, disenables the coincidence gate 37, whereby the service bit bs does not pass into the flip-flop RING and from here into the memory, but is instead shifted back by one character period, the flipflop FIUL being forced to one by the signal MINT.

At the preceding time D10, the direct output of the flip-flop FINT, passed by a coincidence gate 96, resets the flip-flop FIPR while the flip-flop FINT is put into zero condition at the following time D2. The negated output of the flip-flop FIPR at the time D2 (provided for by coincidence gate 34') generates the signal AZRl which zeroizes all the flip-flops of the register 34, whereby it is now possible, with all the components brought back into the initial condition, to introduce other keyboard character.

INTRODUCTION INTO THE STORE BY LINE After the conversation procedure established by the line controller 12, the central processor begins the transmission of a message, character by character. When the first character of the message has reached the controller 12, this informs the terminal control unit 3 by transmitting a signal SPOC. The signal SPOC enters a coincidence gate 137 (middle of FIG. 3), whereby if the signal FUIC is present expressing the condition of assignment to the central processor of the terminal, and at the time D10, a flip-flop FRIC is set. The direct output of this flip-flop enters a coincidence gate 38, whereby if there is the enablement of the negated output ofa flip-flop FCP 2 (which indicates whether an input register 39 for the characters from the line controller is full or empty), the signal CAEL is generated at the time D2. The signal CAEL enables a coincidence gate 40 and permits the transfer of the eight bits SPOl-8 of the character present in a register inside the line controller 12 into the eight flip-flops RU21-28 respectively constituting the input register 39.

The negated output of the flip-flop FCP 2, passed at the time D10 by a coincidence gate 41, had previously generated a signal BRES, which zeroizes the register 39 before the next filling. The signal CAEL, in addition to permitting the filling of the register 39 with the character SP01-8 arriving from the line controller 12, sets the flip-flop FCP 2 which staticizes the full condition of the register 39. In order to do this it has been enabled by a signal CAUS, the significance of which will be further explained, which enters the coincidence gate 42 at the time D2.

At this point, if the flip-flop EC? 2 is set, at the time D3 and with the enablement of the signal FUIC, a coincidence gate 43 generates a signal CRU 1 which enables a coincidence gate 44, whereby the contents of the eight flip-flops RU21-28 of the input register 39 pass into the eight flip flops RUM-18 of the register 34. At the same time, the signal CRUl sets the flip-flop FIPR thus attesting the full state of the register 34. The direct output of the flip-flop FIPR, at the time D5, resets the flip-flop FCP 2, thus attesting that the input register 39 is ready to receive the next character. The character in the register 34 enters the store as previously described.

EXTRACTION FROM STORE TO LINE When the operator at the terminal has finished compiling a message which is completely transferred into the store, he depresses a "message transmission key, whereby eight bits TASl-8 are originated. As previously described, these eight bits enter the register 34. A decoding block 45, fed by the eight flip-flops of the register 34, recognizes the character which expresses the command for extraction from the memory and for transmission to the central processor subject to the assent obtained from the line controller 12. The block 45 therefore produces a signal ETX, which, after an inverter 46, does not permit the flip-flop FlPR to be set since it disenables a coincidence gate 47. Thus there is blocked the entire logical chain which leads to the zeroizing of the shift register 27 and to the passage of the character present in the register 34 to the register 27 itself.

At the same time, the signal ETX sets a flip-flop FUTR to signal the command for extraction of the characters from the memory.

When the line controller 12, after the conversation procedure with the central processor, is ready to receive the first character, it transmits to the control unit 3 the signal SPOC, whereby, with enablement by the signal DUCA which, as already described, signalizes the end of the 1,024 cells circulating in the memory and remains present from the bit period D3 of the l,024th character position to the bit period D3 following inside the first character position circulating in the memory, and, with enablement by the direct output of the flip-flop FUTR, at the time D10, a coincidence gate 48 sets a flip-flop FEST. The direct output of the flip-flop FEST, at the time D! (through coincidence gate 48'), causes the emission of a signal MAUL, and, at the same time, it enters a coincidence gate 42, whereby the flip-flop FCP2 is set attesting the full state of the input register 39 if the signal CAUS is present. At the same time, the signal MAUL enables a coincidence gate 49, causing the contents of the flip-flops REM3-4-5- 6-7-78-0 of shift register 27 to pass into the input register 39. The content of the flip-flop REM9 is, on the other hand, disenabled from the transfer into the register 39 by the negated signal DUCA. At the same time, the content of the flip-flop REM] is enabled by the signal MAUL to transfer into a flip-flop RUBS. The first transfer which occurs in the presence of the signal DUCA, there being present in the shift register 27 only the bit CS in position D9, puts into zero position all the flip-flops RU2l-28 of the register 39. In fact, the transfer of the single bit=l, i.e., the bit CS in ninth position, is blocked by the negated signal DUCA.

Prior to this transfer, the input register 39 has been zeroized, at the time D10, by the signal BRES, as already explained. The content of the register 39 is tested by a decoding block 50, enabled by the signal FUTR which expresses the condition of extraction from the memory. The block 50 recognizes a character composed entirely of zeroes whereby it removes a signal DENU and thereby prevents the signal CAUS being passed by a gate 51, whereby the flip-flop FCP2 can no longer be set via the coincidence gate 42, by action of the signal FEST attesting the full condition of the register 39. At the time D2 the direct output of the flip-flop FEST sets the flip-flop FlUL (upper left, FIG. 3), thereby putting the bit bl =1 into this flip-flop, whereby the bit bl is inserted in the bit period D2 within the character period C1. The flip-flop FEST is reset at the time D5. in the next memory cycle, when there is recognized at the time D10 in the flip-flop REM3 the bit bl =l with the enablement of the signal FUTR and of the negated output of the flip-flop FCP2, the output of a coincidence gate 52 sets the flip-flop FEST. The logical flow already described is thus repeated. In fact, the transfer of the first character from the shift register 27 to the input register 39 occurs at the time D1. At the same time, the signal MAUL zeroizes the flip-flop REM2, removing the bit bl =1 which is shifted at the time D2 into the flip-flop FlUL, i.e., one character period behind. As the character in the register 39 is not decoded by the block as composed entirely of zeroes the signal CAUS is produced, whereby the flip-flop FCP2 is set, staticizing the full condition of the register 39. The direct output of the flip-flop FCP2 enables a coincidence gate 105, whereby the inverted output of a flip-flop FEUP, at the time D3, generates a signal CRU2 which sets the same flip-flop FEUP. The flip-flop FEUP staticizes the full or vacant condition of the register 34 when characters are desired to be extracted from the store in order to transmit them to the central processor and it has been reset by the signal QUER at the time D10 with the presence of the signals FUTR and SPOC. At the time D2, the inverted output of the flip-flop FEUP has zero ized the register 34 through the signal AZR2. The same signal CRU2 enables the coincidence gate 44, whereby the first character extracted from the memory and inserted into the register input 39 is transferred at the time D3 into the register 34.

At the time D5, the direct output of the flip-flop FEUP resets the flip-flop FCP2 thus attesting that the register 39 is ready to receive another character from the store. In fact, at the next time D10 the negated output of the flip-flop FCP2 enters the coincidence gate 52, whereby, as already mentioned, the flip-flop FEST is set, thus giving the command for extraction from the store of the character indicated by the bit b 1. After the extraction, the first two characters of the memory are respectively stored in the registers 34 and 39. Then at the time D5 following, the direct output of the flip-flop FEUP informs the line controller 12, by the signal SCOC, that a character is ready in the register 34. The line controller 12 ac complishes the extraction of the character present in the register 34 and then informs the control unit 3 by transmitting the signal SPOC. This transmission generates the signal QUER which resets the flip-flop FEUP, whereby there recommences the operation of transferring the character present in the register 39 to the register 34, and the subsequent extraction from the memory of the character marked by the bit b l=l in the bit position D2.

DIS PLAY When the terminal is in the condition of free" or assigned to keyboard all the characters present in the memory are displayed. In fact, see FIG. 3, the signal LITA, logical sum of the terminal states of free or assigned to keyboard, passed at each bit period D! by a coincidence gate 53 (lower right), generates a signal MEUL which operates like the signal MAUL in the manner already described. At each bit period DI the transfer of the character present in the register 27 to the input register 39 is thus obtained. The display of the characters circulating in the store and transferred into the register 39 can be obtained in various waysv in particular, see FIG. 4, it can be obtained by means of a character-generating cathode ray tube 55. The character-generating tube may be of the type called Symbolray Character Generating Cathode Ray Tube" manufactured by the Component Division of Raytheon Company, 465 Centre Street, Quincy, Massachusetts, United States of America. In this character generating tube 55 the electron beam generated by the cathode 56 is electrostatically deflected in the horizontal direction by the plates 57 and in the vertical direction by the plates 58. At the bottom of the tube is a matrix 59 in which are impressed the possible numerical, alphabetical and symbolical characters which it is desired to represent. The contents of the register 39 and the flip-flop RUBS, including the bit br=l when it is present, are applied to a digital-analogue converter 54 which provides the voltage levels SCO and SCV cor responding respectively to the horizontal and vertical coordinates of the character printed in the matrix 59, of which the binary code is present in the register 39. The voltage level SCO enters an adder 60 fed by a saw-tooth signal generated by a saw-tooth generator 6]. correspondingly, the voltage level SCV enters an adder 62 fed by a sinusoidal signal generated by a circuit 63. In such a manner the characters to be printed on the matrix 59 are singled out through its horizontal and vertical coordinates, scanned from left to right by an electron beam having a sinusoidal course. In accordance with the variations in the secondary electronic emission picked up by a collector 64, according to whether the electron beam encounters black or white, there is generated on a wire 65 a video signal which, amplified by an amplifier 66, feeds a cathode ray tube 67. The cathode ray tube 67 is a magnetic-deflection tube controlled by three coils respectively fed by a circuit 68 which amplifies, maintaining the same phase, the sinusoidal signal emanating from the circuit 63, from a circuit 69 generating a horizontal deflection saw-tooth signal and from a circuit 70 which generates a vertical deflecting staircase ramp for selecting the 16 display rows in turn. The screen of the cathode tube is therefore scanned by an electron beam having a sinusoidal course from left to right along each row in turn and from top to bottom through the rows in turn. In such a manner, the characters selected through the tube 55 are reproduced on the screen of the tube 67. On the screen of the tube 67, the 16 rows of 56 characters each can be displayed, these being in complete correspondence with the number of cells present in the memory. The synchronism of the time bases of the two tubes 55 and 67 with the command signals of the delay line memory is obtained by means of a synchronizing circuit 71 which triggers the generators of the saw-tooth signals and the generator of the staircase waveform, also the oscillator 63. The circuit 71 is fed by the signal DUCA which indicates the end of the memory cycle and by a signal FLYB which, as will be explained hereinafter, indicates the end ofa row.

FUNCTIONS CONCERNING THE FORMAT OF THE MESSAGE The terminal device embodying the invention is provided with means for permitting control of the format according to which the data is inserted into the store either from the keyboard or from the central processor. The control of the format is based, as will be seen, on the control of the shifting of the service bits bs from one memory cell to another. The fact that the display device is continuously active in every stage of insertion of data in the keyboard and that it is also adapted to display the bit bs, permits the operator to have a continual control of the procedures for compiling the message, while on the part of the central processor it is possible to transmit messages which appear on the screen according to a desired format. RETURN TO START In particular the terminal is provided with a function of return to start" whereby, when it receives either from the keyboard or from the line controller 12 a return to start code, the next character is positioned on the screen at the beginning of the row following the row in which the character preceding the return to start" command is positioned. With reference to FIG. 5, let us suppose that the "return to start key is keyed into the keyboard 31. As previously described, the code inserted is inserted into the register 34 and the flipflop FIPR is set. When the bit bs=l is tested in the flip-flop REM7 at the time D5, the signal AZZE should normally set to zero the shift register 27 as described and the signal MINT causes the transfer of the "return to start" code from the re gister 34 to the register 27. This code must, however, appear neither in the store nor on the display screen, whereby the decoding circuit 45 gives rise to a signal COVE which sets a flip-flop FEVE, the direct output of which feeds a function combining circuit 72 (lower right). This circuit renders a signal MELA false, thus disenabling

coincidence gates

73 and 74 and preventing the respective generation of the signals MINT and AZZE, consequently preventing the passage of the code from the register 34 to the register 27 and from here into the store. The direct output of the flip-flop FEVE enters a coincidence gate 75, whereby, when the bit bs=l is present at the time D10 in the flip-flop REM2, a flip-flop FAM2 is set. The output of this flip-flop at the time D1 enters a coincidence gate 76, whereby a signal TOLS is emitted which disenables the coincidence gate 37, thus not permitting the insertion of the bit bs into the store.

At the same time, the signal TOLS forces the bit bs into the flip-flop FIUL via a coincidence gate 109 (upper left), putting it at one, namely shifting the bit bs one character backwards. At the next following bit period D5, a coincidence gate 77 (lower right) provides a signal ALTM to reset the flip-flop FAM2. The flip-flop FEVE in the meantime remains in one condition, whereby at the following period D10 the bit b: is tested in the flip-flop REM2 so that the flip-flop FAM2 is set again. The shifting of the bit bs one character backwards in the memory then occurs again. This obviously corresponds on the screen to the shifting of the corresponding sign forward from left to right.

The method described above continues until there arises the signal FLYB, generated by the decoding network 30. This signal FLYB remains active from the bit period D3 within the first of the eight free cells which separate, as already mentioned, one row from another, to the bit period D3 of the first cell which can be filled of the row following. The signal FLYB staticizes the row end state during the circulation of the memory cells. In the bit period D5 within the first cell of the eight cells left free between rows, the flip-flop FAM2 is not reset because the signal FLYB prevents the origination of the signal ALTM, whereby, although the flip-flop FEVE is reset by the signal ZEFV which arises in the presence of the signal FLYB, the method previously described of the shifting of the bit bs=l progressively by one cell period continues. The shifting is stopped when, the signal FLYB ceasing, the signal ALTM can reset the flip-flop FAM2, whereby the bit bs=l has been finally transferred into the first cell of the next row. From this it follows that the character inserted after the return to start command will be positioned on the screen in the first position of the next row.

FORWARD SPACING The terminal is provided furthermore with the function offorward spacing" by means of which a character is written in the memory shifted by one cell compared with that previously written. The command forward spacing" can be inserted in the keyboard or be received from the central processor. In particular, if the forward spacing" is depressed there arises a code RASl-S which, as already explained previously, is introduced into the register 34. At the same time, the logical chain has occurred which superintends the transfer from the register 34 to the shift register 27. When the flip-flop FINT is set, as has already been described, subject to recognition at the bit time D5 of the bit bs=l present in the flip flop REM7, the decoding circuit 45 is enabled which recognizes the "forward spacing" command present in the register 34. The block 45 consequently generates the signal COAM which sets the flip-flop FAM2. The output of this flip-flop feeds the function combining circuit 72, which removes the signal MELA, disenabling as already described the origination of the signals AZZE for zeroizing the register 27 and MINT which effects the passage of the characters from the register 34 to the shift register 27. At the same time, as already mentioned, the signal TOLS originates which shifts the bit bs=l one character period backwards, so that on the screen the indicating sign corresponding to the bit bs is consequently shifted by one position forward from the left to right. The flip-flops FEVE and FAMZ being thus reset respectively at the time D1 and D5, the shifting of the bit bs no longer occurs, whereby the next character is inserted in the new memory position marked by BEGINNING OF PAGE The terminal is furthermore provided with the function of beginning of page by means of which a character is written in the first cell C1 of the memory. The beginning of page" command can be keyed in or received from the central processor. in particular, if the beginning of page code is keyed in, there arises a code TAS 1-8, which, as already described, is inserted in the register 34. At the same time, the logical chain is started which superintends the the transfer from the register 34 to the shift register 27. Thereby, when the flip-flop FINT is set it enables the decoding circuit 45 which generates a signal COHO which sets a flip-flop EH10. The output of the said flip-flop feeds the function combining circuit 72 which removes in its turn the signal MELA, thus preventing the transfer of the code present in the register 34 to the register 27. At the same time, the output of the flip-flop FH feeds the coincidence gate 75, whereby, when the bit bs=l is singled out, the flip-flop FAM2 is set. Consequently, the bit bs--l is shifted backwards successively from cell to cell. When all the 1,024 character positions of the memory have circulated, the flip-flop FHl0 is reset by the signal of end of store signal FIME, enabled through a coincidence gate 78 by the output of the flip-flop FAMZ. The bit bs is thus shifted to the first position of the new memory cycle, while the flip-flop FAMZ is reset by the signal ALTM at the first bit period D5, since the signal FLYB does not act during the final eight characters of the last row, i.e., at the end of the store, the decoding block 30 being disenabled by the signal FIM E.

BACK SPACING The terminal is furthermore provided with the function of back spacing" by means of which a character is written in the memory in one cell position backwards. In particular, if the code for "back spacing is keyed in, there originates a code TASl-8 which is introduced into the register 34. At the same time, the logical chain is started which superintends the transfer from the register 34 to the register 27. When the flipflop FINT is set it enables the decoding circuit 45 which generates a signal COIM which sets a flip-flop FIMI. The output of this flip-flop feeds the function combining circuit 72 which cancels in its turn the signal MELA which prevents the transfer of the code present in the register 34 to the register 27. At the same time, the output of the flip-flop FIMI enters a coincidence gate 79, whereby, when the bit bs=l is present in the flip-flop FIUL at the bit period D], the signal MUVI originates which sets a flip-flop F 1M2. The output of the flipflop FIM2, passed, at the time Dl, by a coincidence gate 80 (lower left), forces the bit bs=1 into the flip-flop RING, this shifting the bit bs=l forward by one cell in the memory, and, consequently, backwards by one position on the display screen. At the time D2, the direct output of the flip-flop FIMZ passes through a coincidence gate 81 (upper left), to form a signal ELM which cancels the bit bs=l present in the flip-flop REMO. At the time D2, if the signal FLYB is not present, the direct output of the flip-flop F [M2 resets the flip-flop FIMI. At the time D4, the flip'flop FIM2 is also reset. This is the logical procedure when the bit be is inside a row.

In the case where the "back spacing command is given when the bit bs=l is in the initial position C1 of the memory, the signal DUCA is present, which remains active as far as the bit time D3 inside the first cell Cl, whereby the coincidence gates 80 and 81 are inhibited. The flip-flop FIMI (because of the presence of FLYB) is reset at the time D2, and the flipflop FIM2 is reset at the time D4, whereby the back spacing" command remains inactive. If the bit b.r=l is positioned in the initial cell of a row, eight commands would be required in order to bring the bit bs=l to the final character position of the preceding row. In fact, the rows displayed on the screen, as has already been mentioned, are separated by eight cells left vacant. Since the signal FLYB is present in this period of eight cells, the coincidence gate 82 is disenabled, whereby the flipflop FIMI remains activated until the bit br=1 is brought to the final position of the row preceding. This having occurred, and the signal FLYB having fallen, the flip-flop FlMl can be reset, putting an end to the operation.

TOTAL CANCELLATION The command of total cancellation," i.e., cancellation of everything present in the store can come either from the keyboard or from the processor. If the "total cancellation" is depressed, there originates a code TASl-8 which is introduced into the register 34. At the same time, the logical chain is started which superintends the transfer from the register 34 to the register 27. The total cancellation code is decoded by the circuit 45 which generates a signal CAME, which in its turn sets a flip-flop FANC. The output of this flipflop feeds the function combining circuit 72 which removes the signal MELA preventing the transfer of the code present in the register 34 to the register 27. At the same time, the output of the flip-flop enters a coincidence gate 83, whereby, at the bit period D1 of the first position C1 of the memory, the signal DUCA being present, a signal is generated which sets a flip-flop FOLA. The direct output of the flip-flop FOLA generates, on the one hand, through the coincidence gate 76, the signal TOLS, which inserts the bit bs=l into the position D1 of the first memory cell, and, on the other hand, acts on the output flip-flop FRIV of the store keeping it at zero. In such a manner, the characters are no longer regenerated. At the next time D5 of the flip-flop FANC is reset by the direct output of the flip-flop FOLA. The flip-flop FOLA is reset at the end of the memory cycle, i.e., by the negated output of the flip-flop FIME. As can be seen from this cancellation operation, by not regenerating the characters already present in the memory at the output of the same, it is possible at the same time to introduce new characters either emanating from the keyboard or emanating from the processor. In fact, the logical chain which superintends the cancellation of the characters present in the memory does not interfere with the logical chain, already described, which superintends the insertion of new characters into the said memory.

CHARACTER STEPPING The terminal is moreover provided with the function of "character stepping by means of which the entire contents of the store are shifted by one character position. In particular, if the character stepping key is depressed there originates a code TASl-8 which is introduced into the register 34. The decoding block 45, enabled by the signal FINT, generates a signal COSC which sets a flip-flop FSI-IC, the output of which feeds the function combining circuit 72 which prevents, as already described, the transfer of the code present in the register 34 to the register 27. The output of the flip-flop FSHC in addition enters a coincidence gate 84 (lower left), whereby when the bit bs=1 is recognized at the time D2 in the flip-flop RING, a flip-flop FSHZ is set. The output of this flip-flop resets the flip-flop FSHC at the time D3, through coincidence gate 84' while it disenables a coincidence gate 85, preventing the normal passage of the characters, following the indicating bit bs=l, from the register 27 to the flip-flop RING and from here into the store. At the same time, the output of the flipflop FSH2 enables a coincidence gate 86 (middle left) whereby the characters issuing from the register 27 on the channel Z are entered into a supplementary shift register 87 formed by ten flip-flops RSHl-l). The characters are then inserted in the register 87 and shifted in rhythm with the signal CLOI, after which they emerge from the register 87 and on the channel w are introduced through the flip-flop RING into the memory. As can be seen, all the characters are shifted by one character period, the register 87 into which the characters are entered prior to re-entering the store being of such length.

The shifting of the characters continues until it arrives at the row end in which there are, as previously mentioned, eight vacant cells. Therefore the final character of the row has to be shifted by nine character positions in the memory so that it appears on the screen shifted by one position, i.e., at the beginning of the row following. At this point, the signal DESH originates from the decoding circuit 30 which remains active from the bit period D3 of the last cell which can be filled of the row as far as the following bit period D3, whereby, at the bit period D2 of the first of the eight vacant cells, the signal FLYB not yet being active, there originates from the coincidence gate 88 a signal SFIB which sets a flip-flop FIBL. The output of this flip-flop disenables the coincidence gate 28, whereby the clocking signal CLOB no longer reaches the register 27. In such a manner, the character of the last cell remains arrested in the register 27. After eight character positions, the signal DESH is again generated from the block 30 and remains active for a period of one character whereby, at the time D2, this time in the presence of the signal FLYB, there originates from the coincidence gate 89 the signal RFIB which resets the flipflop FIBL. Thus the coincidence gate 128 is again enabled and resumes the shifting of the characters as previously described, the characters of the last cell now being situated in the first character position of the following row. The signal FIME, at the end of the memory cycle, resets the flip-flop FSH2 back into zero condition, whereby the function is concluded.

ROW SHIFTING The terminal is furthermore provided with the function of row shifting by means of which the entire contents of the store are shifted by the number of cells elapsing between the position of the bit bs=l and the end of the row. If the "row shifting" key is depressed there originates a code TASl-8, which is introduced into the register 34. The decoding block 45, enabled by the signal FINT, generates a signal COSH which sets a flip-flop FSHC (lower left). The signal COSH, if the signal DESI-l is not present, i.e., if the bit bs=l is not situ ated in the last position of the row, whereby a coincidence gate I06 is enabled, sets a flip-flop FSI-II. With the bit bs=l in the final position of the row, the "row shifting" function is equivalent to the "character shifting" function.

The direct output of the flip-flop FSHC feeds the functions combining circuit 72 which prevents, as already described, the transfer of the code present in the register 34 to the register 27. The direct output of the flip-flop FSHI enters the coincidence gate 84, whereby, when the bit bs=l is recognized at the time D2 in the flip-flop RING, the flip-flop FSHZ is set. The direct outputs of the flip-flops FSHI, FSHC, and FSHZ feed a coincidence gate 90 which supplies a signal LASl-l which forces the service bit bl=l into the flip-flop RSHO. The entire operation is then as for the character stepping" function previously described. The first cycle of the store being concluded, the coincidence gate 84 continues to be fed by the direct output of the flip-flop FSH], whereby upon the fresh recognition of the bit bs, the flip-flop FSH2 is set again and the entire content of the memory is again shifted by one character position. The method continues until, with the presence of the signal DESH, i.e., on the final cell of the row, with the enabling ofthe direct output of the flip-flop FSHZ, the bit bl=l is recognized in the flipflop RSH9 at the time D], whereby from the coincidence gate 91 there is generated a signal ENSH which resets the flip-flop FSHI. At the time D2 the inverted output of the flipflop FSHI, passed by a coincidence gate 92, resets the flip-flop RSI-IO, removing the bit bl and thus concluding the process.

TABULATION The terminal embodying the invention is furthermore pro vided with means whereby the displayed data can be arranged on the screen according to different formats. Each format is defined by a group of privileged positions or stops on which the data can be columnized. In particular, when the apparatus is actually installed there are fixed two groups of stops, each group being able to be selected either by means of two keys present in the keyboard or by means of two tabulating codes emanating from the central processor. The stops forming a single format can in their turn be right" or left." By a "right" stop is meant a stop which permits the columnization on the last character keyed into the keyboard or received from the processor after the command for selecting the format. By left stop is meant a stop which permits the columnization on the first character keyed into the keyboard or received from the processor, after the command for selecting the format. The right or left" stops are fixed within a group of stops when the installation is actually carried out.

LEFT-HAND TABULATION In particular there are present in the keyboard two keys which generate respectively the codes TAB] and TABZ. The same codes can be received from the central processor. The codes TAB] and TAB2 select two configurations of stops, i.e., two message formats. Following one of the two tabulation commands, the service bit bs=l is shifted on to the first stop position encountered, relating to the tabulation program, i.e., to the selected group of stops. If one of the said two keys is depressed (see FIG. 6), a code originates which fills the register 34. At the same time, the logical chain is started which superintends the transfer from the register 34 to the register 27. If there is present in the register 34 the code TAB], relating to the first group of stops, it is decoded by the circuit 45 which, when enabled by the signal FINT, generates a signal COT]. The signal COT] sets a flip-flop FAAO and a flip-flop FTAS. If there is present in the register 34, on the other hand, the code TAB2, relating to the second group of stops, it is decoded by the circuit 45, which, when enabled by the signal FINT, generates a signal COT2. The signal COTZ resets the flip-flop FAAO and sets the flip-flop Fl'AS. The outputs of the flip-flop FAAO condition a decoding circuit 93 fed by the counter 29. The circuit 93 emits two signals, respectively referring to the left" or right" stops, in the cell periods relating to the selected group of stops.

Supposing that the key TAB] is depressed then the circuit 45 generates the signal COT], whereby the flip-flop FAAO, having been set, enables the decoding circuit 93 to emit signals only in the positions relating to the group of stops TAB]. The direct output of the flip-flop FI'AS feeds the func tions combining circuit 72 which keeps the signal MELA inactive, thus blocking the transfer of the code TABI from the register 34 to the register 27. At the same time, the output ofthe flip-flop FTAS enters the coincidence gate 75, whereby, when the bit bs=l is recognized at the time D10 in the flip-flop REM2, the flip-flop FAMZ is set.

As previously described, the output of the flip-flop FAMZ sees to it that the signal TOLS shifts the bit bs by one character period backwards in the memory, i.e., by one position forward on the screen. The shifting of the bit bs=l thus progressively continues from cell to cell until it arrives at the first cell assigned to the selected group of stops. This first stop can be a "left" or right stop. In the case of it being a left" stop, the decoding circuit 93 emits a signal DESS which enters a coincidence gate 94. When this gate is enabled by the direct output of the flip-flop FI'AS, when the bit bs=l is recognized at the time D5 in the flip-flop REM7, a signal BRUT originates which sets a flip-flop FATT. The direct output of the flip-flop FATT, at the time D7, produces a signal BUG] (through coin cidence gate 94') which resets the flip-flop FTAS. Thus the shifting procedure of the bit bs is stopped, as the flip-flop FAM2 is no longer kept set.

The flip-flop FTAS resets, the function combining circuit 72 leaves the signal MELA active, whereby at the next cycle, after the recognition of the bit bs within the stop position, the signal AZZE zeroizes the register at the time D10, and at the time DI, the signal MINT enables the transfer of the code TAB] into the register 27 and from here the insertion of this code into the store in the cell relating to the first stop position of the selected group of stops. Finally, the flip-flop FATT is reset at the time D10, the coincidence circuit 96 being enabled. From this point the characters keyed in are positioned in order commencing from the cell following the stop position relating to the group selected.

RIGHT-HAND TABULATION Let it be supposed that one of the two tabulating keys, in particular TABI, has again been depressed. The code relating to the key TAB] is inserted in the register 34, whereby, as already described, with the enabling of the signal FINT, the circuit 45 generates the signal COTl, which performs the functions already described previously in connection with the lefthand tabulation. The bit bs=l, as already mentioned, shifts from cell to cell until it arrives at the position corresponding to the first stop relating to the group selected. In the case of this stop being a right stop, the decoding block 93 emits a signal DESN which enters a coincidence gate 95. When this gate is enabled by the direct output of the flip-flop FIAS, when the bit bs=l is recognized at the time D in the flip-flop REM7, a signal BEDD originates which sets the flip-flop FATI" and a flip-flop FTAN. At the time D7 the output of the flip-flop F ATT resets the flip-flop FIAS by means of the signal BUG]. The coincidence gate 75 is enabled, consequently the flip-flop FAMZ cannot be set, whereby there does not arise the signal TOLS which operates the shifting of the bit bs. The functions combining circuit 72 leaves the signal MELA active, but the generation of the signals MINT and AZZE is still prevented by the fact that the flip-flop FINT is still in zero condition. At the following time D2, the direct output of the flip-flop FTAN, a coincidence gate 97 having been enabled by the direct output of the flip-flop FATT, enters a coincidence gate 98, whereby, the bit bs=l in the flip-flop RING having been recognized, a signal COIL is generated.

The signal COIL forces the service bit bbl into the flip-flop REM l, which is then positioned in the bit period immediately following the bit bs=l. On the next cycle, the signal COIL does not act because the coincidence gate 97 is disenabled, both the flip-flop F ATT as well as the flip-flop FIPR being reset by the output signal of the coincidence circuit 96. The bit b1=l is recognized in the flip-flop FIUL(upper left) in the said next cycle, whereby a coincidence gate 100, enabled by the direct output of the flip-flop FTAN, generates the signal BUSS which sets a flip-flop FSPI. The output of the flip-flop FSPI enters a coincidence gate 101, enabled by the signal MELA and by the negated signal FAZT (which will be mentioned hereinafter), whereby, in all the bit periods apart from the interval DI, the signal BLOC is generated by a gate 102, which ensures the disenablement of the coincidence gate 37, preventing the passage of the characters from the register 27 to the flip-flop RING and from here into the store.

At the same time, the output of the flip-flop FIUL enters a coincidence gate 103, enabled by the coincidence circuit 101, whereby all the bits which issue from the store in the bit periods apart from D1, are introduced directly into the flipflop RING and from here reintroduced into the store. The bit bbl is thus introduced directly into the flip-flop RING without passing through the register 27, while the bit br=l is shifted in the register itself. The output of a coincidence gate 104 (middle right), fed by the outputs of the flip-flops FSPI and FTAN, enters the coincidence gate 35, which, the said bit bs=l having been recognized at the time D5 in the flip-flop REM7, sets the flip-flop FINT again. The direct output of the flip-flop FINT enters the circuit 74 which, enabled by the signal MELA, generates the signal AZZE which zeroizes the flip-flops REM34-56-78-9 of the register 27. Also activated at the time BI is the signal MINT, as the output from the coincidence gate 73, which causes the transfer of the code TABI from the register 34 to the register 27, but without shifting the bit br-l there being here the disablement of the signal FTAN in the coincidence gates 107 (upper left) and 108.

The bit bs=l in the flip-flop REM] is recognized at the same time D1, whereby the output of the coincidence gate 110 resets the flip-flop SFPI. Each time that a character is introduced by the keyboard, the flip-flop FIPR is set, whereby the coincidence gate is enabling, permitting the actuation of the logical network which causes the bit bl=l, the code TABl and the character introduced into the register 27 in the preceding memory cycle to pass directly from the flip-flop FIUL to the flip-flop RING and from here again into the memory, while the bit bs=l still remains in its bit position inside the stop cellr Thus, as successive characters are graudally introduced into the keyboard, all the characters which follow the service bit bl=l pass directly from the flip-flop FIUL to the flip-flop RING and from here into the store, all of them thus gradually shifting by one cell position at each fresh introduc' tron.

EXIT FROM RIGHT-HAND TABULATION In order to exit from the "right stop position selected by one of the two tabulation keys, it is suflicient to depress a key corresponding to any of the functions previously described. In particular, if the forward spacing key is keyed in, the circuit 45, the flip-flop FT AN being activated, generates the signal COAM only when it is empowered by the signal BUSS, As previously described, the flip-flop FAM2 is set, whereby the functions combining circuit 72 does not keep the signal MELA active, whereby the signals AZZE and MINT do not act. At the same time, the absence of the signal MELA disenables the coincidence gate 101, preventing the passage of the bit bl=l, in and of all the characters which follow it, from the flip-flop FIUL to the flip-flop RING. The signal TOLS, generated by the direct output of the flip-flop FAMZ, at the times DI and D2 after the coincidence gate 76, acts on the flip-flop FIUL through the inverter 36 in the coincidence gate 37 and through a coincidence circuit 109 (upper left). Normally the bit bl=l in addition to following the path by which it is transferred from the flip-flop FIUL through the circuit I03 to the flip-flop RING and from here into the store, follows the route to return into the store through the register 2 7. The route through the register 27 is blocked at the coincidence gate 37, in normal conditions of tabulation, by the signal BLOC. As has been mentioned, the signal BLOC is de-activated after the action of the "forward spacing" key, but the circuit 37 still prevents the passage of the bit bl=l which arrives from the register 27, being disenabled by the signal TOLS. Furthermore, the signal TOLS cannot force the bit bFl into the flip-flop FIUL, the coincidence gate 109 being disenabled by the negated output of the flip-flop FTAN. At the moment when the bit b.s=l is recognized, a coincidence gate 111 (middle left), enabled by the signals FSPI and FAMZ, at the time D10, generates a signal CRES which resets the flip-flop FT AN (upper right). The the time D], the output of a coincidence gate 110 resets the flip-flop FSPI. The flip-flop FAMZ is still set, whereby the signal TOLS eliminates, through the coincidence gate 37, the bit bl, which is no longer there, and the bit bs=l which is within the cell corresponding to the stop. At the same time, the signal TOLS acts on the flip-flop FIUL (this time the circuit 109 is enabled) forcing the bit bs=l, which is thus shifted by IS THUS SHIFIED BY one cell, i.e., the forward spacing function has been activated, and all the components are returned to the initial condition.

CANCELLATION IN RIGHT-HAND TABULATION The terminal is moreover provided with the function of cancellation in right-hand tabulation, by means of which it is possible to cancel all the characters keyed in or received, after the right-hand tabulation function. In particular, if a key for "cancellation of right-hand tabulation is depressed, a code is generated which, as already previously described, is transferred into the register 34. The decoding circuit 45 being enabled by the signals BUSS and FTAN, it generates a signal COCT which sets a flip-flop FAZT. The direct output of the flip-flop FAZT enters the coincidence gate 74, whereby at the time D") the signal AZZE is forced which zeroizes the flipflops REM3-4-5678-9. The signal FAZT disenables the coincidence gate 101 whereby there does not occur the passage, from the flip-flop FIUL to the fiipfiop RING, of the bit bk] and of the characters which directly follow it. The signal AZZE cancels, as has been said, the bit bkl which is inside the register 27. At each time D10, the signal AZZE zeroizes the said flip-flops within the register 27, thus cancelling all the characters inserted after the command for the tabulation operation.

When the bit bs=l arrives, this is not cancelled, because in the time D10 it is situated in the flip-flop REM2. At the time D1 when the bit bs=l is recognized in the flip-flop REMI, the output of the coincidence circuit I10 resets the flip-flop FSPI. At the time D2, the bit bs=l having been recognized in the flip-flop RING, the output of the flip-flop FAZT generates the signal COIL through the coincidence gate 98. The signal COIL, as already described, forces the bit bl=l in the flip-flop REMI into the bit position immediately following the bit bF] At the time D5, with the enabling of the inverted output of the flip-flop FSPI, the coincidence gate I13 (lower right), generates a signal BLOT which resets the flip-flop FAZT. At the same time, the signal BLOT sets the flip-flop FIPR and simultaneously activates a code generating circuit 114 which inserts into the register 34 the tabulation code TAB! or TAB2 according to the state of the output of the flip-flop FAAC. At the next memory cycle the tabulation code is inserted into the register 27 and everything proceeds as previously described in the case of the right-hand tabulation.

It will be understood that many changes could be made in the embodiments of the invention described hereinabove, without departure from the scope of the invention. Accordingly, the scope of the invention is not to be considered limited to those embodiments but rather only by the scope of the appended claims.

I claim:

I. A terminal apparatus for the transmission of data including means for generating characters, a first register connected to said generating means for temporarily storing one of said generated characters at a time; a cyclic serial store including a succession of character cells for storing said characters, a timing device for producing timing signals which identify said succession of cells in the store, a second one-character register connecting the input with the output of said cyclic serial store for causing said characters to circulate in said serial store and conditioned by said timing device to enter in succession the characters in corresponding cells of said succession of cells, and a display device arranged to display characters stored in said store in an array of predetermined character cells respec tively, wherein the improvement comprises:

selectively operable means responsive to the timing device for generating selectively a group of stop signals for defining a corresponding group of character cells, each one of said groups of character cells corresponding to display positions defining a corresponding display format, OPERABLE MEANS RESPONSIVE TO THE TIMING DEVICE FOR GENERATING SELECTIVELY A GROUP OF STOP SIGNALS FOR DEFINING A COR- RESPONDING GROUP OF CHARACTER CELLS, EACH ONE OF SAID GROUPS OF CHARACTER CELLS CORRESPONDING TO DISPLAY POSITIONS DEFINING A CORRESPONDING DISPLAY FORMAT,

decoder means responsive to said selected group of stop signals for decoding a first stop signal of the selected group of stop signals, and

gate means jointly conditioned by said selectively operable means and said decoder means for causing the character stored in said first register to be transferred to said second register at a predetermined instant, whereby the transferred character is inserted in the cell of said serial store defined by said decoded stop signal.

2. A terminal apparatus according to claim I, wherein said display device comprises a cathode ray tube and wherein the display positions corresponding to the cells of the selected group are aligned in columns on said cathode ray tube, said apparatus further comprising a third one-character register jointly conditioned by said selectively operable means and said decoder means for causing the characters successively entered in said second register to be displayed by said cathode ray tube in tabulated formats.

3. A terminal apparatus according to claim 2; wherein a first sub-group of the stop signals define display position columns of said cathode ray tube columns on which characters are tabulated to the left of the center portion of the screen of said tube and a second sub-group of the stop signals define display position columns of said cathode ray tube columns on which characters are tabulated to the right of the center portion.

4. A terminal apparatus according to claim 2; further comprising key-actuated means for erasing from the store the last entered group of characters tabulated on one of the columns.

5. A data transmission system including a terminal apparatus according to claim 2; said apparatus being connected to a central data processor through means for controlling the transmission of the characters between the terminal apparatus and the central data processor, said selectively operable means being operable to select the display format both in response to means actuated locally in the terminal apparatus and in response to means actuated by a command received from the central data processor.

6. A terminal apparatus according to claim 2, further comprising means operable for erasing from the serial store all characters in the store at the time said erasing means is operated, means conditioned concomitantly with said erasing means for causing said first register to insert further characters in the store in the same cycle of the store when the erasure is taking place, and delay means controlled by said timing means for delaying the insertion operation of said concomitantly conditioned means.

7. A terminal apparatus for the transmission of data including means for generating characters, a first one-character register connected to said generating means for temporarily storing one of said generated characters at which identify each of said succession of cells in the store, each cell including a plurality of bit positions, one position of said plurality of bit positions being adapted to be marked by an identification bit, a second one-character register connecting the input with the output of said cyclic serial store for causing said characters to circulate in said serial store, said second register being conditioned by said timing device to enter in succession therein character therein in a corresponding cell of said succession of cells, a display device arranged to display the characters stored in said store in an array of positions which are arranged in rows and correspond to predetermined cells of said succession of character cells respectively, and a control unit normally arranged to introduce each said character of said second register into the store in that cell which is marked by said identification bit and then to shift the identification bit automatically to the next cell, wherein the improvement comprises:

first gate means conditioned by said identification bit for causing the character stored in said first register to be transferred to said second register at a predetermined instant, whereby the transferred character is inserted in the cell of said serial store defined by said identification bit,

a normally ineffective third one-character register connectable serially between said second register and said cyclic serial store and conditionable by said timing device when so connected to enter in succession each of the characters therefrom in a correspondent cell of said succession of cells,

means included in said control unit and selectively operable to generate a command signal, and

second gate means jointly conditioned by said identification bit and said command signal for so connecting said third responding to the row in which lies said identification bit. said second gate means being jointly conditioned by said second command signal and by said identification bit for so connecting said third register thus causing the characters coming from said second register to enter in succession in said third register, said second gate means being disabled by said decoder means whereby the characters are shifted in the store by the number of cells comprised between the cell containing said identification bit and the cell corresponding to the last character of a row.

I I! l l UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patentlkh 3,654,620 Dated April 4. 1972 Invmnmr(S)AntOniO S. Bartocci It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

Column 5, line 47, the numerals -78- should read Column 8, line 53, the letters "RASl-B should read TASl-S Column 9, line 16, "FHlO" should read FHIO line 20, FHlO should read FHIO line 24, "FHlO" should read FHIO Column 10, line 12, after "total cancellation" insert key line 72, after "channel" the "w" should read W Column 14, line 54, "The", first occurrence, should be deleted and At inserted. Column 16, line 42, after "at" insert a time, a cyclic serial store including a succession of character cells for storing chaxacters, a timing device for producing timing signals line 49, "therein" should read the Signed and sealed this 14th day of November 1972.

(SEAL) Attest:

EDWARD M.FLETCHER,JR. ROBERT GOTTSCHALK Attesting Officer Commissioner of Patents UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No. 3 Dated April 4 1972 Antonio S. Bartocci Inventor(s) It; is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

Column 15 lines 59 to 66 delete "OPERABLE MEANS RESPONSIVE TO THE TIMING DEVICE FOR GENERATING SELECTIVELY A GROUP OF STOP SIGNALS FOR DEFINING A CORRESPONDING GROUP OF CHARACTER CELLS, EACH ONE OF SAID GROUPS OF CHARACTER CELLS CORRESPONDING TO DISPLAY POSITIONS DEFINING A CORRESPONDING DISPLAY FORMAT."

Signed and sealed this 27th day of August 1974.

(SEAL) Attest! MCCOY M. GIBSON, JR. C. MARSHALL DANN Attesting Officer Commissioner of Patents ORM 0-69) USCOMM-DC 60376-Pl59 Q U 5, GOVERNMENT 'RIIITHIG OIHCE I... 036l-334.

Claims

1. A terminal apparatus for the transmission of data including means for generating characters, a first register connected to said generating means for temporarily storing one of said generated characters at a time; a cyclic serial store including a succession of character cells for storing said characters, a timing device for producing timing signals which identify said succession of cells in the store, a second one-character register connecting the input with the output of said cyclic serial store for causing said characters to circulate in said serial store and conditioned by said timing device to enter in succession the characters in corresponding cells of said succession of cells, and a display device arranged to display characters stored in said store in an array of predetermined character cells respectively, wherein the improvement comprises: selectively operable means responsive to the timing device for generating selectively a group of stop signals for defining a corresponding group of character cells, each one of said groups of character cells corresponding to display positions defining a corresponding display format, OPERABLE MEANS RESPONSIVE TO THE TIMING DEVICE FOR GENERATING SELECTIVELY A GROUP OF STOP SIGNALS FOR DEFINING A CORRESPONDING GROUP OF CHARACTER CELLS, EACH ONE OF SAID GROUPS OF CHARACTER CELLS CORRESPONDING TO DISPLAY POSITIONS DEFINING A CORRESPONDING DISPLAY FORMAT, decoder means responsive to said selected group of stop signals for decoding a first stop signal of the selected group of stop signals, and gate means jointly conditioned by said selectively operable means and said decoder means for causing the character stored in said first register to be transferred to said second register at a predetermined instant, whereby the transferred character is inserted in the cell of said serial store defined by said decoded stop signal.

2. A terminal apparatus according to claim 1, wherein said display device comprises a cathode ray tube and wherein the display positions corresponding to the cells of the selected group are aligned in columns on said cathode ray tube, said apparatus further comprising a third one-character register jointly conditioned by said selectively operable means and said decoder means for causing the characters successively entered in said second register to be displayed by said cathode ray tube in tabulated formats.

7. A terminal apparatus for the transmission of data including means for generating characters, a first one-character register connected to said generating means for temporarily storing one of said generated characters at which identify each of said succession of cells in the store, each cell including a plurality of bit positions, one position of said plurality of bit positions being adapted to be marked by an identification bit, a second one-character register connecting the input with the output of said cyclic serial store for causing said characters to circulate in said serial store, said second register being conditioned by said timing device to enter in succession therein character therein in a corresponding cell of said succession of cells, a display device arranged to display the characters stored in said store in an array of positions which are arranged in rows and correspond to predetermined cells of said succession of character cells respectively, and a control unit normally arranged to introduce each said character of said second register into the store in that cell which is marked by said identification bit and then to shift the identification bit automatically to the next cell, wherein the improvement comprises: first gate means conditioned by said identification bit for causing the character stored in said first register to be transferred to said second register at a predetermined instant, whereby the transferred character is inserted in the cell of said serial store defined by said identification bit, a normally ineffective third one-character register connectable serially between said second register and said cyclic serial store and conditionable by said timing device when so connected to enter in succession each of the characters therefrom in a correspondent cell of said succession of cells, means included in said control unit and selectively operable to generate a command signal, and second gate means jointly conditioned by said identification bit and said command signal for so connecting said third register, thus causing the characters coming from said second register to enter in succession into said third register, whereby all the characters in the store in the cells following the cell including said identification bit are shifted by one cell.

8. A terminal apparatus according to claim 7, wherein a group of stop signals defines the cells corresponding to the last character of the rows of said display, further comprising second means included in said control unit and selectively operable to generate a second command signal, decoder means for decoding the stop signal of the character cell corresponding to the row in which lies said identification bit, said second gate means being jointly conditioned by said second command signal and by said identification bit for so connecting said third register thus causing the characters coming from said second register to enter in succession in said third register, said second gate means being disabled by said decoder means whereby the characters are shifted in the store by the number of cells comprised between the cell containing said identification bit and the cell corresponding to the last character of a row.