US3271744A - Handling of multiple matches and fencing in memories - Google Patents

Handling of multiple matches and fencing in memories Download PDF

Info

Publication number
US3271744A
US3271744A US3271744DA US3271744A US 3271744 A US3271744 A US 3271744A US 3271744D A US3271744D A US 3271744DA US 3271744 A US3271744 A US 3271744A
Authority
US
United States
Prior art keywords
stages
register
memory
registers
columns
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Publication date
Application granted granted Critical
Publication of US3271744A publication Critical patent/US3271744A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/02—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using magnetic elements

Definitions

  • the present invention relates to a data memory and more particularly to means for reading multiple matches of information out of such a memory and means for suppressing or fencing olf certain predetermined portions of the memory during a lead out operation.
  • An associative memory system may be described generally as a system including word memory and means for simultaneously interrogating all words of the memory in accordance with selected data requirements. When this interrogation or association indicates that the interrogated portion of one or more words in the memory matches the selected data requirements, it is usually desired to extract the entire matching word or parts thereof from memory.
  • a usual mode of operation is to interrogate a multiple word memory in accordance with association data and to register an indication of those words which match the association data. Thereafter. the matching words or portions thereof are read out to utilization circuits. Generally the words are read out serially by word and either serially or parallel by bit.
  • One aspect of the present invention is directed toward reading multiple matching words serially by word out of memory after the match indication has been recorded in a match indicating register.
  • a copending application Serial No. 120,213, filed June 28, l9nl, and assigned to the assignee of the present invention discloses circuitry for use in connection with an associative memory wherein multiple matches of data in a single column of memory are recorded and are scqucntially read out.
  • the present invention provides for the interrogation and read out of an mxn word memory matrix with selective suppression or fencing out of predetermined portions of the memory.
  • Another object of this invention is to provide apparains for reading from a memory selected words and for fencing out or suppressing selected areas of the memory from which words are not to be read.
  • a further object of this invention is to provide apparatus for reading from memory selected words and for fencing out or suppressing selected areas of the memory from which words are not to be read out by storing the fencing data in one or more fence planes.
  • certain portions of the memory may be isolated or fenced to exclude from read out any matching word that falls outside the fenced area.
  • the fencing feature may be used in other ways.
  • the memory may store a large number of names and addresses, for example, the names and addresses of the subscribers to a large number of publications.
  • a fencing plane may be used to store the memory addresses of those subscribers to a particular publication. It may then be desirable, using two subscription lists (that is fencing planes) and to manipulate these planes in various ways.
  • the memory may be interrogated in accordance with one subscription list and thereafter the subscribers to the first list may be checked against the subscribers in a second list to determine which ones were duplicated on both lists.
  • the first list may be checked for the presence of names on one or more additional lists; for the presence on one additional list but not on a third list; or for the presence on either one of two additional lists.
  • Another feature of this invention is logical combination of the data in the detector plane and the fence planes may be accomplished whereby the read out of a word of memory may be dependent selectively upon the presence of corresponding stored indications in the detector plane and in all fence planes, or in at least one fence plane, or in only one fence plane.
  • FIGURE 1 is a block schematic of the entire system.
  • FIGURE 2 shows the arrangement of FIGURES 2A through 2? which form a composite circuit schematic of the system.
  • FIGURE 3 shows the arrangement of FIGURES 3A and 3B which form a partial schematic diagram.
  • FIGURE 4 shows another partial schematic diagram.
  • FIGURE 5 shows a partial schematic diagram of another embodiment.
  • the system comprises a memory having a detector plane, at least one fence plane and two shift registers.
  • the memory is first interrogated in accordance with a given criteria and the addresses of words matching the interrogation criteria are stored in the detector plane.
  • the multiple columns of the detector plane are then interrogated in parallel and a column shift register is set in accordance with the columns storing addresses.
  • the row shift register is set in accordance with the rows containing data.
  • the row shift register is reset and the columns are thereafter interrogated sequentially.
  • the first column is interrogated and row registers corresponding to addresses in the first column only are set.
  • the row registers are interrogated and corresponding words in memory are read out.
  • the second column is interrogated and again row registers are set. The reading out column-by-column is continued until all columns have been read out at which time a completion-of-readout indicator is actuated.
  • One or more fence planes may be provided for use in connection with the detector plane.
  • the fence planes may be set to suppress the read out of given areas of the memory even though the detector plane indicates the presence of data therein which corresponds to the interrogation criteria.
  • the rum word memory 10 may be, for example, a magnetic core memory consisting of 36 tiple bit words where the words are arranged in a 6 array. In this case ":6 and m:6.
  • An nxm ctor plane 12. which may be physically a part of the iory 10, records multiple match indications received esponse to an interrogation of the memory 10 or in other suitable manner.
  • the plane 12 has siX vercolumns in and six horizontal rows n.
  • An in de- )r plane flip-flop tFF) unit 14 connected by a group nos 16, registers the 111 columns of detector plane 12 in :h data are recorded.
  • m skipping shift register 18 connected by lines 21-- 23-24, 25-26, is associated with the FF unit 14 to trol sequential interrogation of the HI columns.
  • the auts of the or register 18 are applied through a pinty of lines 28, OR gates and drivers 32 to coin- 'nt selection lines 34 of memory 10 to effect, in coopion with signals on other coincidence lines, the read out of words.
  • the outputs of. in register 18 also are tied over lines 36.
  • OR gates 38 and drivers 40 to lines to effect sequential interrogation of the detector plane -he detector plane 12 also is connected by a group of s 44 to an n detector plane flip-flop (FF) unit 46.
  • FF detector plane flip-flop
  • 5 group of flip-flops is connected by lines 48-49, 50- 52-53 to an n skipping shift register 56.
  • the outputs I register 56 are applied over lines 58, OR gates 60 and ters 62 to coincident selection lines 64 to cooperate h outputs on coincidence lines 34 to read out words in the memory 10.
  • Coincidence of a signal on a line and a line 34 is effective to read out a word located he intersection of the two lines.
  • ⁇ nother output from the a register 56. over line 66 is ilied in parallel to OR gates 68 and 70.
  • the outputs OR gates 68 and 70 respectitely are effective to start :rrogation of the next or column of plane 12 which itains a set core and to reset FF unit 46.
  • n register 18 Upon comtion of the read out of all words indicated in the detecplane 12, an output from n register 18 is applied over ine 72 to actuate a completion indicator device 74.
  • An uxm fencing plane 80 similar to detector plane 12, Jrovidcd into which fencing data are entered, by means t shown, to fence oll' portions, rows and/or columns. the detector plane 12 which are to be ignored during given read out operation.
  • the fence plane is linked the lines 82 which are extensions. through switches of the lines 42.
  • the fence plane 80 is connected by a Jup of lines 86 to an m fence plane flip-flop (FF) unit which is identical to FF unit 14.
  • FF fence plane flip-flop
  • the FF unit 88 is nnected by lines 90-91 to an m fence plane gate unit 94, ferred to hereinafter as m gates 94. It is noted that oups of gang switches 96 and 98 may be set selectively the lines 23-24, or lines 23-24' to respectively exclude include m gates 94 in the circuit between FF unit 14 d m register 18.
  • An n fence plane flip-flop (FF) unit 100 is connected the fence plane 80 by a group of lines 102.
  • the FF tit 100 is identical to FF unit 88.
  • the unit 100 is concted to an n fence plane gate unit 104 by lines 106- '7.
  • the n gates 104 are identical to the m gates 94. to n gates 104 may be included selectively in the lines -51 or 50'5l' between FF tmit 46 and It register 56 groups of switches 108 and 110.
  • second input to the OR gate 118 is by means of a witch 122 which may be operated manually or otherwise i apply an advance pulse to n register 56.
  • a vitch 124 is provided to apply an advance pulse through R gate 68 to the I register 18.
  • a pair of switches 126 ad 128 are provided for resetting the FF units 88, l4, [l0 and 46, the reset pulse to FF 100 and 1 F 46 being aplied through OR gate 70.
  • a switch 130 is provided 4 for applying an initial interrogation pulse in parallel through a line 132 to all OR gates 38.
  • the detector plane 12, fence plane 80, as well as the various fence plane and detector plane gate and flip-flop units may also be referred to as registers.
  • FIG. 2 shows the arrangement of FIGS. 2A through 2F to form a composite schematic.
  • switches 84 (FIG. 2B), 96, 98 (FIG. 2B), 108 and 110 (FIG. 2D) are set to the positions shown.
  • the memory 10 is interrogated in accordance with usual associative memory techniques or, in some other way, the cores in plane 12 are set in accordance with the words which it is desired to read out.
  • the switches 126 and 128 (FIGS. 2A and 2C) are closed momentarily to reset FF units 88, 14, 100 and 46 to their 0 states.
  • the switch 130 (FIG. 2E) is closed momentarily to apply a signal from a power source represented by terminal over the line 132, where it is applied in parallel to a group of six OR gates 38.
  • the output of the OR gates are applied to a group of six drivers 40 which apply currents through six lines 42 linking the m columns of core plane 12, through switches 84 to ground.
  • the cores of planes 12 and 80 are of the type which may be read out nondestructively. A suitable core is described in an article by V. L. Ncwhouse which is published in the "Proceedings of the IRE," November 1957, pages 1484-1492.
  • a core is described wherein the application of magnetizing pulses much larger than the coercive force do not give rise to permanent changes of magnetization provided that that duration of the pulses is sufliciently short.
  • Other suitable non-destructive read out memory elements are multi-aperture devices, or two-core per bit devices where the cores are destructively but independently read out, whereby a stored bit may be read out twice.
  • the currents in lines 16 are applied to fiip-flops 14-1 through 14-6, setting corresponding flip-flops to their l states.
  • the currents applied to lines 44 are similarly applied to flip-flops 46-1 through 46-6.
  • the O and l outputs of FF unit 46 are applied over lines 48, 50. 52 or 49, SI. 53 to the n register 56.
  • the in register 18 includes seven flip-flops -1 through 1511-7. These flip-flops have their 0 and 1 inputs arranged at the bottom and their 0 and l outputs arranged at the top. Each flip-flop 15! is a conventional flip-flo which switches to its 1 state when a signal is applied to the l input and which. in the 1 state, provides an output from the 1 output terminal.
  • a signal applied to the input switches the flip-flop to its 1) state providing an output on the 0 output terminal.
  • the flip-flops 150-1 through 150-6 correspond to the six at columns of cores in the plane 12 whereas FF 150-7 is responsive to an output from FF 1511-13 to indicate that all six columns of the plane 12 have been interrogated.
  • the m register 18 is started by closing the switch 124 (FIG. 213) to apply a pulse from the power source indicated by terminal 152 through the OR gate 68 to a line 154.
  • the line 154 branches into lines 156 and 158.
  • one or more of the lines 25 may have a signal thereon.
  • the input on line 154 is attractive to flip to its 1 state the first flip-flop 150 corresponding to the line 25 which has a signal thereon.
  • the signal on line 158 gates that signal through an AND gate 160-1 and the same signal on line 156 gates the output of AND 160-1 through an AND gate 162-1 whereby it is applied to the 1 input of FF 150-1.
  • the signal on line 158 is gated through AND gate 164-1. through an OR gate 166-1 uherc it is applied to AND gate 160-2 to gate through a signal on the line 25-2 to AND gate 162-2 and to the 1 in ut terminal of FF 150-2. If there is no signal on line 25-2, there will he one on line 26-2 to gate the signal on line 158 through AND gate 164-2.
  • a signal applied to the line 154 is applied through line 158, AND gates 164 and OR gates 166 to the first AND gate 160 corresponding to a 1 input on a line 25.
  • flip-flop [50-1 When flip-flop [50-1 is in its 1 state, its output is a plied to an AND gate 170-1 and OR gate 166-1. The 1 outputs of subsequent flip-flops 150 are applied to AND gates 170 corresponding to the next succeeding flip-flop.
  • the gates 170 cllcct the turning off of a flip-flop 150 when the next succeeding pulse is applied to the line 156.
  • the next succeeding AND gate 160 is conditioned through the OR gate 166 corresponding to the flip-flop 159 which is in its 1 state.
  • subsequent pulses on line 158 are superfluous whereas the same pulses on line 156 are effective to turn oil the flipflop 150 which is on and to turn on the next conditioned flip-flop 150.
  • the output from an actuated flip-flop 150-1 through 150-6 is applied to corresponding lines 28 and 36.
  • successive advance signals applied to the line 66 hy n register 56 and through OR gate 68 to the line 154 successively advance the m register 18 until the last m column containing a set core is read out.
  • the next advance pulse on line 154 then switches the fliptlop 1507 to its I state, applying an output signal on line 72 to actuate the completion indicator device 74 to indicate completion of thc read out.
  • This device 74 may be a hell, light, relay, switch, etc.
  • the I: register 56 operates in an identical manner. the corresponding components being designated similarly to those in unit 18; however, those in 56 contain a prime reference.
  • flip-flops 14-1, 14-3, 14-5, 14-6, 46-1, 46-2, 46-3, 46-4, 46-5 and 46-6 are set to their 1 states and signals 6 are applied to m register 18 through lines 25-1, 25-3, 25-5, 25-6, 26-2 and 26-4, and to n register 56 through lines 52-1, 52-2. 52-4. 52-5 and 52-6.
  • the switch 214 (FIG. 2B) is closed momentarily and the resulting signal on line 158 gates the signal on line 25-1 through AND gate 160-1; the signal on line 156 gates the output of AND 160-1 through AND 162-1 to the 1 input terminal of FF 150-1, setting this flip-flop to its 1 state and applying a signal to the corresponding lines 28-1 and 36-1 and to AND gate 170-1 and OR gate 166-1.
  • the switch 122 (FIG. 2D) is not closed at this time and therefore no signals are applied to the lines 58. With a signal on line 34-1 (FIG. 2F) but not on any line 64 (FIG. 2F), read out of information from memory 10 is not affected.
  • the switch 128 (FIG. 2C) is closed momentarily to reset FF unit 46.
  • the signal on line 36-1 is applied to OR gate 38-1 and, through driver 40-1, applies a pulse to line 42-1.
  • the signal on line 42-1 is effective through the set core at the intersections of lines 44-2, 44-3 and 44-4 with line 16-1 to induce currents in the latter three lines 44.
  • the current in line 16-1 is superfluous since FF 14-1 was previously set to its 1 state and has not been reset.
  • the currents in lines 44-2, 44-3 and 44-4 are effective to set corresponding flip-flops 46-2, 46-3 and 46-4 to their l states.
  • FF 44-2 is applied over line 52-2 to AND gate 160-2' in n register 56.
  • Switch 122 is closed momentarily to apply an advance signal through OR gate 118 and line 120.
  • the line 1-20 branches into lines 156' and 158'. Since there is no signal on line 52-1, the signal on line 158' advances, in the manner described hereinbefore, to gate the signal on line 52-2 through AND gate 160-2' to AND gate 162-2' where it is gated by the signal on line 156' to the 1 input of FF 150-2, setting this flip-flopto its 1 state.
  • FF 150-1 in m register 18 and FF 150-2' in n register 56 are now in their 1 states and are applying signals to corresponding lines 28-1 and 58-2.
  • Coincident currents on lines 34-1 and 64-2 (FIG. 2F) thus read out the word in memory 10 at the address defined by the intersection of these lines.
  • the read out pulse is applied over line 113-1 to OR gate and over line 117 to OR gate 118.
  • next flip-flop 14 which has been set to its 1 state is FF 14-3. Therefore, an output is applied to the line 36-3, through OR gate 38-3 and driver 40-3 to line 42-3 to induce outputs on lines 44-1 44-2 and 44-4, setting flip-flops 46-1, 46-2 and 46-4 to their 1 states. Current also is induced in line 16-3 but is superfluous since FF 14-3 is arcady in its 1 state.
  • the switch 122 (FIG. 2D) is closed momentarily to apply an advance pulse through OR gate 118 to n register 56.
  • This pulse sets FF 150-1' to its 1 state.
  • coincidence of pulses on lines 34-3 and 64-1 efl'ects read out of the word in memory at the corresponding address.
  • the resultant output on line 113-3 to OR gate 115 is applied through OR gate 118 to switch FtF 150-1' to its 0 state and to switch FF 1504' to its 1 state.
  • a coincidence of pulses on lines 34-3 and 4-2 effects the read out of the word in memory 10 at 1e corresponding address.
  • the n register 56 is advanced turn on FF 150-4' causing the corresponding word 1 he read out. Since no more flip-flops 46 are in the 1 ate, the resulting output pulse form OR gate 115 is fed nck to turn FF 150 -7' on, to again rcsct Fl" unit 46 and l advance in register 18.
  • the seven cores shown as solid in plane I are set. Assume also that cores are set in plane 12 a in the foregoing example of multiple match read out. he switches 84, 96, 98, 108 and 110 are set to their alterite positions. Switches 126 and 128 are closed momenrily to reset FF units 88, 14, 100 and 46. The switch 10 is closed momentarily to provide interrogation of 1 columns of plane 12, and as in the prior example, outit signals are derived on lines 16-1, 16-3, 16-5, 16-6, l-l, 44-2. 44-3, 44-4, 44-5 and 44-6, setting cor- :sponding flip-flops 14 and 46 to their 1 states.
  • the sigllS on lines 42 flow through the switches 84, lines 82 1d the associated columns of fence plane 80.
  • the cur- :nts flowing through fence plane 80 induce currents in res 86-1, 86-5, 86-6. 102-1, 102-3 and 102-5.
  • flip-flops 88-1, 88-5, 88-6, 100-1, 100-3 1d 100-5 are set to their 1 states.
  • gate tit 94 (FIG. 2B).
  • the odd number gates 94-1, 94-3, l-5, etc. are AND gates.
  • the AND gates 94 'e connected to the 1 outputs of flip-flops 88 and 14 hereas the OR gates 94 are connected to the 0 outputs flip-flops 88 and 14.
  • gate unit 104 the ld-nnm bered AND gates 104 are connected to the l itputs of the flip-flops 100 and 46 whereas the evenimbered OR gates 104 are connected to the 0 outputs flip-flops 100 and 46.
  • FF 14-1 is set to its 1 state and therefore applies an put to AND gate 94-1.
  • FF 88-1 is set to its 1 state id therefore applies a second input to AND gate 94-1 gate through the signal from FF 14-1 and thus set e FF 150-1 to its 1 state when the advance signal is lplied by closing switch 124.
  • switch 128 FIG. 2C
  • the switch 122 is closed to apply an advance signal. Since FF 150-3' which is the first flip-flop [50' corresponding to flip-flops 100 and 46 both of which are in their 1 states, the signal on lines 156' and 158' advances to set FF 150-3' in its 1 state. At this time, FF 150-1 is still set in its 1 state and coincidence of signals on lines 34-1 and 64-3 is effective to read the word out of memory 10 at the corresponding address. The resultant output on line 117 applies an advance pulse to n register 56. The advance signal proceeds down the lines 156 and 158, in n register 56, seeking the next register position corresponding to flip fiops 100 and 46 both of which are set to their 1 states.
  • the remaining flip-flops 14 which are set to their 1 states are FF 14-3, 14-5 and 14-6.
  • the remaining flipllops 88 which are set in their 1 states are FF 88-5 and 88-6.
  • FF 150-5 and 150-6 may be set to their 1 states. Therefore, the advance signal through OR gate 68 advances through In register 18 to set FF 150-5 in its 1 state, thus producing an output on lines 28-5 and 36-5.
  • the signal on line 36-5 is applied through OR gate 38-5 and driver 40-5 to lines 42-5 and 82-5.
  • the signals on lines 42-5 and 82-5 induce outputs on lines 16-5 and 86-5, both of which are superfluous since the corresponding flip-flops 14-5 and 88-5 are already set in their 1 states. Currents also are induced on lines 44-1, 44-2, 44-3, 44-4, 44-5, 102-1, 102-3 and 102-5.
  • Flip-flops 46-1, 46-2, 46-3. 46-4, 46-5, 100-1, 100-3 and 100-5 are set to their 1 states.
  • the switch 122 is closed to apply an advance signal to n register 56. This signal advances down the lines 156' and 158' seeking a flip-flop position corresponding to coincidcntly set flip-flops 100 and 46.
  • the first such flip-flop is FF 150-1' and the word corresponding to lines 34-5 and 64-1 is read out of memory 10.
  • FF 100-3 and FF 46-3 are both set so the word corresponding to lines 34-5 and 64-3 is read out. Row 4 is fenced out and is thus skipped.
  • FF 100-5 and FF 46-5 are both set so the word corresponding to lines 34-5 and 64-5 is read out. Neither FF 100-6 nor 46-6 is not set and the advance signal following read out of the word at the intersection of lines 34-5 and 64-5 proceeds to set flip-flop -7' to produce a reset output from OR 70 and an advance signal to m register 18. This advance pulse advances to set FF 150-6.
  • the resultant interrogation of column six of planes 12 and 80 sets flip-flops 46-3, 46-6 and 100-1. Flip-flops 14-6 and 88-6 remain set.
  • FIGURES 3A and 3B a variation of a portion of the system shown in FIGURFS ZA-ZF is illustrated wherein a detector plane 112, imilar to detector plane 12 of FIGURE 2E, and two fence planes and 280, each similar to fence plane 30 in FIGURE 25 are provided.
  • the illustration in FIGURE 3 is on a smaller scale wherein 3 and m :--3. whereas in FIGS. ZA-Z F,
  • This embodiment illustrates that a novel and useful system may be provided by AN Ding the contents of a detector plane with the contents of two or more fence planes.
  • the detector plane 112 and the fence planes 180 and 280 are coiucidently interrogated by signals on the lines 142 which correspond to the lines 42-82 in FIGURE 2E. Assume that the cores A1, A3, A5, A6 and A9 in plane 112 have been set. Assume that cores B1, B3. B and H9 in plane 180 and cores C1, C5, C6 and C9 in plane 280 have been set.
  • n outputs of plane 112 are on lines 144-1, 144-2, 144-3. connecting to the I inputs of corresponding flipll ps 146-1. 146-2. 146-3.
  • the m outputs are on lines 1161, 116-2 and 116-3, connecting respectively to the 1 inputs of flip-flops 114-1, 114-2 and 114-3.
  • n output lines 202 and 302 of planes 180 and 280 respectively. similarly connect to the 1 inputs of corresponding llip-llops 200 and 300.
  • the at output lines 186 and 286 of planes 180 and 280 respectively connect to the 1 inputs of flip-flops 188 and 288.
  • a common reset line 190 is provided for m flip-flop units 114, 188 and 288.
  • a common reset line 192 is provided for n flip-flop units 146, 200 and 300.
  • a gating unit 194 generally corresponding in function to the gating units 94 in FIGURE 2 is interposed between the m llip-flop units 114, 188 and 288 and the m register 18.
  • a gating unit 204 corresponding to unit 104 in FIG. 2 is interposed between :1 flip-flops 146, 114, 200, 188, 300 and 288 and the register flip-flop units 146, 200 and 300 and the n register 56.
  • AND gates 204-1. 204-3 and 204-5 have as inputs the l outputs of n tIip-llops 146, 200 and 300 as follows:
  • OR gates 204-2, 204-4 and 204-6 have as inputs the a outputs of n liipllops 146, 200 and 300 as follows:
  • OR gates 194-2, 194-4 and 194-6 have as inputs the 0 outputs of m flip-flops 114, 188 and 288 as follows:
  • switches may be provided for selectively including either or both fencing planes and 280.
  • FIGURE 4 two circuit blocks 294 and 304 are shown which may be substituted in FIGURE 3 for blocks 194 and 204 respectively.
  • This embodiment illustrates another variation of the system wherein the contents of the detector plane 112 are ANDed with the contents of either fence plane 180 or 280.
  • the inputs to the blocks 294 and 304 are the some as the inputs to the blocks 194 and 204 in FIGURE 3. These inputs are the 0 and 1 outputs of the flip-flops 114, 146, 188, 200, 288 and 300, and are so indicated in the lefthand margin of FIGURE 4.
  • OR gate 310-1 has as inputs the 1 output of flip-flops 200-1 and 300-1.
  • OR gate 310-2 has as inputs the 1 outputs of flip-flops 200-2 and 300-2.
  • OR gate 310-3 has as inputs the 1 outputs of flip-flops 200-3 and 300-3.
  • OR gate 312-1 has as inputs the 1 outputs of flip-flops 188-1 and 288-1.
  • OR gate 312-2 has as inputs the l outputs of flip-flops 188-2 and 288-2.
  • OR gate 312-3 has as inputs the 1 outputs of flip-flops 188-3 and 288-3.
  • OR gate 310 or 312 will produce an output when either of the flip-flops connected as inputs is in its 1 state.
  • each gate 310 and 312 will produce an output when both of its inputs are in their 1 states.
  • OR gates 310-1, 310-2 and 310-3 are applied respectively to AND gates 304-1, 304-3 and 304-5.
  • the second inputs to these AND gates are the 1 0:11pm: of flip-flops 146-1, 146-2 and 146-3 respective y.
  • OR gates 312-1, 312-2 and 312-3 respectively are connected as inputs to AND gates 294-1, 294-3 and 294-5.
  • the second inputs to these AND gates are the 1 outputs of flip-flops 114-1, 114-2 and 114-3, respectively.
  • the OR gates 304-2, 304-4, 304-6, 294-2, 294-4 and 294-6 each have three inputs which are the 0 outputs :11 the flip-flops 114, 146, 188, 200, 288 and 300 as folows:
  • circuit blocks 394 and 404 are shown which may be substituted in FIGURE 3 for blocks 194 and 204 respectively.
  • This embodiment illustrates a further variation of the system wherein the contents of the detector plane 112 may be ANDed with the contents of one or the other of the planes 180 and 280, but not with both. i
  • FIGURE 4 and FIG- ZE 5 are substantially identical but have the following ferences.
  • AND gates 410 and 412 have been ostituted for the OR gates 310 and 312 of FIGURE 4. condly, each of the AND gates has as its two inputs the output of a flip-flop 238 or 300 and the output of a u-fiop 188 or 200,
  • the circuit of FIGURE is ective to produce the read out of a word corresponding an address set in a core in the detector plane 112 proled that a corresponding core is set in the detector plane 0 but is not set in the corresponding core in fence me 180.
  • a first register having n rows and m columns of register elements corresponding to the n rows and in columns of said memory, one element corresponding to each word of said memory with selected ones of said elements set to a given state,
  • a third register having I: stages corresponding to the n rows of said first register, first skipping shift register having in stages corresponding to the in stages of said second register, operable in response to the setting of stages of said second register for selling corresponding stages of said first skipping shift register, and operable in response to successive interrogation inputs to provide outputs successively from set stages thereof,
  • a second skipping shift register having n stages corresponding to the n stages of said third register, operable in response to the setting of stages of said third register for setting corresponding stages of said second skipping shift register, and operable in response to successive interrogation inputs to provide outputs successively from set stages thereof,
  • said means for pplying interrogation inputs to said first skipping shift :gislcr comprise means for applying an initial interrogaon input and means for applying the last said successive ulput from said second skipping shift register.
  • means for pplying inlcrrogulion inputs to said second skipping shift register comprise means for applying an initial interrogation input and means for applying inputs which set stage of said second skipping shift registers.
  • a first register having :1 rows and m columns of register elements corresponding to the n rows and m columns of said memory, one element corresponding to each word of said memory with selected ones of said elements set to a given state,
  • a second register having n rows and m columns of register elements corresponding to the n rows and in columns of said memory, one element corresponding to each word of said memory with selected ones of said elements set to a given state,
  • third and fourth registers each having an stages corresponding to the m columns of said first and second registers respectively
  • first logical means having in stages corresponding to the m stages of said third and fourth registers, each stage being set when the corresponding stages of said third and fourth registers are set,
  • a first skipping shift register having m stages corresponding to the in stages of said first logical means, scttable in accordance with the setting of corresponding stages of said first logical means, and operable in response to successive interrogation inputs to provide outputs successively from set stages thereof,
  • fifth and sixth registers each having it stages corresponding to the n rows of said first and second registers respectively
  • second logical means having n stages corresponding to the n stages of said fifth and sixth registers, each stage being set when the corresponding stages of said fifth and sixth registers are set,
  • a second skipping shift register having :1 stages corresponding to the n stages of said second logical means, settable in accordance with the setting of corresponding stages of said second logical means, and operable in response to successive interrogation inputs to provide outputs successively from set stages thereof,
  • said means for applying interrogation inputs to said lirst skipping shift applying interrogation inputs to said second skipping shift register comprise means for applying, an initial interrogation input and means for applying inputs which are outputs from said memory in response to coincident application to said memory of an output from a set stage of srud first skipping shift register and an output from a set stage of said second skipping shift register.
  • said means for applying resetting inputs to said fifth and sixth registers comprise means for applying initial resetting inputs and means for applying the last said successive output from said second skipping shift register.
  • a first register having 11 rows and in columns of register elements corrc-pomling to the 11 rows and m columns of said memory. one element corresponding to each word of said memory with selected ones of said elements set to a given state,
  • a second register having it rows and m columns of register elements corresponding to the n rows and in columns of said memory, one element corresponding to each word of said memory with selected ones of said elements set to a given state,
  • third and fourth registers each having m stages corresponding to the m columns of said first and second registers respectively
  • first logical means having m stages corresponding to the in stages of said third and fourth registers, each stage being set when the corresponding stage of either of said third and fourth registers is set,
  • a first skipping shift register having in stages corresponding to the m stages of said first logical means, sen-able in accordance with the setting of corresponding stages of said first logical means, and operable in response to successive interrogation inputs to provide outputs successively from set stages thereof.
  • fifth and sixth registers each having :2 stages corresponding to the n rows of said first and second registers respectively
  • second logical means having it stages corresponding to the n stages of said fifth and sixth registers, each stage being set when the corresponding stage of either of said fifth and sixth registers is set,
  • a second skipping shift register having n stages corre sponding to the :1 tages of said second logical mean settahlc in accordance with the setting of corresponding stages of said second logical means, and operable in response to successive interrogation inputs to provide outputs uccessively from set stages thereof,
  • a first register having it rows and in columns of register elements corresponding to the n rows and in columns of said memory. one element corresponding to each word of said memory with selected ones of said elements set to a given state,
  • a second register having I: rows and in columns of register elements corresponding to the n rows and in columns of said memory, one element corresponding to each word of said memory with selected ones of said elements set to a given state,
  • third and fourth registers each having in stages corrcspending to the in columns of said first and second registers respectively
  • first logical means having m stages corresponding to said third and fourth registers. each stage being set when only one of the corresponding stages of said third and fourth registers is set,
  • a first skipping shift register having m stages corresponding to the in stages of said first logical means. scttahle in accordance with the setting of corresponding stages of said first logical means, and operable in response to successive interrogation inputs to pro vide outputs successively from set stages thereof.
  • fifth and sixth registers each having 11 stages coresponding to the n rows of said first and second registers respectively
  • second logical means having n stages corresponding to the n stages of said fifth and sixth registers, each stage being set when one only of the corresponding stages of said fifth and sixth registers is set.
  • a second skipping shift register having n stages corresponding to the n stages of said second logical means, sctlable in accordance with the setting of corresponding stages of said second logical means, and operable in response to successive interrogation inputs to provide outputs successively from set stages thereof,
  • first registers each having n rows and m columns of register elements corresponding to the n rows and m columns of said memory, one element in each said register corresponding to each word of said memory with said elements of said registers set selectively to given states
  • a first logical circuit having m stages, each stage corresponding to a similar stage of all said second registcrs, each said stage of said first logical circuit being set when said similar stages of said second registers are set.
  • a first ski ping shift regi ter having in stages corresponding to the m stages of said first logical cir cult. scttahlc in accordance with the setting of corrc spouding stages of said first logical circuit. and operable in response to successive interrogation inputs to provide outputs successively from set stages thereof, second lo ical circuit having ll stages each stage corresponding to a similar stage of said third registers, each said stage of said second logical cir uit being set when said similar stages of said third registers are set, second skipping shift register having a stages corresponding to the n stages of said second logical circuit. settable in accordance with the setting of corresponding stages of said second logical circuit, and operable in response to successive interrogation inuts to rovide outputs successively front set stages thereof,
  • first registers each having it rows and in columns of register elements corresponding to (hi: it rows and or columns of said memory.
  • one element in each said regi ter corresponding to each word of said memory with said elements of said registers set selectively to given states.
  • a first logical circuit having in stages. each stage corresponding to a similar stage of all said second grstct's. each said stage of said first logical circuit being set when said similar stage of one of said sec ond
  • a first ski ping shift register having in stages corresponding to the in stages of said first logical circuit. settable in accordance with the setting of correspond ing stages of said first logical circuit, and operable in response to successive interrogation inputs to provide outputs successively from set stages thereof,
  • a second logical circuit having n stages each stage corresponding to a similar stage of said third rcgis tcrs. each said stage of said second logical circuit hcing set when said similar stage of one of said third registers is set and said similar stage of at least one of: the other said second registers is set,
  • second skipping shift register having it stages orresponding to the n stages of said second logical circuit, suitable in accordance with the setting of corresponding stages of said second logical circuit. and operahle in response to successive interrogation inputs to provide outputs successively from set stages thereof,
  • a multiple word data memory having n rows and in columns.
  • first registers each having it rows and m columns of register elements corresponding to the n rows and m columns of said memory, one element in each said register corresponding to each word of said memory with said elements of said registers set selectively to given states
  • a first logical circuit having m stages each stage corresponding to a similar stage of all said second registers, each said stage of said first logical circuit being set when said similar stage of one of said second registers is set and said similar stage of only one of the other said registers is set,
  • a first skipping shift register having or stages corresponding to the in stages of said first logical circuit, settable in accordance ⁇ tlllt the setting of corresponding stages of said first logical circuit, and operable in response to succe sive interrogation inputs to provide outputs succcssitely frotn set stages thereof.
  • a second logical circuit having It stages each stage corresponding to a similar stage of said third registers. each said stage of said second logical circuit being set when said similar stage of one of said third registers is set and said similar stage of only one of the other said registers is set.
  • a second skipping shift register having it stages corresponding to the n stages of said second logical circuit, scttahlc in accordance with the setting of corresponding stages of said second logical circuit, and operable in response to successive interrogation inputs to provide outputs successively from set stages thereof,

Description

Sept. 6, 1966 H. E. PETERSEN ETAL 3. 4
HANDLING OF MULTIPLE MATCHES AND FENCING IN MEMORIES 11 Sheets-Sheet 2 Filed Doc. 51, 1962 REMFLFfi 6 5 mmcmon Sept. 6, 1966 H. E. PETERSEN ETAL ,7
HANDLING OF MULTIPLE MATCHES AND FENCING IN MEMORIES 11 Sheets-Shea t 3 Filed Dec. 51, 1962 FIG.2B
- gee-1 25-1 Sept. 6, 1966 H. E. PETERSEN ETAL 3. 7 .7
HANDLING OF MULTIPLE MATCHES AND FENCING IN MEMORIES 11 Sheets-Shut 4 Filed Dec.
FIG. 2C
Sept. 6, 1966 H. E. PETERSEN ETAL 3,271,744
HANDLING OF MULTIPLE MATCHES AND FENCING IN MEMORIES 11 Sheets-Sheet 5 Filed Dec.
Sept. 6, 1966 H. E. PETERSEN ETAL 3,
HANDLING OF MULTIPLE MATCHES AND FENCING IN MEMORIES 11 Sheets-Sheet 6 Filed Dec.
E 2 G F 0 mm oJTIAX H a 2 3 lu M M A 1 .14 IJ m R mi ANX- MM 8 R Jim 0 w R J10 0 0. R R m 4 0 0 2 A MMI M W r MMIH R fw O m w in w Wm w i H Sept. 6, 1966 HANDLING OF MULTIPLE MATCHES AND FENCING IN MEMORIES Filed Dec. 51. 1962 FIG. 2F
H. E. PETERSEN ET'AL 11 Sheets-Sheet on DR on R ER DR HHEHH 113-3113-2 115-1 117 Se t. 6, 1966 H. E. PETERSEN ET Al. 3, 4
HANDLING OF MULTIPLE MATCHES AND FENCING IN MEMORIES 11 Sheets-Sheet 9 Filed Dec.
Sept. 6, 1966 Filed Dec.
MS'Z
H- E. PETERSEN ETAL HANDLING OF MULTIPLE MATCHES AND FENCING IN MEMORIES Sept. 6, 1966 H. E. PETERSEN ETAL 3,271,744
HANDLING OF MULTIPLE MATCHES AND FENCING IN MEMORIES 11 Sheets-Sheet 11 Filed Dec 0* we 1 Wm United States Patent Office 3,271,744 Patented Sept. 6, 1966 3,271,744 HANDLING OF MULTIPLE MATCHES AND FENCING IN MEMORIES Harold E. Peterson, Snratoga, Calif., and Michael Teig,
Yonkers, N.Y., assignors to International Business Machines Corporation, New York, N.Y., a corporation of New York Filed Dec. 31, I962, Ser. No. 248,595 15 Claims. (CI. 340l72.5)
The present invention relates to a data memory and more particularly to means for reading multiple matches of information out of such a memory and means for suppressing or fencing olf certain predetermined portions of the memory during a lead out operation.
While the principles of this invention may be applied to other types of memories. it would be particularly useful with an associative memory system. An associative memory system may be described generally as a system including word memory and means for simultaneously interrogating all words of the memory in accordance with selected data requirements. When this interrogation or association indicates that the interrogated portion of one or more words in the memory matches the selected data requirements, it is usually desired to extract the entire matching word or parts thereof from memory. A usual mode of operation is to interrogate a multiple word memory in accordance with association data and to register an indication of those words which match the association data. Thereafter. the matching words or portions thereof are read out to utilization circuits. Generally the words are read out serially by word and either serially or parallel by bit.
One aspect of the present invention is directed toward reading multiple matching words serially by word out of memory after the match indication has been recorded in a match indicating register.
A copending application Serial No. 120,213, filed June 28, l9nl, and assigned to the assignee of the present invention discloses circuitry for use in connection with an associative memory wherein multiple matches of data in a single column of memory are recorded and are scqucntially read out. The present invention provides for the interrogation and read out of an mxn word memory matrix with selective suppression or fencing out of predetermined portions of the memory.
It is a primary object of the present invention to pro vide improved memory read out apparatus.
It is another object of this invention to provide apparatus for sequentially reading out of memory selected 1' words in accordance with the setting of storage elements in a detector plane corresponding to addresses in memory of the words which are to be read out.
Another object of this invention is to provide apparains for reading from a memory selected words and for fencing out or suppressing selected areas of the memory from which words are not to be read.
A further object of this invention is to provide apparatus for reading from memory selected words and for fencing out or suppressing selected areas of the memory from which words are not to be read out by storing the fencing data in one or more fence planes.
It is a feature of this invention that certain portions of the memory may be isolated or fenced to exclude from read out any matching word that falls outside the fenced area. In addition to the foregoing mode of operation, the fencing feature may be used in other ways. For
ill
(ill
example, the memory may store a large number of names and addresses, for example, the names and addresses of the subscribers to a large number of publications. A fencing plane may be used to store the memory addresses of those subscribers to a particular publication. It may then be desirable, using two subscription lists (that is fencing planes) and to manipulate these planes in various ways. The memory may be interrogated in accordance with one subscription list and thereafter the subscribers to the first list may be checked against the subscribers in a second list to determine which ones were duplicated on both lists. The first list may be checked for the presence of names on one or more additional lists; for the presence on one additional list but not on a third list; or for the presence on either one of two additional lists.
Another feature of this invention is logical combination of the data in the detector plane and the fence planes may be accomplished whereby the read out of a word of memory may be dependent selectively upon the presence of corresponding stored indications in the detector plane and in all fence planes, or in at least one fence plane, or in only one fence plane.
The foregoing and other objects, features and advantages of the invention will be apparent from the follow ing more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings.
in the drawings:
FIGURE 1 is a block schematic of the entire system.
FIGURE 2 shows the arrangement of FIGURES 2A through 2? which form a composite circuit schematic of the system.
FIGURE 3 shows the arrangement of FIGURES 3A and 3B which form a partial schematic diagram.
FIGURE 4 shows another partial schematic diagram.
FIGURE 5 shows a partial schematic diagram of another embodiment.
In general, the system comprises a memory having a detector plane, at least one fence plane and two shift registers. The memory is first interrogated in accordance with a given criteria and the addresses of words matching the interrogation criteria are stored in the detector plane. The multiple columns of the detector plane are then interrogated in parallel and a column shift register is set in accordance with the columns storing addresses. At the same time the row shift register is set in accordance with the rows containing data. The row shift register is reset and the columns are thereafter interrogated sequentially. The first column is interrogated and row registers corresponding to addresses in the first column only are set. The row registers are interrogated and corresponding words in memory are read out. After read out of the first column, the second column is interrogated and again row registers are set. The reading out column-by-column is continued until all columns have been read out at which time a completion-of-readout indicator is actuated.
One or more fence planes may be provided for use in connection with the detector plane. The fence planes may be set to suppress the read out of given areas of the memory even though the detector plane indicates the presence of data therein which corresponds to the interrogation criteria.
Referring to FIGURE I, a block schematic of the system is illustrated. The rum word memory 10 may be, for example, a magnetic core memory consisting of 36 tiple bit words where the words are arranged in a 6 array. In this case ":6 and m:6. An nxm ctor plane 12. which may be physically a part of the iory 10, records multiple match indications received esponse to an interrogation of the memory 10 or in other suitable manner. The plane 12 has siX vercolumns in and six horizontal rows n. An in de- )r plane flip-flop tFF) unit 14, connected by a group nos 16, registers the 111 columns of detector plane 12 in :h data are recorded. .n m skipping shift register 18, connected by lines 21-- 23-24, 25-26, is associated with the FF unit 14 to trol sequential interrogation of the HI columns. The auts of the or register 18 are applied through a pinty of lines 28, OR gates and drivers 32 to coin- 'nt selection lines 34 of memory 10 to effect, in coopion with signals on other coincidence lines, the read out of words. The outputs of. in register 18 also are tied over lines 36. OR gates 38 and drivers 40 to lines to effect sequential interrogation of the detector plane -he detector plane 12 also is connected by a group of s 44 to an n detector plane flip-flop (FF) unit 46. 5 group of flip-flops is connected by lines 48-49, 50- 52-53 to an n skipping shift register 56. The outputs I register 56 are applied over lines 58, OR gates 60 and ters 62 to coincident selection lines 64 to cooperate h outputs on coincidence lines 34 to read out words in the memory 10. Coincidence of a signal on a line and a line 34 is effective to read out a word located he intersection of the two lines. \nother output from the a register 56. over line 66, is ilied in parallel to OR gates 68 and 70. The outputs OR gates 68 and 70 respectitely are effective to start :rrogation of the next or column of plane 12 which itains a set core and to reset FF unit 46. Upon comtion of the read out of all words indicated in the detecplane 12, an output from n register 18 is applied over ine 72 to actuate a completion indicator device 74. An uxm fencing plane 80, similar to detector plane 12, Jrovidcd into which fencing data are entered, by means t shown, to fence oll' portions, rows and/or columns. the detector plane 12 which are to be ignored during given read out operation. The fence plane is linked the lines 82 which are extensions. through switches of the lines 42. The fence plane 80 is connected by a Jup of lines 86 to an m fence plane flip-flop (FF) unit which is identical to FF unit 14. The FF unit 88 is nnected by lines 90-91 to an m fence plane gate unit 94, ferred to hereinafter as m gates 94. It is noted that oups of gang switches 96 and 98 may be set selectively the lines 23-24, or lines 23-24' to respectively exclude include m gates 94 in the circuit between FF unit 14 d m register 18. An n fence plane flip-flop (FF) unit 100 is connected the fence plane 80 by a group of lines 102. The FF tit 100 is identical to FF unit 88. The unit 100 is concted to an n fence plane gate unit 104 by lines 106- '7. The n gates 104 are identical to the m gates 94. to n gates 104 may be included selectively in the lines -51 or 50'5l' between FF tmit 46 and It register 56 groups of switches 108 and 110.
Each time a word is read out of memory 10, a signal applied over a line 113 to an OR gate 115 and over a to 117 to an OR gate 118. The output of OR gate 118 applied over a line 120 to advance the n register 56. second input to the OR gate 118 is by means of a witch 122 which may be operated manually or otherwise i apply an advance pulse to n register 56. Similarly, a vitch 124 is provided to apply an advance pulse through R gate 68 to the I register 18. A pair of switches 126 ad 128 are provided for resetting the FF units 88, l4, [l0 and 46, the reset pulse to FF 100 and 1 F 46 being aplied through OR gate 70. A switch 130 is provided 4 for applying an initial interrogation pulse in parallel through a line 132 to all OR gates 38.
Hereinafter and in the claims, the detector plane 12, fence plane 80, as well as the various fence plane and detector plane gate and flip-flop units may also be referred to as registers.
Referring to FIGS. 2A through 2F, a preferred embodiment of the system schematically illustrated in FIG. 1 is shown. FIG. 2 shows the arrangement of FIGS. 2A through 2F to form a composite schematic.
While the embodiment shown in FIGS. 2A through 2? has values of n=6 and m---6 and is illustrated as comprising a core memory, it will be understood that this is merely illustrative. Normally much larger memories will be utilized and various changes, including the substitution of other types of memories may be made without departing from the scope of the invention.
The system will be described first without use of the fence plane 80. Therefore. switches 84 (FIG. 2B), 96, 98 (FIG. 2B), 108 and 110 (FIG. 2D) are set to the positions shown.
Initially, the memory 10 is interrogated in accordance with usual associative memory techniques or, in some other way, the cores in plane 12 are set in accordance with the words which it is desired to read out. To start read out of the desired words from the memory 10, the switches 126 and 128 (FIGS. 2A and 2C) are closed momentarily to reset FF units 88, 14, 100 and 46 to their 0 states.
The switch 130 (FIG. 2E) is closed momentarily to apply a signal from a power source represented by terminal over the line 132, where it is applied in parallel to a group of six OR gates 38. The output of the OR gates are applied to a group of six drivers 40 which apply currents through six lines 42 linking the m columns of core plane 12, through switches 84 to ground. For each core in the plane 12 which is in its set condition the current in the corresponding line 42 induces a current in the corresponding lines 16 and 44. The cores of planes 12 and 80 are of the type which may be read out nondestructively. A suitable core is described in an article by V. L. Ncwhouse which is published in the "Proceedings of the IRE," November 1957, pages 1484-1492. A core is described wherein the application of magnetizing pulses much larger than the coercive force do not give rise to permanent changes of magnetization provided that that duration of the pulses is sufliciently short. Other suitable non-destructive read out memory elements are multi-aperture devices, or two-core per bit devices where the cores are destructively but independently read out, whereby a stored bit may be read out twice.
The currents in lines 16 are applied to fiip-flops 14-1 through 14-6, setting corresponding flip-flops to their l states. The currents applied to lines 44 are similarly applied to flip-flops 46-1 through 46-6. For each flipflop 14 which is set to its 1 state. an output is applied through corresponding lines 21. 23 and 25 to the m register 18. For each flip-flop 14 which is not set to its 1 state, an output is applied through corresponding lines 22-24 and 26 to the in register 18. Thus, of each air of line groups 21-23-25 or 22-24-26, one will have a signal thereon whereas the other will not. Similarly. the O and l outputs of FF unit 46 are applied over lines 48, 50. 52 or 49, SI. 53 to the n register 56.
Before proceeding with the description of the circuit, the n and m registers 18 and 56 will be described. Since registers 18 and 56 are identical. the description of one will sutlice for both. The in register 18 includes seven flip-flops -1 through 1511-7. These flip-flops have their 0 and 1 inputs arranged at the bottom and their 0 and l outputs arranged at the top. Each flip-flop 15! is a conventional flip-flo which switches to its 1 state when a signal is applied to the l input and which. in the 1 state, provides an output from the 1 output terminal.
Similarly. a signal applied to the input switches the flip-flop to its 1) state providing an output on the 0 output terminal. The flip-flops 150-1 through 150-6 correspond to the six at columns of cores in the plane 12 whereas FF 150-7 is responsive to an output from FF 1511-13 to indicate that all six columns of the plane 12 have been interrogated.
It is not necessary to reset registers 18 and 56 to their 0 states since the e registers will be set in accordance with the outputs of the planes 12 and 80. The m register 18 is started by closing the switch 124 (FIG. 213) to apply a pulse from the power source indicated by terminal 152 through the OR gate 68 to a line 154. The line 154 branches into lines 156 and 158. Depending upon the contents of the detector plane 12, one or more of the lines 25 may have a signal thereon. The input on line 154 is attractive to flip to its 1 state the first flip-flop 150 corresponding to the line 25 which has a signal thereon. If a signal is present on the first line 25-1, the signal on line 158 gates that signal through an AND gate 160-1 and the same signal on line 156 gates the output of AND 160-1 through an AND gate 162-1 whereby it is applied to the 1 input of FF 150-1.
If there is no signal on line 25-1. then there must be a signal on a line 26-1 which is connected to the 0 terminal of the same flip-flop 14-1 that applies signals to line 25-1. Therefore. the signal on line 158 is gated through AND gate 164-1. through an OR gate 166-1 uherc it is applied to AND gate 160-2 to gate through a signal on the line 25-2 to AND gate 162-2 and to the 1 in ut terminal of FF 150-2. If there is no signal on line 25-2, there will he one on line 26-2 to gate the signal on line 158 through AND gate 164-2. Thus, it is seen that a signal applied to the line 154 is applied through line 158, AND gates 164 and OR gates 166 to the first AND gate 160 corresponding to a 1 input on a line 25.
When flip-flop [50-1 is in its 1 state, its output is a plied to an AND gate 170-1 and OR gate 166-1. The 1 outputs of subsequent flip-flops 150 are applied to AND gates 170 corresponding to the next succeeding flip-flop.
The gates 170 cllcct the turning off of a flip-flop 150 when the next succeeding pulse is applied to the line 156. After setting the first flip-flop 150 by the pulse from line 154 the next succeeding AND gate 160 is conditioned through the OR gate 166 corresponding to the flip-flop 159 which is in its 1 state. Thus. subsequent pulses on line 158 are superfluous whereas the same pulses on line 156 are effective to turn oil the flipflop 150 which is on and to turn on the next conditioned flip-flop 150.
The output from an actuated flip-flop 150-1 through 150-6 is applied to corresponding lines 28 and 36. During operation. successive advance signals applied to the line 66 hy n register 56 and through OR gate 68 to the line 154 successively advance the m register 18 until the last m column containing a set core is read out. The next advance pulse on line 154 then switches the fliptlop 1507 to its I state, applying an output signal on line 72 to actuate the completion indicator device 74 to indicate completion of thc read out. This device 74 may be a hell, light, relay, switch, etc.
The I: register 56 operates in an identical manner. the corresponding components being designated similarly to those in unit 18; however, those in 56 contain a prime reference.
To continue with the system description, assume that only los cores which are shown as solid black in m columns 1, 3. and 6 and in n rows 1, 2, 3, 4, 5 and 6 of core plane 12 (FIG. 2E) are set to indiate words which are to be read out of memory 10. The switch 130 (FIG. IE) is closed momentarily and currents on the lines 42 induce output pulses on lines 16-1, 16-3, 16-5, 16-6, 44-1, 44-2. 44-3. 44-4, 44-5 and 44-6. Accordingly, flip-flops 14-1, 14-3, 14-5, 14-6, 46-1, 46-2, 46-3, 46-4, 46-5 and 46-6 are set to their 1 states and signals 6 are applied to m register 18 through lines 25-1, 25-3, 25-5, 25-6, 26-2 and 26-4, and to n register 56 through lines 52-1, 52-2. 52-4. 52-5 and 52-6.
The switch 214 (FIG. 2B) is closed momentarily and the resulting signal on line 158 gates the signal on line 25-1 through AND gate 160-1; the signal on line 156 gates the output of AND 160-1 through AND 162-1 to the 1 input terminal of FF 150-1, setting this flip-flop to its 1 state and applying a signal to the corresponding lines 28-1 and 36-1 and to AND gate 170-1 and OR gate 166-1. The switch 122 (FIG. 2D) is not closed at this time and therefore no signals are applied to the lines 58. With a signal on line 34-1 (FIG. 2F) but not on any line 64 (FIG. 2F), read out of information from memory 10 is not affected.
Next, the switch 128 (FIG. 2C) is closed momentarily to reset FF unit 46. The signal on line 36-1 is applied to OR gate 38-1 and, through driver 40-1, applies a pulse to line 42-1. The signal on line 42-1 is effective through the set core at the intersections of lines 44-2, 44-3 and 44-4 with line 16-1 to induce currents in the latter three lines 44. The current in line 16-1 is superfluous since FF 14-1 was previously set to its 1 state and has not been reset. The currents in lines 44-2, 44-3 and 44-4 are effective to set corresponding flip-flops 46-2, 46-3 and 46-4 to their l states.
The output of FF 44-2 is applied over line 52-2 to AND gate 160-2' in n register 56. Switch 122 is closed momentarily to apply an advance signal through OR gate 118 and line 120. The line 1-20 branches into lines 156' and 158'. Since there is no signal on line 52-1, the signal on line 158' advances, in the manner described hereinbefore, to gate the signal on line 52-2 through AND gate 160-2' to AND gate 162-2' where it is gated by the signal on line 156' to the 1 input of FF 150-2, setting this flip-flopto its 1 state.
FF 150-1 in m register 18 and FF 150-2' in n register 56 are now in their 1 states and are applying signals to corresponding lines 28-1 and 58-2. Coincident currents on lines 34-1 and 64-2 (FIG. 2F) thus read out the word in memory 10 at the address defined by the intersection of these lines. The read out pulse is applied over line 113-1 to OR gate and over line 117 to OR gate 118.
The advance pulse from OR gate 118 to lines 156' and 158 sets FF -3' to its 1 state and resets FF 1511-12 to its 0 state. The word at the intersection of lines 34-1 and 64-3 is read out. The resulting signal on line 112-1 advances in register 56 to set FF 150-4' and resets FF 150-3. The corresponding word is read out of memory 10.
Since no other flip-flops 46 are set to the 1 state. the advance pulse on lines 156' and 158' sets FF 150-7 to its 1 state producing an output on line 66 which is applied to OR gates 68 and 70. The output from OR gate 70 resets H unit 46. The output of OR gate 68 is applied to the lines 156 and 158 to switch to its 1 state the next flip-flop 150 associated with a flip-flop 14 which is in its 1 state.
In the present example the next flip-flop 14 which has been set to its 1 state is FF 14-3. Therefore, an output is applied to the line 36-3, through OR gate 38-3 and driver 40-3 to line 42-3 to induce outputs on lines 44-1 44-2 and 44-4, setting flip-flops 46-1, 46-2 and 46-4 to their 1 states. Current also is induced in line 16-3 but is superfluous since FF 14-3 is arcady in its 1 state.
The switch 122 (FIG. 2D) is closed momentarily to apply an advance pulse through OR gate 118 to n register 56. This pulse sets FF 150-1' to its 1 state. At this time coincidence of pulses on lines 34-3 and 64-1 efl'ects read out of the word in memory at the corresponding address. The resultant output on line 113-3 to OR gate 115 is applied through OR gate 118 to switch FtF 150-1' to its 0 state and to switch FF 1504' to its 1 state. At this time a coincidence of pulses on lines 34-3 and 4-2 effects the read out of the word in memory 10 at 1e corresponding address. The n register 56 is advanced turn on FF 150-4' causing the corresponding word 1 he read out. Since no more flip-flops 46 are in the 1 ate, the resulting output pulse form OR gate 115 is fed nck to turn FF 150 -7' on, to again rcsct Fl" unit 46 and l advance in register 18.
in the foregoing manner or columns and 6 of piano 2 are interrogated sequentially, setting corresponding ip-fiops 46. time the flip-flops 46 are set, the viteh 122 is closed to start the sequential advancing of register 56 with the resultant read out of words in temory 10.
When the last in column has been completely read out, ie resulting output pulse from memory is effective trough register 56 and line 66 to advance m register it to turn FF 150-7 on which produces an output on no 74 to completion indicator device 74 to indicate that ll words corresponding to cores set in the detector plane 2 have been read out.
Fencing operation Under special conditions it may be desired to inhibit |e read out of particular sections of the memory 10, wen though the detector plane 12 contains match indicaons in those inhibited areas. In such an event, the inibited area is fenced out whereby the interrogation auto- .atically skips those areas.
Assume that it is desired to fence off columns 2, 3 and and rows 2, 4 and 6 of detector plane 12. To accomplish tlS fencing, at least one core is set in each of the unt'enced )lumns 1, Sand 6 and the unfenced rows 1, 3, and 5, of nce plane 80. Further. it is required that none of the \rcs in the fenced off rows and columns he set. Obviousthe connections to the (l to 1 inputs or from the (l and l .itputs of FF units 88 and 100 could be reversed wherev the set cores could be in the rows and columns which 'e to be fenced out.
Accordingly, the seven cores shown as solid in plane I are set. Assume also that cores are set in plane 12 a in the foregoing example of multiple match read out. he switches 84, 96, 98, 108 and 110 are set to their alterite positions. Switches 126 and 128 are closed momenrily to reset FF units 88, 14, 100 and 46. The switch 10 is closed momentarily to provide interrogation of 1 columns of plane 12, and as in the prior example, outit signals are derived on lines 16-1, 16-3, 16-5, 16-6, l-l, 44-2. 44-3, 44-4, 44-5 and 44-6, setting cor- :sponding flip- flops 14 and 46 to their 1 states. The sigllS on lines 42 flow through the switches 84, lines 82 1d the associated columns of fence plane 80. The cur- :nts flowing through fence plane 80 induce currents in res 86-1, 86-5, 86-6. 102-1, 102-3 and 102-5.
Accordingly, flip-flops 88-1, 88-5, 88-6, 100-1, 100-3 1d 100-5 are set to their 1 states. Referring now to gate tit 94 (FIG. 2B). the odd number gates 94-1, 94-3, l-5, etc. are AND gates. The even-numbered gates l-2, 94-4, 94-6, etc. or OR gates. The AND gates 94 'e connected to the 1 outputs of flip- flops 88 and 14 hereas the OR gates 94 are connected to the 0 outputs flip- flops 88 and 14. Similarly, in gate unit 104, the ld-nnm bered AND gates 104 are connected to the l itputs of the flip- flops 100 and 46 whereas the evenimbered OR gates 104 are connected to the 0 outputs flip- flops 100 and 46.
FF 14-1 is set to its 1 state and therefore applies an put to AND gate 94-1. FF 88-1 is set to its 1 state id therefore applies a second input to AND gate 94-1 gate through the signal from FF 14-1 and thus set e FF 150-1 to its 1 state when the advance signal is lplied by closing switch 124. At this point the effect the currents on lines 44 and 102 is unimportant since e FF units 100 and 46 will be reset to their 0 states by using switch 128 (FIG. 2C). The output of FF 150-1 applied through line 36-1 to OR gate 38-1 and driver Ill 8 40-1 to line 42-1. Again outputs are derived on lines 16-1, 86-1, 44-2, 44-3, 44-4, 102-1, 102-3 and 102-5 to set corresponding flip-flops in units 100 and 46 to their 1 states. The units ll tilt-1 and FF 14-1 were not reset.
The switch 122 is closed to apply an advance signal. Since FF 150-3' which is the first flip-flop [50' corresponding to flip- flops 100 and 46 both of which are in their 1 states, the signal on lines 156' and 158' advances to set FF 150-3' in its 1 state. At this time, FF 150-1 is still set in its 1 state and coincidence of signals on lines 34-1 and 64-3 is effective to read the word out of memory 10 at the corresponding address. The resultant output on line 117 applies an advance pulse to n register 56. The advance signal proceeds down the lines 156 and 158, in n register 56, seeking the next register position corresponding to flip fiops 100 and 46 both of which are set to their 1 states. In accordance with the stated example, there is no such coinicidence of flip-flops in their 1 states and the advance signal is propagatcd through AND gates 164' and OR gates 166 to set flip-flop 150-7' to its 1 state. An advance signal over line 66 resets FF units 100 and 46 and applies an advance signal to in register 18.
The remaining flip-flops 14 which are set to their 1 states are FF 14-3, 14-5 and 14-6. The remaining flipllops 88 which are set in their 1 states are FF 88-5 and 88-6. As in the case of FF units 100 and 46, there must he coincidence of 1 states in corresponding flip- flops 88 and 14 in order to have a corresponding flip-flop 150 set to its 1 state. Thus, FF 150-5 and 150-6 may be set to their 1 states. Therefore, the advance signal through OR gate 68 advances through In register 18 to set FF 150-5 in its 1 state, thus producing an output on lines 28-5 and 36-5. The signal on line 36-5 is applied through OR gate 38-5 and driver 40-5 to lines 42-5 and 82-5. The signals on lines 42-5 and 82-5 induce outputs on lines 16-5 and 86-5, both of which are superfluous since the corresponding flip-flops 14-5 and 88-5 are already set in their 1 states. Currents also are induced on lines 44-1, 44-2, 44-3, 44-4, 44-5, 102-1, 102-3 and 102-5. Flip-flops 46-1, 46-2, 46-3. 46-4, 46-5, 100-1, 100-3 and 100-5 are set to their 1 states. The switch 122 is closed to apply an advance signal to n register 56. This signal advances down the lines 156' and 158' seeking a flip-flop position corresponding to coincidcntly set flip- flops 100 and 46. The first such flip-flop is FF 150-1' and the word corresponding to lines 34-5 and 64-1 is read out of memory 10.
Since row 2 of plane is fenced out and FF -2 is not set, the setting of FF 46-2 is ineffective. FF 100-3 and FF 46-3 are both set so the word corresponding to lines 34-5 and 64-3 is read out. Row 4 is fenced out and is thus skipped. FF 100-5 and FF 46-5 are both set so the word corresponding to lines 34-5 and 64-5 is read out. Neither FF 100-6 nor 46-6 is not set and the advance signal following read out of the word at the intersection of lines 34-5 and 64-5 proceeds to set flip-flop -7' to produce a reset output from OR 70 and an advance signal to m register 18. This advance pulse advances to set FF 150-6. The resultant interrogation of column six of planes 12 and 80 sets flip-flops 46-3, 46-6 and 100-1. Flip-flops 14-6 and 88-6 remain set.
When switch 122 (FIG. 2D) is closed, the signal on lines 156 and 158' fail to detect any coincidence on flipflops 46 and 100 so FF 150-7' is set to its 1 state. The output of FF 150-7' resets FF units 46 and 100 and advances m register 18 to set FF 150-7. The output of FF 150-7 signals completion of the operation.
Multiple [mice planes Referring to FIGURES 3A and 3B. a variation of a portion of the system shown in FIGURFS ZA-ZF is illustrated wherein a detector plane 112, imilar to detector plane 12 of FIGURE 2E, and two fence planes and 280, each similar to fence plane 30 in FIGURE 25 are provided. The illustration in FIGURE 3 is on a smaller scale wherein 3 and m :--3. whereas in FIGS. ZA-Z F,
9 n-G and t n--16. For convenience in comparison with the embodiment in FIGS. ZA-ZF, consider that the three n lines and the three in lines from each plane 112, 180 and 280 corres ond to the first three such lines in the embodiment of FIGURES ZA-ZF.
This embodiment illustrates that a novel and useful system may be provided by AN Ding the contents of a detector plane with the contents of two or more fence planes.
The detector plane 112 and the fence planes 180 and 280 are coiucidently interrogated by signals on the lines 142 which correspond to the lines 42-82 in FIGURE 2E. Assume that the cores A1, A3, A5, A6 and A9 in plane 112 have been set. Assume that cores B1, B3. B and H9 in plane 180 and cores C1, C5, C6 and C9 in plane 280 have been set.
The n outputs of plane 112 are on lines 144-1, 144-2, 144-3. connecting to the I inputs of corresponding flipll ps 146-1. 146-2. 146-3. Similarly the m outputs are on lines 1161, 116-2 and 116-3, connecting respectively to the 1 inputs of flip-flops 114-1, 114-2 and 114-3.
The n output lines 202 and 302 of planes 180 and 280 respectively. similarly connect to the 1 inputs of corresponding llip-llops 200 and 300. The at output lines 186 and 286 of planes 180 and 280 respectively connect to the 1 inputs of flip-flops 188 and 288. As in the case of flipllop units 88 and 14, in FIGURES 2A and 213. a common reset line 190 is provided for m flip-flop units 114, 188 and 288. Similarly, a common reset line 192 is provided for n flip- flop units 146, 200 and 300.
A gating unit 194 generally corresponding in function to the gating units 94 in FIGURE 2 is interposed between the m llip-flop units 114, 188 and 288 and the m register 18. Similarly, a gating unit 204 corresponding to unit 104 in FIG. 2 is interposed between :1 flip- flops 146, 114, 200, 188, 300 and 288 and the register flip- flop units 146, 200 and 300 and the n register 56.
AND gates 204-1. 204-3 and 204-5 have as inputs the l outputs of n tIip- llops 146, 200 and 300 as follows:
146-1, 200-1, 300-1 connected to AND 204-1 146-2, 200-2, 3002 connected to AND 204-3 146-3, 200 3, 300-3 connected to AND 204-5 OR gates 204-2, 204-4 and 204-6 have as inputs the a outputs of n liipllops 146, 200 and 300 as follows:
146-1, 200-1. 300-1 connected to OR 204-2 146-2, 200-2, 3002 connected to OR 204-4 146-3. 200-3, 300-3 connected to OR 204-6 AND gates 194-1. 194-3 and 194-5 have as inputs the 1 outputs of I11 flip-flop 114, 188 and 288 as follows:
114-1, 188-1 and 288-1 connected to AND 194-1 114-2, 188-2 and 288-2 connected to AND 194-3 114-3, 188-3 and 288-3 connected to AND 194-5 OR gates 194-2, 194-4 and 194-6 have as inputs the 0 outputs of m flip-flops 114, 188 and 288 as follows:
114-1, 188-1 and 288-1 connected to OR 194-2 114-2, 188-2 and 288-2 connected to OR 194-4 114-3, 188-3 and 288-3 connected to OR 194-6 The outputs of the AND gates 194-1, 194-3 and 194-5 are applied to lines 23-1", 23-2" and 23-3" as the inputs to the first three stages of the register 18, just as were the outputs of the AND gates 94 in FIGURE 2. The outputs of the OR gates 194-2, 194-4 and 194-6 are applied to lines 24-1", 24-2" and 24-3". The outputs of AND and OR gates 204 similarly are applied to lines 50" and 51" as inputs to register 56.
Thus, it is seen that, for example, the coincidence of signal on the n lines 144-1, 202-1 and 302-1 will produce an output from AND gate 204-1 to condition the first stage of the register 56. Similarly, the coincidence of outputs on m lines 116-1, 186-1 and 286-1 will produee an output from AND gate 194-1 to condition the first stage of the register 18. Thus, with the first stages of both registers 18 and 56 set, read out is effected from a corresponding address in the memory 10. When there is not the foregoing coincidence of outputs, the corresponding OR gates 194 or 204 are actuated, causing the interrogation pulse to the registers 18 and S6 to be advanced to the next stages which are conditioned.
Obviously, switches may be provided for selectively including either or both fencing planes and 280.
With the cores set as indicated in FIG. 3, there is coincidence of set cores in all three planes in the following three instances: A1, B1, C1; A5. B5, C5; and A9, B9, C9. Accordingly, the three words corresponding to addresses A1, A5 and A9 will be read out of the memory in the manner described with respect to FIGURE 2.
Referring 10 FIGURE 4, two circuit blocks 294 and 304 are shown which may be substituted in FIGURE 3 for blocks 194 and 204 respectively. This embodiment illustrates another variation of the system wherein the contents of the detector plane 112 are ANDed with the contents of either fence plane 180 or 280.
The inputs to the blocks 294 and 304 are the some as the inputs to the blocks 194 and 204 in FIGURE 3. These inputs are the 0 and 1 outputs of the flip- flops 114, 146, 188, 200, 288 and 300, and are so indicated in the lefthand margin of FIGURE 4.
In the circuit block 304, three OR gates designated 310-1, 310-2 and 310-3 are provided. OR gate 310-1 has as inputs the 1 output of flip-flops 200-1 and 300-1. OR gate 310-2 has as inputs the 1 outputs of flip-flops 200-2 and 300-2. OR gate 310-3 has as inputs the 1 outputs of flip-flops 200-3 and 300-3.
In block 294 three OR gates 312-1, 312-2 and 312-3 are provided. OR gate 312-1 has as inputs the 1 outputs of flip-flops 188-1 and 288-1. OR gate 312-2 has as inputs the l outputs of flip-flops 188-2 and 288-2. OR gate 312-3 has as inputs the 1 outputs of flip-flops 188-3 and 288-3.
Thus it is apparent that a given OR gate 310 or 312 will produce an output when either of the flip-flops connected as inputs is in its 1 state. Similarly, each gate 310 and 312 will produce an output when both of its inputs are in their 1 states.
The outputs of OR gates 310-1, 310-2 and 310-3 are applied respectively to AND gates 304-1, 304-3 and 304-5. The second inputs to these AND gates are the 1 0:11pm: of flip-flops 146-1, 146-2 and 146-3 respective y.
The outputs of OR gates 312-1, 312-2 and 312-3 respectively are connected as inputs to AND gates 294-1, 294-3 and 294-5. The second inputs to these AND gates are the 1 outputs of flip-flops 114-1, 114-2 and 114-3, respectively.
The OR gates 304-2, 304-4, 304-6, 294-2, 294-4 and 294-6 each have three inputs which are the 0 outputs :11 the flip- flops 114, 146, 188, 200, 288 and 300 as folows:
OR 304-2 146-1 200-1 300-1 OR 304-4 146-2 200-2 300-2 OR 304-6 146-3 200-3 300-3 OR 294-2 114-1 188-1 288-1 OR 294-4 114-2 188-2 288-2 OR 294-6 114-3 1 88-3 288-3 It is thus apparent that coincidence of a set core in plane 112 with a set core in either or both of planes 180 and 280 will produce an output from corresponding AND gates 304 and 294 to etl'ect read out of a corresponding word from memory.
Referring to FIGURE 5, circuit blocks 394 and 404 are shown which may be substituted in FIGURE 3 for blocks 194 and 204 respectively. This embodiment illustrates a further variation of the system wherein the contents of the detector plane 112 may be ANDed with the contents of one or the other of the planes 180 and 280, but not with both. i
It will be noted that the circuits in FIGURE 4 and FIG- ZE 5 are substantially identical but have the following ferences. First. AND gates 410 and 412 have been ostituted for the OR gates 310 and 312 of FIGURE 4. condly, each of the AND gates has as its two inputs the output of a flip-flop 238 or 300 and the output of a u-fiop 188 or 200, Thus the circuit of FIGURE is ective to produce the read out of a word corresponding an address set in a core in the detector plane 112 proled that a corresponding core is set in the detector plane 0 but is not set in the corresponding core in fence me 180. Third, lhc 0 outputs of flip- flops 288 and 300 2 applied as inputs to the OR gates 404 and 394 and the outputs of llip-flops I88 anti 200 are applied as inputs thesc OR gates. Thus, in accordance with the setting cores in planes H2, 180 and 280 as shown in FIG- Rii 3, only the word corresponding to the set core A6 plane 112 will he read out.
While the invention has been particularly shown and scribed with reference to preferred embodiments thereit will be understood by those skilled in the art that rious changes in form and details may be made therein thou: departing from the spirit and scope of the inven- What is claimed is:
1. In a data processing system a multiple word data memory having n rows and m columns,
a first register having n rows and m columns of register elements corresponding to the n rows and in columns of said memory, one element corresponding to each word of said memory with selected ones of said elements set to a given state,
a second register having m stages corresponding to the m columns of said first register,
a third register having I: stages corresponding to the n rows of said first register, first skipping shift register having in stages corresponding to the in stages of said second register, operable in response to the setting of stages of said second register for selling corresponding stages of said first skipping shift register, and operable in response to successive interrogation inputs to provide outputs successively from set stages thereof,
a second skipping shift register having n stages corresponding to the n stages of said third register, operable in response to the setting of stages of said third register for setting corresponding stages of said second skipping shift register, and operable in response to successive interrogation inputs to provide outputs successively from set stages thereof,
means for simultaneously interrogating all m columns of said first register to set stages of said second and third registers corresponding to said in columns and 11 rows respectively which have elements set to said given state,
means for applying resetting inputs to said third register,
means for applying outputs from said m stages of said first skipping shift register to corresponding columns of said memory and said first register,
means for applying outputs from said u stages of said second skipping shift register to corresponding rows of said memory,
means for applying interrogation inputs to said first skipping shift register,
means for applying interrogation inputs to said second skipping shift register.
2. The invention of claim I wherein said means for pplying interrogation inputs to said first skipping shift :gislcr comprise means for applying an initial interrogaon input and means for applying the last said successive ulput from said second skipping shift register.
3. The invention of claim I wherein said means for pplying inlcrrogulion inputs to said second skipping shift register comprise means for applying an initial interrogation input and means for applying inputs which set stage of said second skipping shift registers.
4. The invention of claim 1 having indicator means responsive to the last said successive output from said first skipping shift register.
5. in a data processing system a multiple word data memory having n rows and m columns,
a first register having :1 rows and m columns of register elements corresponding to the n rows and m columns of said memory, one element corresponding to each word of said memory with selected ones of said elements set to a given state,
a second register having n rows and m columns of register elements corresponding to the n rows and in columns of said memory, one element corresponding to each word of said memory with selected ones of said elements set to a given state,
third and fourth registers each having an stages corresponding to the m columns of said first and second registers respectively,
first logical means having in stages corresponding to the m stages of said third and fourth registers, each stage being set when the corresponding stages of said third and fourth registers are set,
a first skipping shift register having m stages corresponding to the in stages of said first logical means, scttable in accordance with the setting of corresponding stages of said first logical means, and operable in response to successive interrogation inputs to provide outputs successively from set stages thereof,
fifth and sixth registers each having it stages corresponding to the n rows of said first and second registers respectively,
second logical means having n stages corresponding to the n stages of said fifth and sixth registers, each stage being set when the corresponding stages of said fifth and sixth registers are set,
a second skipping shift register having :1 stages corresponding to the n stages of said second logical means, settable in accordance with the setting of corresponding stages of said second logical means, and operable in response to successive interrogation inputs to provide outputs successively from set stages thereof,
means for simultaneously interrogating all m columns of said first and second registers for setting stages of said third and fifth registers corresponding to the m columns and n rows respectively of said first register which have elements set to said given state, and for setting stages of said fourth and sixth registers corresponding to the m columns and in rows respectively of said second register which have elements set to said given state,
means for applying resetting inputs to said fifth and sixth registers,
means for applying outputs from said m stages of said first skipping shift register to corresponding columns of said memory and said first and second registers,
means for applying outputs from said n stages of said second skipping shift register to corresponding rows -of said memory,
means for applying interrogation inputs to said first skipping shift register,
means for applying interrogation inputs to said second skipping shift register.
6. The invention of claim 5 wherein said means for applying interrogation inputs to said lirst skipping shift applying interrogation inputs to said second skipping shift register comprise means for applying, an initial interrogation input and means for applying inputs which are outputs from said memory in response to coincident application to said memory of an output from a set stage of srud first skipping shift register and an output from a set stage of said second skipping shift register.
8. The invention of claim wherein said means for applying resetting inputs to said fifth and sixth registers comprise means for applying initial resetting inputs and means for applying the last said successive output from said second skipping shift register.
9. The invention of claim 5 having indicator means responsive to the last said successive output from said first skipping shift register.
10. in a data proce sing system a multiple \void data memory having n rows and in columns,
a first register having 11 rows and in columns of register elements corrc-pomling to the 11 rows and m columns of said memory. one element corresponding to each word of said memory with selected ones of said elements set to a given state,
a second register having it rows and m columns of register elements corresponding to the n rows and in columns of said memory, one element corresponding to each word of said memory with selected ones of said elements set to a given state,
third and fourth registers each having m stages corresponding to the m columns of said first and second registers respectively,
first logical means having m stages corresponding to the in stages of said third and fourth registers, each stage being set when the corresponding stage of either of said third and fourth registers is set,
a first skipping shift register having in stages corresponding to the m stages of said first logical means, sen-able in accordance with the setting of corresponding stages of said first logical means, and operable in response to successive interrogation inputs to provide outputs successively from set stages thereof.
fifth and sixth registers each having :2 stages corresponding to the n rows of said first and second registers respectively,
second logical means having it stages corresponding to the n stages of said fifth and sixth registers, each stage being set when the corresponding stage of either of said fifth and sixth registers is set,
a second skipping shift register having n stages corre sponding to the :1 tages of said second logical mean settahlc in accordance with the setting of corresponding stages of said second logical means, and operable in response to successive interrogation inputs to provide outputs uccessively from set stages thereof,
means for simultaneou ly interrogating all m columns of said first and econd registers for setting stages of said third and fifth registers corresponding to the m columns and n rows respectively of said first regis tcr which have elements set to said given state, and for setting stages of said fourth and sixth registers corresponding to the m columns and n rows respcctively of said second register which have elements set to said given state,
means for applying resetting inputs to said fifth and sixth registers,
means for applying outputs from said In stages of said first skipping shift register to corresponding columns of said memory and said first and second registers,
means for applying outputs from said n stages of said second skipping shift register to corresponding rows of said memory,
means for applying interrogation inputs to said first skipping shift register.
means for applying interrogation inputs to said second skipping shift register.
ll. In a data processing system a multiple word data memory having n rows and m columns,
a first register having it rows and in columns of register elements corresponding to the n rows and in columns of said memory. one element corresponding to each word of said memory with selected ones of said elements set to a given state,
a second register having I: rows and in columns of register elements corresponding to the n rows and in columns of said memory, one element corresponding to each word of said memory with selected ones of said elements set to a given state,
third and fourth registers each having in stages corrcspending to the in columns of said first and second registers respectively,
first logical means having m stages corresponding to said third and fourth registers. each stage being set when only one of the corresponding stages of said third and fourth registers is set,
a first skipping shift register having m stages corresponding to the in stages of said first logical means. scttahle in accordance with the setting of corresponding stages of said first logical means, and operable in response to successive interrogation inputs to pro vide outputs successively from set stages thereof.
fifth and sixth registers each having 11 stages coresponding to the n rows of said first and second registers respectively,
second logical means having n stages corresponding to the n stages of said fifth and sixth registers, each stage being set when one only of the corresponding stages of said fifth and sixth registers is set.
a second skipping shift register having n stages corresponding to the n stages of said second logical means, sctlable in accordance with the setting of corresponding stages of said second logical means, and operable in response to successive interrogation inputs to provide outputs successively from set stages thereof,
means for simultaneously interrogating all in columns of said first and second register for selling stages of said third and fifth registers corresponding to the m columns and n rows respectively of said first registcr which have elements set to said given stage, and for setting stages of said fourth and sixth registers corresponding to the m columns and n rows respectively of said second register which have elements set to said given state,
means for applying resetting inputs to said fifth and sixth registers.
means for applying outputs from said In stages of said first skipping shift register to corresponding columns of said memory and said first and second registers,
means for applying outputs from said it stages of said second skipping shift register to corresponding rows of said memory,
means for applying interrogation inputs to said first skipping shift register,
means for applying interrogation inputs to said second skipping shift register.
12. In a data processing system a multiple word data memory having n rows and m columns,
a plurality of first registers each having n rows and m columns of register elements corresponding to the n rows and m columns of said memory, one element in each said register corresponding to each word of said memory with said elements of said registers set selectively to given states,
a plurality of second registers each having m stages and each corresponding to one of said first registers.
a plurality of third registers each having 2: stages and each corresponding to one of said first registers,
a first logical circuit having m stages, each stage corresponding to a similar stage of all said second registcrs, each said stage of said first logical circuit being set when said similar stages of said second registers are set.
a first ski ping shift regi ter having in stages corresponding to the m stages of said first logical cir cult. scttahlc in accordance with the setting of corrc spouding stages of said first logical circuit. and operable in response to successive interrogation inputs to provide outputs successively from set stages thereof, second lo ical circuit having ll stages each stage corresponding to a similar stage of said third registers, each said stage of said second logical cir uit being set when said similar stages of said third registers are set, second skipping shift register having a stages corresponding to the n stages of said second logical circuit. settable in accordance with the setting of corresponding stages of said second logical circuit, and operable in response to successive interrogation inuts to rovide outputs successively front set stages thereof,
means for simultaneously interrogating all m columns of said first registers for setting stages of said secout] and third registers corresponding to the in columm and n rows respectively of said first registers uhieh have elements set to said given state,
lllLZllls for applying resetting inputs to said third rcgislers.
means for applying outputs from said m stages of said li st skipping shift register to corresponding columns of said mem ry and said first registers,
means for apphiug outputs from said it stages of said --econd skipping shitt register to Corresponding rows of said memory.
means for applying interrogation inputs to said first skipping shift register,
means for applying interrogation inputs to said second skipping shift register.
13. In a data processing system a multiple word data memory having it rows and in columns,
a plurality of first registers each having it rows and in columns of register elements corresponding to (hi: it rows and or columns of said memory. one element in each said regi ter corresponding to each word of said memory with said elements of said registers set selectively to given states.
a plurality of meond registers each having m stages and each corresponding to one of said first registers.
plurality of third registers each having ll stages and h rresponding to one of said first registers.
a first logical circuit having in stages. each stage corresponding to a similar stage of all said second reglstct's. each said stage of said first logical circuit being set when said similar stage of one of said sec ond |L{ll lC|'s, is set and said similar stage of at least one of the other said second registers is set,
a first ski ping shift register having in stages corresponding to the in stages of said first logical circuit. settable in accordance with the setting of correspond ing stages of said first logical circuit, and operable in response to successive interrogation inputs to provide outputs successively from set stages thereof,
a second logical circuit having n stages each stage corresponding to a similar stage of said third rcgis tcrs. each said stage of said second logical circuit hcing set when said similar stage of one of said third registers is set and said similar stage of at least one of: the other said second registers is set,
second skipping shift register having it stages orresponding to the n stages of said second logical circuit, suitable in accordance with the setting of corresponding stages of said second logical circuit. and operahle in response to successive interrogation inputs to provide outputs successively from set stages thereof,
means for simultaneously interrogating all in columns of said first registers for setting stages of said second and third registers corresponding to the m columns and n rows respectively of said first registers which have elements set to said given state,
means for applying resetting inputs to said third registers,
means for applying outputs from said In stages of said first skipping shift register to corresponding columns of said memory and said first registers,
means for applying outputs from said n stages of said second skipping shift register to corresponding rows of said memory,
means for applying interrogation inputs to said first skipping shift register,
means for applying interrogation inputs to said second skipping shift register.
14. In a data processing system a multiple word data memory having n rows and in columns.
a plurality of first registers each having it rows and m columns of register elements corresponding to the n rows and m columns of said memory, one element in each said register corresponding to each word of said memory with said elements of said registers set selectively to given states,
a plurality of second registers each having in stages and each corresponding to one of said first registers,
a plurality of third registers each having I: stages and each corresponding to one of said first registers,
a first logical circuit having m stages each stage corresponding to a similar stage of all said second registers, each said stage of said first logical circuit being set when said similar stage of one of said second registers is set and said similar stage of only one of the other said registers is set,
a first skipping shift register having or stages corresponding to the in stages of said first logical circuit, settable in accordance \tlllt the setting of corresponding stages of said first logical circuit, and operable in response to succe sive interrogation inputs to provide outputs succcssitely frotn set stages thereof.
a second logical circuit having It stages each stage corresponding to a similar stage of said third registers. each said stage of said second logical circuit being set when said similar stage of one of said third registers is set and said similar stage of only one of the other said registers is set.
a second skipping shift register having it stages corresponding to the n stages of said second logical circuit, scttahlc in accordance with the setting of corresponding stages of said second logical circuit, and operable in response to successive interrogation inputs to provide outputs successively from set stages thereof,
means for simultaneously interrogating all in columns of said first registers for setting stages of said scc- 0nd and third registers corresponding to the m columns and n rows respectively of said first registers which have elements set to said given state,
means for applying resetting inputs to said third registers,
means for applying outputs from said m stages of said first skipping shift register to corresponding columns of said memory and said first registers.
means for applying outputs front said u stages of said second skipping shift register to corresponding rows of said memory,
means for ap lying interrogation inputs to said first skipping shift register.
means for applying interrogation inputs to said second skipping shift register.
17 18 15. The invcnlion of uiuim 1 wherein said means for 3,108,257 10/1963 Buchhoiz 340172.5 applying resetting inputs to said third register comprise 3,121,2l7 2/1964 Sccber et a1. 340-1725 means for app1ying am initial resetting input and means 3.191.155 6/1965 Seeber et a1. 340-1725 For uppiying the last \Zlid successive output from said sec- 3.191.156 6/1965 Rath 340-1725 nnd \kipping \hifl register. 5 3,195,109 7/1965 Hehnkc 340172.S 3,199,082 8. 1965 Haiht 340-172.5
References Cited by the Examiner UNI'Hil) S'IIHFS PATENTS I'm n m gm was H L 72 1 HENON. ASJI'AINHI Exmniuvr. mums mam; Buchllnlz cl :1]. 340-1715 ROBERT C. BAILEY. Primary Iimminer.

Claims (1)

1. IN A DATA PROCESSING SYSTEM A MULTIPLE WORD DATA MEMORY HAVING N ROWS AND M COLUMNS, A FIRST REGISTER HAVING N ROWS AND M COLUMNS OF REGISTER ELEMENTS CORRESPONDING TO THE N ROWS AND M COLUMNS OF SAID MEMORY, ONE ELEMENT CORRESPONDING TO EACH WORD OF SAID MEMORY WITH SELECTED ONES OF SAID ELEMENTS SET TO A GIVEN STATE, A SECOND REGISTER HAVING M STAGES CORRESPONDING TO THE M COLUMNS OF SAID FIRST REGISTER, A THIRD REGISTER HAVING N STAGES CORRESPONDING TO THE N ROWS OF SAID FIRST REGISTER, A FIRST SKIPPING SHIFT REGISTER HAVING M STAGES CORRESPONDING TO THE M STAGES OF SAID SECOND REGISTER, OPERABLE IN RESPONSE TO THE SETTING OF STAGES OF SAID SECONE REGISTER FOR SETTING CORRESPONDING STAGES OF SAID FIRST SKIPPING SHIFT REGISTER, AND OPERABLE IN RESPONSE TO SUCCESSIVE INTERROGATION INPUTS TO PROVIDE OUTPUTS SUCCESSIVELY FROM SET STAGES THEREOF, A SECOND SKIPPING SHIFT REGISTER HAVING N STAGES CORRESPONDING TO THE N STAGES OF SAID THIRD REGISTER, OPERABLE IN RESPONSE TO THE SETTING OF STAGES OF SAID THIRD REGISTER FOR SETTING CORRESPONDING STAGES OF SAID SEC-
US3271744D 1962-12-31 Handling of multiple matches and fencing in memories Expired - Lifetime US3271744A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US24859562A 1962-12-31 1962-12-31

Publications (1)

Publication Number Publication Date
US3271744A true US3271744A (en) 1966-09-06

Family

ID=22939789

Family Applications (1)

Application Number Title Priority Date Filing Date
US3271744D Expired - Lifetime US3271744A (en) 1962-12-31 Handling of multiple matches and fencing in memories

Country Status (2)

Country Link
US (1) US3271744A (en)
GB (1) GB1016429A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3377624A (en) * 1966-01-07 1968-04-09 Ibm Memory protection system
US3400371A (en) * 1964-04-06 1968-09-03 Ibm Data processing system
US3402394A (en) * 1964-08-31 1968-09-17 Bunker Ramo Content addressable memory
US3451044A (en) * 1966-08-10 1969-06-17 Us Army Coding device
US3465297A (en) * 1966-09-30 1969-09-02 Control Data Corp Program protection arrangement
US3508205A (en) * 1967-01-17 1970-04-21 Computer Usage Co Inc Communications security system
US3593321A (en) * 1967-04-29 1971-07-13 Zuse Kg Matrix storage
US3742458A (en) * 1970-09-30 1973-06-26 Yokogawa Electric Works Ltd Memory protection system providing fixed, conditional and free memory portions corresponding to ranges of memory address numbers
US4523271A (en) * 1982-06-22 1985-06-11 Levien Raphael L Software protection method and apparatus

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3004109A (en) * 1958-10-29 1961-10-10 Lucas Pierre Marie High speed memory testing device
US3108256A (en) * 1958-12-30 1963-10-22 Ibm Logical clearing of memory devices
US3121217A (en) * 1960-08-12 1964-02-11 Ibm Memory and circuits therefor
US3191155A (en) * 1960-08-22 1965-06-22 Ibm Logical circuits and memory
US3191156A (en) * 1962-03-02 1965-06-22 Internat Bustiness Machines Co Random memory with ordered read out
US3195109A (en) * 1962-04-02 1965-07-13 Ibm Associative memory match indicator control
US3199082A (en) * 1959-11-27 1965-08-03 Ibm Memory system

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3004109A (en) * 1958-10-29 1961-10-10 Lucas Pierre Marie High speed memory testing device
US3108256A (en) * 1958-12-30 1963-10-22 Ibm Logical clearing of memory devices
US3108257A (en) * 1958-12-30 1963-10-22 Ibm Locking and unlocking of memory devices
US3199082A (en) * 1959-11-27 1965-08-03 Ibm Memory system
US3121217A (en) * 1960-08-12 1964-02-11 Ibm Memory and circuits therefor
US3191155A (en) * 1960-08-22 1965-06-22 Ibm Logical circuits and memory
US3191156A (en) * 1962-03-02 1965-06-22 Internat Bustiness Machines Co Random memory with ordered read out
US3195109A (en) * 1962-04-02 1965-07-13 Ibm Associative memory match indicator control

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3400371A (en) * 1964-04-06 1968-09-03 Ibm Data processing system
US3402394A (en) * 1964-08-31 1968-09-17 Bunker Ramo Content addressable memory
US3377624A (en) * 1966-01-07 1968-04-09 Ibm Memory protection system
US3451044A (en) * 1966-08-10 1969-06-17 Us Army Coding device
US3465297A (en) * 1966-09-30 1969-09-02 Control Data Corp Program protection arrangement
US3508205A (en) * 1967-01-17 1970-04-21 Computer Usage Co Inc Communications security system
US3593321A (en) * 1967-04-29 1971-07-13 Zuse Kg Matrix storage
US3742458A (en) * 1970-09-30 1973-06-26 Yokogawa Electric Works Ltd Memory protection system providing fixed, conditional and free memory portions corresponding to ranges of memory address numbers
US4523271A (en) * 1982-06-22 1985-06-11 Levien Raphael L Software protection method and apparatus

Also Published As

Publication number Publication date
GB1016429A (en) 1966-01-12

Similar Documents

Publication Publication Date Title
US3402398A (en) Plural content addressed memories with a common sensing circuit
US2800277A (en) Controlling arrangements for electronic digital computing machines
US3271744A (en) Handling of multiple matches and fencing in memories
US4170039A (en) Virtual address translation speed up technique
US3093814A (en) Tag memory
US3387276A (en) Off-line memory test
GB1316290A (en) Data stores
GB887111A (en) Input system for storage devices
US3699535A (en) Memory look-ahead connection arrangement for writing into an unoccupied address and prevention of reading out from an empty address
US3456243A (en) Associative data processing system
US3229253A (en) Matrix for reading out stored data
US3548386A (en) Associative memory
GB1179613A (en) Data Transfer System
US3266022A (en) Computer addressing system
US3774166A (en) Short-range data processing transfers
GB921246A (en) Information storage and search system
US3453421A (en) Readout system by sequential addressing of computer elements
GB1073800A (en) Improvements relating to digital data storage systems
JPH0774994B2 (en) OSC detection method for buffer storage controller
US3200378A (en) Data input/output device
GB1046357A (en) Word "selecting system" for data storage arrangement
US3594731A (en) Information processing system
RU2037215C1 (en) Storage device
SU1280380A2 (en) Device for determining the maximum paths in graphs
SU1133622A1 (en) Buffer storage