US20090085626A1 - Semiconductor integrated circuit and method for controlling semiconductor integrated circuit - Google Patents
Semiconductor integrated circuit and method for controlling semiconductor integrated circuit Download PDFInfo
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- US20090085626A1 US20090085626A1 US12/232,162 US23216208A US2009085626A1 US 20090085626 A1 US20090085626 A1 US 20090085626A1 US 23216208 A US23216208 A US 23216208A US 2009085626 A1 US2009085626 A1 US 2009085626A1
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- circuit
- master
- bus
- semiconductor integrated
- slave
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
Definitions
- the present invention relates to a semiconductor integrated circuit and a method for controlling a semiconductor integrated circuit.
- IP integrated property
- a master circuit is a circuit that instructs other circuits to execute given processing.
- Examples of a master circuit include a central processing unit (CPU), a digital signal processor (DSP) and other signal-processing circuits (such as an image processing circuit).
- a slave circuit is a circuit that executes a given processing in response to an instruction issued by others.
- An example of a slave circuit is a semiconductor storage device (hereinafter referred to as a memory when appropriate).
- a given slave circuit is previously assigned to a given master circuit. In this case, the slave circuit assigned to the master circuit is unavailable when the master circuit is in an inactive state (in a shutdown state or a sleep state).
- the number of unavailable slave circuits increases as the number of master circuits in an inactive state increases. This may result in a significant decrease in the use efficiency of system resources. In other words, a slave circuit assigned to a certain master circuit becomes unavailable when the certain master circuit goes into an inactive state. Accordingly, the use efficiency of system recourses decreases.
- the semiconductor integrated circuit according to the present invention includes a first slave circuit, a first master circuit, and a second master circuit.
- the first slave circuit previously assigned to the first master circuit is reassigned to the second master circuit in accordance with the operational status of the first master circuit.
- the first slave circuit By reassigning the first slave circuit previously assigned to the first master circuit to the second master circuit in accordance with the operational status of the first master circuit, the first slave circuit can be used not only by the first master circuit but also by the second master circuit. Accordingly, the use efficiency of system resources is improved.
- the method for controlling the semiconductor integrated circuit according to the present invention is a method for controlling a semiconductor integrated circuit having a first and a second master circuits and at least one slave circuit.
- the slave circuit previously assigned to the first master circuit is reassigned to the second circuit when the operational status of the first master circuit is detected to be in an inactive state.
- the slave circuit By reassigning the first slave circuit previously assigned to the first master circuit to the second master circuit when the operational status of the first master circuit is inactive, the slave circuit can be used not only by the first master circuit but also by the second master circuit. Accordingly, the use efficiency of system resources of the semiconductor integrated circuit is improved.
- FIG. 1 is a schematic block diagram of a semiconductor integrated circuit 50 .
- FIG. 2 is an explanatory diagram for describing the order of superiority of the circuit blocks.
- FIG. 3 is a schematic timing diagram for describing the operation of the semiconductor integrated circuit 50 .
- FIG. 4 is a schematic block diagram of a semiconductor integrated circuit 51 .
- FIG. 5 is a general block diagram of the semiconductor integrated circuit 52 .
- FIG. 6 is a general timing diagram illustrating the operation of a master module.
- FIG. 7 is a general timing diagram illustrating the operation of the semiconductor integrated circuit 52 .
- FIG. 1 shows a schematic block diagram of a semiconductor integrated circuit 50 .
- FIG. 2 shows an explanatory diagram for describing the order of superiority of the circuit blocks.
- FIG. 3 shows a schematic timing diagram for describing the operation of the semiconductor integrated circuit 50 .
- the semiconductor integrated circuit 50 includes master circuits 1 to 5 , a slave circuit 6 , a system controller 7 , a master status register 8 , a bus controller 9 and a bus 10 .
- the semiconductor integrated circuit 50 i-s a monolithic semiconductor device.
- the semiconductor integrated circuit 50 is made multi-functional based on SoC (System on Chip) technology.
- the master circuits 1 to 5 instruct other circuits to execute a predetermined processing.
- the master circuits may be, for example, a CPU (Central Processing Unit), a DSP (Digital Signal Processor) or other signal-processing circuits (such as an image processing circuit).
- a master ID (master identifier) is previously set for each of the master circuits 1 to 5 .
- the master circuits 1 to 5 are connected to the bus controller 9 via the bus 10 .
- the master circuits 4 and 5 are small-scale CPUs (miniature CPU) with a smaller circuit size than the master circuits 1 to 3 .
- the master circuit 4 has an interface circuit (input/output circuit) 11 that is connected to the bus 10 .
- the master circuit 5 also has an interface circuit (input/output circuit) 12 that is connected to the bus 10 .
- the master circuit 4 may be called CPU 1 and the master circuit 5 may be called CPU 2 in the following descriptions.
- the slave circuit 6 executes a predetermined processing in response to an instruction from outside.
- a slave circuit may be, for example, a memory.
- the slave circuit 6 determines which master circuit has made an access, based on its master ID.
- the slave circuit 6 is divided into three regions. Specifically, the slave circuit 6 includes an M1 region (slave circuit) 14 as a first region, an M2 region (slave circuit) 15 as a second region, and an M3 region (slave circuit) 16 as a third region.
- the M1 region 14 is assigned for the master circuit 1 . In other words, the M1 region 14 is a dedicated region for the master circuit 1 .
- the slave circuit 6 determines, based on a master ID, if an access to the M1 region 14 is made by the master circuit 1 .
- the slave circuit 6 permits an access to the M1 region 14 if a master ID transmitted via the bus 10 is the one previously set in the master circuit 1 .
- the slave circuit 6 denies an access to the M1 region 14 if the value of the master ID transmitted via the bus 10 is not the one set in the master circuit 1 , but the one set in a master circuit other than the master circuit 1 .
- the M2 region 15 is assigned to the master circuit 2
- the M3 region 16 is assigned to the master circuit 3 .
- the above-mentioned explanation on the access control to the M1 region 14 also applies to the M2 region 15 and to the M3 region 16 .
- the slave circuit 6 is divided to form the M1 region 14 , the M1 region 14 alone is assumed to work as a slave circuit. The same applies to the M2 region 15 and to the M3 region 16 .
- the system controller 7 is a master circuit that controls the whole system of the semiconductor integrated circuit 50 . That is to say, as shown in FIG. 2 , the system controller 7 is a circuit block of the most significant hierarchy that controls the master circuits 1 to 5 . In addition, as shown in FIG. 2 , the master circuits 1 to 5 form a circuit block of the intermediate hierarchy that controls the slave circuit 6 . The slave circuit 6 is a circuit block of the lowest hierarchy that operates in response to instructions from the master circuits 1 to 5 .
- the system controller 7 controls each of the master circuits 1 to 5 .
- the system controller 7 not only controls start and restart of the master circuit 1 and start and end of processing by the master circuit 1 , but also gives instructions to the other master circuits concurrently.
- the system controller 7 is connected to the interface circuit 11 of the CPU 1 .
- the system controller 7 is able to issue commands to the master circuit 4 via the interface circuit 11 and access the internal resources of the master circuit 4 .
- the system controller 7 is also able to carry out the similar operations via the interface circuit 12 .
- the system controller 7 checks the operation status of each of the master circuits 1 to 5 by referring to the master status register 8 .
- the system controller 7 changes the bus setting based on the operation status of each of the master circuits 1 to 5 , and reassigns a slave circuit previously assigned to a given master circuit to another master circuit.
- the system controller 7 reassigns the M2 region 15 previously assigned to the master circuit 2 to the CPU 1 when the master circuit 2 is in an inactive state.
- the M2 region 15 is utilized by the CPU 1 even when the master circuit 2 is in an inactive state, thereby improving the use efficiency of system resources of the semiconductor integrated circuit 50 as a whole.
- a value “0” is previously set for the system controller 7 as a master ID.
- the master data register 8 is a register having multiple bits. Each bit holds a status value that indicates the operation status of each master circuit. More specifically, a status value is set to a given bit in the master status register 8 , the status value indicating if the status of the master circuit 1 is in an active state (operational state) or in an inactive state (shutdown or sleep state). For example, the master circuit 1 is in an operational state when the status value is 1 (level H); the master circuit 1 is in either a shutdown or sleep state when the status value is 0 (level L).
- an active state (hereinafter referred to as an operational state as needed) is a state in which a master circuit can issue a command to the other circuits to execute a certain processing. Also note that an inactive state not only includes a sleep state but also a state in which the function of the master circuits is substantially stopped, such as a shutdown state.
- the bus controller 9 includes a control register 13 .
- the bus setting is changed by changing the hold value set in the control register 13 . This operation changes the master ID that is transmitted to the slave circuit, thereby enabling a signal transfer between a master circuit and a slave circuit, a combination not initially used.
- the bus controller 9 includes the control register 13 which is a register that includes multiple bits. A signal value is set in the control register 13 , the signal value indicating a method for controlling the signal transfer between a master circuit and a slave circuit.
- the bus controller 9 can change the bus setting in a way that an access request is processed in a slave circuit by regarding the access request, which is actually sent from the master circuit 4 , as an access request sent from the master circuit 2 .
- the system controller 7 changes the setting of the hold value set in the above-mentioned control register 13 .
- the bus setting is changed, and the access request is processed by regarding the access request, which is actually issued by the master circuit 4 , as an access request issued by the master circuit 2 .
- the bus 10 is a transmission line for signals and includes an address bus, data bus and a control line. Connected to the bus 10 are the master circuit 5 to 10 , the slave circuit 6 , the system controller 7 , the master status register 8 and the bus controller 9 .
- the master circuit 1 is in an operational state
- the master circuit 2 is in an operational state
- the master circuit 3 is in an operational state
- the CPU 1 is in a sleep state
- the CPU 2 is in a sleep state.
- an operational state is indicated as RUN
- a sleep state is indicated as SLEEP.
- the master circuit 2 goes into a sleep state.
- a status value in the master status register 8 , indicating the operation status of the master circuit 2
- a value indicating that the master circuit 2 is in an inactive state is set.
- the system controller 7 changes the bus setting and reassigns the M2 region 15 previously assigned to the master circuit 2 to the CPU 1 . More specifically, the system controller 7 changes the hold value in the control register 13 from a value indicating the master circuit 2 to a value indicating the CPU 1 . Thereby, an access request from the CPU 1 is processed at the slave circuit 6 as an access request from the master circuit 2 .
- 2 is transmitted to the slave circuit 6 as a master ID, and the M2 region 15 of the slave circuit 6 is made available to the CPU 1 .
- the system controller 7 causes the CPU 1 go into the operational state by starting the CPU 1 and instructing the CPU 1 to start processing.
- a status value in the master status register 8 , indicating the operation status of the CPU 1 , a value indicating that the CPU 1 is in an active state is set.
- the CPU 1 goes into a sleep state.
- a status value in the master status register 8 , indicating the operation status of the CPU 1
- a value indicating that CPU 1 is in an inactive state is set.
- the system controller 7 initiates the bus setting and reassigns the M2 region 15 previously assigned to the CPU 1 to the master circuit 2 . More specifically, the system controller 7 puts the hold value in the control register 13 back to a value indicating the master circuit 2 , which is the initial value.
- the master ID transmitted to the slave circuit 6 is changed from 2 to 4 . After this, an access request issued from the CPU 1 to the slave circuit 6 is recognized as an access request issued from the CPU 1 at the slave circuit 6 ; the access request will not be processed as one from the master circuit 2 .
- the state of the master circuit 2 never changes from a sleep state to an operational state between the time t 1 to the time t 2 . This is because the system controller 7 does not start the master circuit 2 at least while the M2 region 15 is assigned to the CPU 1 .
- the end of processing by the CPU 1 may be detected by a way that the system controller 7 checks the operation status of the CPU 1 via the interface circuit 11 .
- the end of processing by the CPU 1 may be detected by a way that the system controller 7 receives a process end notification from the CPU 1 via the bus 10 .
- the master circuit 3 goes into a sleep state.
- a status value in the master status register 8 , indicating the operation status of the master circuit 3
- a value indicating that the master circuit 3 is in an inactive state is set.
- the system controller 7 changes the bus setting and reassigns the M3 region 16 previously assigned to the master circuit 3 to the CPU 1 .
- the slave circuit 6 processes an access request from the CPU 1 as an access request from the master circuit 3 . That is to say, The M3 region 16 is made available to the CPU 1 .
- the system controller 7 puts the CPU 1 in an operational state after changing the bus setting.
- a status value in the master status register 8 , indicating the operation status of the CPU 1 , a value indicating that the CPU 1 is in an active state is set.
- the CPU 1 goes into a sleep state.
- a status value in the master status register 8 , indicating the operation status of the CPU 1
- a value indicating that the CPU 1 is in an inactive state is set.
- the system controller 7 Upon detecting the end of processing by the CPU 1 , the system controller 7 initiates the bus setting and reassigns the M3 region 16 previously assigned to the CPU 1 to the master circuit 3 . Thereafter, the M3 region 16 does not process an access from the CPU 1 as an access from the master circuit 3 .
- the master circuit 1 and the master circuit 2 are in a sleep state.
- a status value in the master status register 8 , indicating the operation status of the master circuit 1
- a value indicating that the master circuit 1 is in an inactive state is set.
- the system controller 7 initiates the bus setting and reassigns the M1 region 14 previously assigned to the master circuit 1 to the CPU 1 .
- the system controller 7 initiates the bus setting and reassigns the M2 region 15 previously assigned to the master circuit 2 to the CPU 2 .
- the slave circuit 6 processes an access request issued from the CPU 1 as an access request issued from the master circuit 1 .
- the slave circuit 6 processes an access request issued from the CPU 2 as an access request issued from the master circuit 2 . That is to say, the master ID transmitted to the slave circuit 6 is changed, and the M1 region 14 of the slave circuit 6 is made available to the CPU 1 . Also, the M2 region 15 of the slave circuit 6 is made available to the CPU 2 .
- the system controller 7 puts the CPU 1 and CPU 2 in an active state.
- a status value in the master status register 8 , indicating the operation status of the CPU 1 , a value indicating that the CPU 1 is in an active state is set.
- the CPU 1 and the CPU 2 go into a sleep state.
- a state value in the master status register 8 , indicating the operation status of the CPU 1
- a value indicating that the CPU 1 is in an inactive state is set.
- a state value in the master status register 8 , indicating the operation status of the CPU 2
- a value indicating that the CPU 2 is in an inactive state is set.
- the system controller 7 Upon detecting the end of processing by the CPU 1 and by the CPU 2 , the system controller 7 initiates the bus setting and reassigns the M1 region 14 previously assigned to the CPU 1 to the master circuit 1 and reassigns the M2 region 15 previously assigned to the CPU 2 to the master circuit 2 . Thereafter, the M1 region 14 does not process an access from the CPU 1 as an access from the master circuit 1 . Also, the M2 region 15 does not process an access from the CPU 2 as an access from the master circuit 2 .
- the system controller changes the bus setting. Based on this change of the bus setting, the master ID transmitted to the slave circuit is changed. Then, the slave circuit previously assigned to the master circuit that has gone into an inactive state is reassigned to another master circuit. Thereby, the slave circuit previously assigned to the master circuit that has gone into an inactive state is made available to the master circuit to which the slave circuit is now assigned. Accordingly, the use efficiency of system resources is improved.
- system controller initiates the bus setting and reassigns the slave circuit previously assigned to another circuit to the original master circuit. This prevents the interruption to the primary operation of the semiconductor integrated circuit.
- FIG. 4 shows a schematic block diagram of a semiconductor integrated circuit 51 .
- the semiconductor integrated circuit 51 according to this embodiment is different from the semiconductor integrated circuit 50 according to the first embodiment in that the semiconductor integrated circuit 51 includes an external terminal 21 and a system controller 20 .
- the system controller 20 is connected to the interface circuit 11 of the CPU 1 via the external terminal 21 .
- the system controller 20 is connected to the interface circuit 12 of the CPU 2 via the external terminal 21 .
- the system controller 20 is mounted outside a semiconductor chip on which the semiconductor integrated circuit 51 is mounted. Note that the system controller 20 may be monolithically formed with the semiconductor integrated circuit 51 .
- the above-mentioned change of bus setting and initiation of bus setting are executed by the CPU 1 and the CPU 2 that are controlled by the system controller 20 .
- the CPU 1 which is started by the system controller 20 , monitors the operation statuses of the other master circuits by referring to the master status register 8 . If the master circuit is in a sleep state, the CPU 1 changes the bus setting and assigns the M1 region 14 to the CPU 2 . This enables the CPU 2 , which is started by the system controller 20 , to use the M1 region 14 . Thereby, the slave circuit previously assigned to the master circuit in an inactive state is made available to the master circuit to which the slave circuit is now assigned. Accordingly, the use efficiency of system resources in the semiconductor integrated circuit 51 is improved.
- the CPU 1 Upon detecting that the processing by the CPU 2 is ended, the CPU 1 , which has been started by the system controller 20 , initiates the bus setting and reassigns the M1 region 14 previously assigned to the CPU 2 to the master circuit 1 . Thereafter, the slave circuit 6 does not process an access request issued from the CPU 2 as an access request issued from the master circuit 1 .
- change of bus setting and initiation of bus setting are executed by the CPU 1 that is controlled by the system controller 20 . That is to say, changing of bus setting and initiation of bus setting do not have to be executed by a system controller inside a semiconductor integrated circuit.
- FIG. 5 shows a schematic block diagram of a semiconductor integrated circuit 52 .
- FIG. 6 shows a schematic timing diagram illustrating the operation of a master module.
- FIG. 7 shows a schematic timing diagram illustrating the operation of the semiconductor integrated circuit 52 .
- the semiconductor integrated circuit 52 according to this embodiment is different from the semiconductor integrated circuit 50 according to the first embodiment in that the semiconductor integrated circuit 52 includes a master module 30 and a mode control register 35 . Note that the master circuits 4 and 5 are omitted from the drawings.
- the master module 30 is a circuit module including multiple master circuits.
- the master ID “ 6 ” is preset in the master module 30 .
- the master module 30 includes an IP circuit (functional circuit) 31 and a master circuit 32 .
- the IP circuit 31 is a master circuit that carries out predetermined functions.
- the master circuit 32 is a small-scale CPU that has smaller circuit size then the IP circuit 31 .
- the master circuit 32 is occasionally called a CPU 3 .
- the IP circuit 31 includes a hardware (for example, an ALU: Arithmetic and Logic Unit) 36 and a memory 37 .
- the CPU 3 is able to access the hardware 36 and the memory 37 , which are located inside the IP circuit 31 , via an interface in the IP circuit 31 .
- the CPU 3 includes an interface circuit (input/output circuit) 38 .
- the IP circuit 31 is connected to the bus 10 via a bus 34 , and the CPU 3 is connected to the bus 10 via the bus 34 .
- the CPU 3 is also connected to a slave circuit (the hardware 36 and the memory 37 ) inside the IP circuit 31 via a bus 33 .
- An interface circuit 38 of the CPU 3 is connected to the bus 10 .
- the CPU 3 is connected to the system controller 7 via the bus 10 .
- the mode control register 35 is connected to the system controller 7 via the bus 10 .
- the mode control register 35 holds a predetermined value corresponding to the setting condition of the bus 33 and the bus 34 .
- the bus 34 is controlled so as to enable the CPU 3 to access the bus 10 and not to enable the IP circuit 31 to access the bus 10 .
- the hold value in the mode control register 35 is 0 (level L)
- the bus 34 is controlled so as to enable the IP circuit 31 to access the bus 10 and not to enable the CPU 3 to access the bus 10 .
- the mode control register 35 in response to the change of the hold value in the mode control register 35 , the mode control register 35 exclusively (selectively) enables either the IP circuit 31 or the CPU 3 to access the bus 10 .
- the CPU 3 when in an operational state, the CPU 3 is accessible to the slave circuit inside the IP circuit 31 via the bus 33 that is in an active state.
- the mode control register 35 outputs to the buses 33 and 34 a mode signal corresponding to the hold value in the mode control register 35 .
- the operation of the master module 30 is described with reference to FIG. 6 .
- the IP circuit 31 is in an operational (RUN) state, the mode signal is level L, and the CPU 3 is in a sleep state.
- the IP circuit 31 goes into a sleep state.
- a state value in the master status register 8 , indicating the operation status of the master module 30 , a value indicating that the master module 30 is in an inactive state is set. It is assumed here that the operation statuses of the IP circuit 31 and the master circuit 32 can be determined by referring to the status value indicating the operation status of the master module 30 . Needless to say, a status value may be assigned to each of the IP circuit 31 and the master circuit 32 .
- the system controller 7 sets the hold value in the mode control register 35 to level H and the mode signal to level H. This enables the CPU 3 to access the slave circuit inside the IP circuit 31 via the bus 33 . Additionally, the CPU 3 is enabled to access the bus 10 via the bus 34 .
- the system controller 7 also starts the CPU 3 . Consequently, the master module 30 is set so as to operate independently. In other words, the CPU becomes accessible to the bus 10 . Meanwhile, the CPU does not have to be started via the interface circuit 38 .
- the CPU 3 performs a different function which is not implemented in the IP circuit 31 . This makes the master module 30 a multi-functional module.
- the CPU 3 can use via the bus 33 the slave circuit (the hardware 36 and the memory 37 ) inside the IP circuit 31 that is in a sleep state.
- the use efficiency of system resources in the semiconductor integrated circuit 52 improves as the CPU 3 utilizes the slave circuit inside the IP circuit 31 .
- the system controller 7 may directly access the IP circuit 31 .
- the CPU 3 goes into a sleep state.
- the system controller 7 Upon detecting the end of processing by the CPU 3 , the system controller 7 initiates the setting of the mode control register 35 . That is to say, the system controller 7 puts the hold value in the mode control register back to level L and sets the mode signal back to level L. Accordingly, the master module 30 is set so that the IP circuit 31 can operate independently.
- the IP circuit 31 goes into an operational state.
- a status value in the master status register 8 , indicating the operation status of the master module 30 , a value indicating that the master module 30 is in an active state is set.
- a different function is added to the master module 30 by causing the CPU 3 to function when the IP circuit 31 is not functioning.
- the use efficiency of system resources in the semiconductor integrated circuit 52 improves as the CPU 3 can utilize the slave circuit (the hardware 36 and the memory 37 ) inside the IP circuit 31 .
- the master circuit 1 When the time is t 0 , the master circuit 1 is in an operational (RUN) state, the master circuit 2 is in an operational (RUN) state, the master circuit 3 is in an operational (RUN) state, the IP circuit 31 is in an operational (RUN) state, and the mode signal is level L and the CUP 3 is in a sleep state.
- the master circuit 2 goes into a sleep state, and the master module 30 also goes into a sleep state.
- a state value in the master status register 8 , indicating the operation status of the master circuit 2 , a value indicating that the master circuit 2 is in an inactive state is set. The same applies to the master module 30 .
- the system controller 7 changes the bus setting and reassigns the M2 region 15 previously assigned to the master circuit 2 to the master module 30 .
- the slave circuit 6 processes an access request issued from the master module 30 as an access request issued from the master circuit 2 . That is to say, the M2 region 15 is made available to the master module 30 .
- the system controller 7 After changing the bus setting, the system controller 7 sets the hold value in the mode control register 35 to level H and the mode signal to level H. The system controller 7 also starts the CPU 3 . This allows CPU 3 to perform a different function which is not implemented in the IP circuit 31 while the IP circuit 31 is in a sleep state. That is, a multi-functional master module is achieved.
- the slave circuit (the hardware 36 and the memory 37 ) inside the IP circuit 31 that is in a sleep state is made available to the CPU 3 connected thereto via the bus 33 .
- This improves the use efficiency of system resources in the IP circuit 31 .
- the CPU 3 because the setting of the bus 10 has been changed, the CPU 3 is able to access the M2 region 15 via the bus 10 . That is to say, even when the operation status of the master module 30 is altered with the change in the hold value in the mode control register 35 , the M2 region 15 can be set in a state in which the M2 region 15 may be useable by the CPU 3 . This further improves the use efficiency of system resources in the semiconductor integrated circuit 52 .
- the CPU 3 goes into a sleep state.
- the system controller Upon detecting the end of processing by the CPU 3 , the system controller initiates the bus setting and reassigns the M2 region 15 previously assigned to the master module 30 to the master circuit 2 . This operation initiates the master ID that is transmitted to the slave circuit 6 . Thereafter, an access request issued from the master module 30 is not processed as an access request issued from the master circuit 2 .
- the system controller 7 also initiates the setting of the mode control register 35 . That is to say, the system controller 7 sets the hold value in the mode control register 35 back to level L and the mode signal back to level L. Consequently, the master module 30 is set so that the IP circuit 31 is able to operate independently.
- the IP circuit 31 goes into an operational state.
- a state value in the master status register 8 , indicating the operation status of the master module 30 , a value indicating that the master module 30 is in an active state is set.
- a multi-functional master module is achieved by using the CPU 3 .
- the CPU 3 can access the slave circuit (the hardware 36 and the memory 37 ) in the IP circuit 31 via the bus 33 that is in an active state. Accordingly, the use efficiency of system resources inside the master module 30 is improved.
- the bus setting is changed, and the M2 region 15 previously assigned to the master circuit 2 is reassigned to the master module 30 . Then the M2 region 15 is made available to the CPU 3 . By this, the slave circuit previously assigned to the master circuit that is in an inactive state becomes available to the CPU 3 as well. Accordingly, the use efficiency of system resources inside the semiconductor integrated circuit 52 is further improved.
Abstract
When a master circuit is in an inactive state, a slave circuit assigned to the master circuit is not used. Accordingly, the use efficiency of system recourses is decreased. To solve the above problem, a semiconductor integrated circuit reassigns a M2 region of a slave circuit, previously assigned to a first master circuit, to a second master circuit. That is to say, the M2 region of the slave circuit previously assigned to the first master circuit is reassigned to the second master circuit based on the operational status of the first master circuit. This improves the use efficiency of system resources of the semiconductor integrated circuit.
Description
- 1. Field of the Invention
- The present invention relates to a semiconductor integrated circuit and a method for controlling a semiconductor integrated circuit.
- 2. Background Art
- Semiconductor integrated circuits have been remarkably improved to be more multifunctional and highly integrated in recent years. In such a semiconductor integrated circuit, multiple functional circuits (intellectual property (IP) circuits) implementing different functions are monolithically integrated.
- Multiple master circuits and multiple slave circuits are generally mounted in such a multifunctional semiconductor integrated circuit. A master circuit is a circuit that instructs other circuits to execute given processing. Examples of a master circuit include a central processing unit (CPU), a digital signal processor (DSP) and other signal-processing circuits (such as an image processing circuit). On the other hand, a slave circuit is a circuit that executes a given processing in response to an instruction issued by others. An example of a slave circuit is a semiconductor storage device (hereinafter referred to as a memory when appropriate).
- Systems each including master circuits and slave circuits are disclosed in Japanese Patent Application Publication Nos. Hei 6-274459, 2003-296294, 2001-166960, and Hei 2-85953. In a technique disclosed in Japanese Patent Application Publication No. Hei 6-274459, the connection relation between processors is allowed to be changed, so that the versatility of LSI is improved. In a technique disclosed in Japanese Patent Application Publication No. 2003-296294, an input/output terminal is assigned to one of multiple function modules on the basis of profile data that indicates whether each of the function modules is used or not. In a technique disclosed in Japanese Patent Application Publication No. 2001-166960, an individual region for each processor is assigned to a shared memory. Japanese Patent Application Publication No. Hei 2-85953 discloses a technique for performing a fault analysis on a master module.
- In some semiconductor integrated circuits each including master circuits and slave circuits, a given slave circuit is previously assigned to a given master circuit. In this case, the slave circuit assigned to the master circuit is unavailable when the master circuit is in an inactive state (in a shutdown state or a sleep state).
- In a semiconductor integrated circuit including multiple master circuits and multiple slave circuits, the number of unavailable slave circuits increases as the number of master circuits in an inactive state increases. This may result in a significant decrease in the use efficiency of system resources. In other words, a slave circuit assigned to a certain master circuit becomes unavailable when the certain master circuit goes into an inactive state. Accordingly, the use efficiency of system recourses decreases.
- The semiconductor integrated circuit according to the present invention includes a first slave circuit, a first master circuit, and a second master circuit. The first slave circuit previously assigned to the first master circuit is reassigned to the second master circuit in accordance with the operational status of the first master circuit.
- By reassigning the first slave circuit previously assigned to the first master circuit to the second master circuit in accordance with the operational status of the first master circuit, the first slave circuit can be used not only by the first master circuit but also by the second master circuit. Accordingly, the use efficiency of system resources is improved.
- The method for controlling the semiconductor integrated circuit according to the present invention is a method for controlling a semiconductor integrated circuit having a first and a second master circuits and at least one slave circuit. In this method, the slave circuit previously assigned to the first master circuit is reassigned to the second circuit when the operational status of the first master circuit is detected to be in an inactive state.
- By reassigning the first slave circuit previously assigned to the first master circuit to the second master circuit when the operational status of the first master circuit is inactive, the slave circuit can be used not only by the first master circuit but also by the second master circuit. Accordingly, the use efficiency of system resources of the semiconductor integrated circuit is improved.
- According to the present invention, it is possible to improve the use efficiency of system resources in a semiconductor integrated circuit with master circuits and slave circuits.
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FIG. 1 is a schematic block diagram of a semiconductor integratedcircuit 50. -
FIG. 2 is an explanatory diagram for describing the order of superiority of the circuit blocks. -
FIG. 3 is a schematic timing diagram for describing the operation of the semiconductor integratedcircuit 50. -
FIG. 4 is a schematic block diagram of a semiconductor integratedcircuit 51. -
FIG. 5 is a general block diagram of the semiconductor integratedcircuit 52. -
FIG. 6 is a general timing diagram illustrating the operation of a master module. -
FIG. 7 is a general timing diagram illustrating the operation of the semiconductor integratedcircuit 52. - Embodiments of the present invention are described below with reference to the accompanying drawings. Each embodiment is simplified for convenience of the description. The technical scope of the present invention should not be construed narrowly based on the simplified descriptions in the drawings. The same reference numerals are denoted to the same components, and descriptions thereof are not repeated.
- A first embodiment is described hereinafter in connection with
FIGS. 1 through 3 .FIG. 1 shows a schematic block diagram of a semiconductor integratedcircuit 50.FIG. 2 shows an explanatory diagram for describing the order of superiority of the circuit blocks.FIG. 3 shows a schematic timing diagram for describing the operation of the semiconductor integratedcircuit 50. - As shown in
FIG. 1 , the semiconductor integratedcircuit 50 includesmaster circuits 1 to 5, aslave circuit 6, asystem controller 7, amaster status register 8, abus controller 9 and abus 10. The semiconductor integratedcircuit 50 i-s a monolithic semiconductor device. The semiconductor integratedcircuit 50 is made multi-functional based on SoC (System on Chip) technology. - The
master circuits 1 to 5 instruct other circuits to execute a predetermined processing. The master circuits may be, for example, a CPU (Central Processing Unit), a DSP (Digital Signal Processor) or other signal-processing circuits (such as an image processing circuit). - A master ID (master identifier) is previously set for each of the
master circuits 1 to 5. A master ID=1 is set for themaster circuit 1, a master ID=2 for themaster circuit 2, a master ID=3 for themaster circuit 3, a master ID=4 for themaster circuit 4, and a master ID=5 for themaster circuit 5. Themaster circuits 1 to 5 are connected to thebus controller 9 via thebus 10. - The
master circuits master circuits 1 to 3. Themaster circuit 4 has an interface circuit (input/output circuit) 11 that is connected to thebus 10. Themaster circuit 5 also has an interface circuit (input/output circuit) 12 that is connected to thebus 10. Themaster circuit 4 may be calledCPU 1 and themaster circuit 5 may be calledCPU 2 in the following descriptions. - The
slave circuit 6 executes a predetermined processing in response to an instruction from outside. A slave circuit may be, for example, a memory. Theslave circuit 6 determines which master circuit has made an access, based on its master ID. Here, theslave circuit 6 is divided into three regions. Specifically, theslave circuit 6 includes an M1 region (slave circuit) 14 as a first region, an M2 region (slave circuit) 15 as a second region, and an M3 region (slave circuit) 16 as a third region. TheM1 region 14 is assigned for themaster circuit 1. In other words, theM1 region 14 is a dedicated region for themaster circuit 1. Theslave circuit 6 determines, based on a master ID, if an access to theM1 region 14 is made by themaster circuit 1. That is to say, theslave circuit 6 permits an access to theM1 region 14 if a master ID transmitted via thebus 10 is the one previously set in themaster circuit 1. On the other hand, theslave circuit 6 denies an access to theM1 region 14 if the value of the master ID transmitted via thebus 10 is not the one set in themaster circuit 1, but the one set in a master circuit other than themaster circuit 1. Similarly, theM2 region 15 is assigned to themaster circuit 2, and theM3 region 16 is assigned to themaster circuit 3. The above-mentioned explanation on the access control to theM1 region 14 also applies to theM2 region 15 and to theM3 region 16. Although theslave circuit 6 is divided to form theM1 region 14, theM1 region 14 alone is assumed to work as a slave circuit. The same applies to theM2 region 15 and to theM3 region 16. - The
system controller 7 is a master circuit that controls the whole system of the semiconductor integratedcircuit 50. That is to say, as shown inFIG. 2 , thesystem controller 7 is a circuit block of the most significant hierarchy that controls themaster circuits 1 to 5. In addition, as shown inFIG. 2 , themaster circuits 1 to 5 form a circuit block of the intermediate hierarchy that controls theslave circuit 6. Theslave circuit 6 is a circuit block of the lowest hierarchy that operates in response to instructions from themaster circuits 1 to 5. - The
system controller 7 controls each of themaster circuits 1 to 5. For example, thesystem controller 7 not only controls start and restart of themaster circuit 1 and start and end of processing by themaster circuit 1, but also gives instructions to the other master circuits concurrently. - The
system controller 7 is connected to theinterface circuit 11 of theCPU 1. Thesystem controller 7 is able to issue commands to themaster circuit 4 via theinterface circuit 11 and access the internal resources of themaster circuit 4. As to theCPU 2, thesystem controller 7 is also able to carry out the similar operations via theinterface circuit 12. - The
system controller 7 checks the operation status of each of themaster circuits 1 to 5 by referring to themaster status register 8. Thesystem controller 7 changes the bus setting based on the operation status of each of themaster circuits 1 to 5, and reassigns a slave circuit previously assigned to a given master circuit to another master circuit. - For example, the
system controller 7 reassigns theM2 region 15 previously assigned to themaster circuit 2 to theCPU 1 when themaster circuit 2 is in an inactive state. TheM2 region 15 is utilized by theCPU 1 even when themaster circuit 2 is in an inactive state, thereby improving the use efficiency of system resources of the semiconductor integratedcircuit 50 as a whole. - As shown in
FIG. 1 , a value “0” is previously set for thesystem controller 7 as a master ID. The master ID=0 set for thesystem controller 7 is transmitted to thebus controller 9 via thebus 10. - The master data register 8 is a register having multiple bits. Each bit holds a status value that indicates the operation status of each master circuit. More specifically, a status value is set to a given bit in the
master status register 8, the status value indicating if the status of themaster circuit 1 is in an active state (operational state) or in an inactive state (shutdown or sleep state). For example, themaster circuit 1 is in an operational state when the status value is 1 (level H); themaster circuit 1 is in either a shutdown or sleep state when the status value is 0 (level L). - Note that an active state (hereinafter referred to as an operational state as needed) is a state in which a master circuit can issue a command to the other circuits to execute a certain processing. Also note that an inactive state not only includes a sleep state but also a state in which the function of the master circuits is substantially stopped, such as a shutdown state.
- The
bus controller 9 according to the present embodiment includes acontrol register 13. The bus setting is changed by changing the hold value set in thecontrol register 13. This operation changes the master ID that is transmitted to the slave circuit, thereby enabling a signal transfer between a master circuit and a slave circuit, a combination not initially used. Thebus controller 9 includes thecontrol register 13 which is a register that includes multiple bits. A signal value is set in thecontrol register 13, the signal value indicating a method for controlling the signal transfer between a master circuit and a slave circuit. For example, when a predetermined value is set in thecontrol register 13, thebus controller 9 can change the bus setting in a way that an access request is processed in a slave circuit by regarding the access request, which is actually sent from themaster circuit 4, as an access request sent from themaster circuit 2. - The
system controller 7 changes the setting of the hold value set in the above-mentionedcontrol register 13. This changes the bus setting so that an access request is processed by regarding the access request, which is actually issued from a master circuit, as an access request issued from another master circuit. For example, as is similar to the above specific example, when thesystem controller 7 sets a predetermined hold value in thecontrol register 13, the bus setting is changed, and the access request is processed by regarding the access request, which is actually issued by themaster circuit 4, as an access request issued by themaster circuit 2. - The
bus 10 is a transmission line for signals and includes an address bus, data bus and a control line. Connected to thebus 10 are themaster circuit 5 to 10, theslave circuit 6, thesystem controller 7, themaster status register 8 and thebus controller 9. - The operation of the semiconductor integrated
circuit 50 is described below with reference toFIG. 3 . - At time t0, the
master circuit 1 is in an operational state, themaster circuit 2 is in an operational state, themaster circuit 3 is in an operational state, theCPU 1 is in a sleep state, and theCPU 2 is in a sleep state. InFIG. 3 , an operational state is indicated as RUN, and a sleep state is indicated as SLEEP. - At time t1, the
master circuit 2 goes into a sleep state. At this time, as a status value, in themaster status register 8, indicating the operation status of themaster circuit 2, a value indicating that themaster circuit 2 is in an inactive state is set. In response to this change of the status value, thesystem controller 7 changes the bus setting and reassigns theM2 region 15 previously assigned to themaster circuit 2 to theCPU 1. More specifically, thesystem controller 7 changes the hold value in the control register 13 from a value indicating themaster circuit 2 to a value indicating theCPU 1. Thereby, an access request from theCPU 1 is processed at theslave circuit 6 as an access request from themaster circuit 2. That is to say, 2 is transmitted to theslave circuit 6 as a master ID, and theM2 region 15 of theslave circuit 6 is made available to theCPU 1. After changing the bus setting, thesystem controller 7 causes theCPU 1 go into the operational state by starting theCPU 1 and instructing theCPU 1 to start processing. At this time, as a status value, in themaster status register 8, indicating the operation status of theCPU 1, a value indicating that theCPU 1 is in an active state is set. - At time t2, the
CPU 1 goes into a sleep state. At this time, as a status value, in themaster status register 8, indicating the operation status of theCPU 1, a value indicating thatCPU 1 is in an inactive state is set. In response to this change of the status value, when detecting the end of processing performed by theCPU 1, thesystem controller 7 initiates the bus setting and reassigns theM2 region 15 previously assigned to theCPU 1 to themaster circuit 2. More specifically, thesystem controller 7 puts the hold value in thecontrol register 13 back to a value indicating themaster circuit 2, which is the initial value. By this, the master ID transmitted to theslave circuit 6 is changed from 2 to 4. After this, an access request issued from theCPU 1 to theslave circuit 6 is recognized as an access request issued from theCPU 1 at theslave circuit 6; the access request will not be processed as one from themaster circuit 2. - Incidentally, the state of the
master circuit 2 never changes from a sleep state to an operational state between the time t1 to the time t2. This is because thesystem controller 7 does not start themaster circuit 2 at least while theM2 region 15 is assigned to theCPU 1. - In addition, there is another method for confirming the end of processing at the
CPU 1 in addition to the method in which thesystem controller 7 checks the status value in themaster status register 8. That is, the end of processing by theCPU 1 may be detected by a way that thesystem controller 7 checks the operation status of theCPU 1 via theinterface circuit 11. Alternatively, the end of processing by theCPU 1 may be detected by a way that thesystem controller 7 receives a process end notification from theCPU 1 via thebus 10. - At time t3, the
master circuit 3 goes into a sleep state. At this time, as a status value, in themaster status register 8, indicating the operation status of themaster circuit 3, a value indicating that themaster circuit 3 is in an inactive state is set. In response to the change of the status value, thesystem controller 7 changes the bus setting and reassigns theM3 region 16 previously assigned to themaster circuit 3 to theCPU 1. This changes the master ID transmitted to theslave circuit 6 from 4 to 3. Thereby, theslave circuit 6 processes an access request from theCPU 1 as an access request from themaster circuit 3. That is to say, TheM3 region 16 is made available to theCPU 1. Thesystem controller 7 puts theCPU 1 in an operational state after changing the bus setting. As a status value, in themaster status register 8, indicating the operation status of theCPU 1, a value indicating that theCPU 1 is in an active state is set. - At time t4, the
CPU 1 goes into a sleep state. At this time, as a status value, in themaster status register 8, indicating the operation status of theCPU 1, a value indicating that theCPU 1 is in an inactive state is set. Upon detecting the end of processing by theCPU 1, thesystem controller 7 initiates the bus setting and reassigns theM3 region 16 previously assigned to theCPU 1 to themaster circuit 3. Thereafter, theM3 region 16 does not process an access from theCPU 1 as an access from themaster circuit 3. - At time t5, the
master circuit 1 and themaster circuit 2 are in a sleep state. At this time, as a status value, in themaster status register 8, indicating the operation status of themaster circuit 1, a value indicating that themaster circuit 1 is in an inactive state is set. The same applies to themaster circuit 2. In response to these changes of the status values, thesystem controller 7 initiates the bus setting and reassigns theM1 region 14 previously assigned to themaster circuit 1 to theCPU 1. In the meantime, thesystem controller 7 initiates the bus setting and reassigns theM2 region 15 previously assigned to themaster circuit 2 to theCPU 2. - Thereby, the
slave circuit 6 processes an access request issued from theCPU 1 as an access request issued from themaster circuit 1. Likewise, theslave circuit 6 processes an access request issued from theCPU 2 as an access request issued from themaster circuit 2. That is to say, the master ID transmitted to theslave circuit 6 is changed, and theM1 region 14 of theslave circuit 6 is made available to theCPU 1. Also, theM2 region 15 of theslave circuit 6 is made available to theCPU 2. After changing the bus setting, thesystem controller 7 puts theCPU 1 andCPU 2 in an active state. As a status value, in themaster status register 8, indicating the operation status of theCPU 1, a value indicating that theCPU 1 is in an active state is set. The same applies to theCPU 2 At time t6, theCPU 1 and theCPU 2 go into a sleep state. At this time, as a state value, in themaster status register 8, indicating the operation status of theCPU 1, a value indicating that theCPU 1 is in an inactive state is set. Also, as a state value, in themaster status register 8, indicating the operation status of theCPU 2, a value indicating that theCPU 2 is in an inactive state is set. - Upon detecting the end of processing by the
CPU 1 and by theCPU 2, thesystem controller 7 initiates the bus setting and reassigns theM1 region 14 previously assigned to theCPU 1 to themaster circuit 1 and reassigns theM2 region 15 previously assigned to theCPU 2 to themaster circuit 2. Thereafter, theM1 region 14 does not process an access from theCPU 1 as an access from themaster circuit 1. Also, theM2 region 15 does not process an access from theCPU 2 as an access from themaster circuit 2. - In this embodiment, as it is clear from the above descriptions, when a given master circuit goes into an inactive state, the system controller changes the bus setting. Based on this change of the bus setting, the master ID transmitted to the slave circuit is changed. Then, the slave circuit previously assigned to the master circuit that has gone into an inactive state is reassigned to another master circuit. Thereby, the slave circuit previously assigned to the master circuit that has gone into an inactive state is made available to the master circuit to which the slave circuit is now assigned. Accordingly, the use efficiency of system resources is improved.
- In addition, the system controller initiates the bus setting and reassigns the slave circuit previously assigned to another circuit to the original master circuit. This prevents the interruption to the primary operation of the semiconductor integrated circuit.
- A second embodiment is described hereinafter with reference to
FIG. 4 .FIG. 4 shows a schematic block diagram of a semiconductor integratedcircuit 51. - As shown in
FIG. 4 , the semiconductor integratedcircuit 51 according to this embodiment is different from the semiconductor integratedcircuit 50 according to the first embodiment in that the semiconductor integratedcircuit 51 includes an external terminal 21 and asystem controller 20. Thesystem controller 20 is connected to theinterface circuit 11 of theCPU 1 via the external terminal 21. Thesystem controller 20 is connected to theinterface circuit 12 of theCPU 2 via the external terminal 21. Here, thesystem controller 20 is mounted outside a semiconductor chip on which the semiconductor integratedcircuit 51 is mounted. Note that thesystem controller 20 may be monolithically formed with the semiconductor integratedcircuit 51. - In this embodiment, the above-mentioned change of bus setting and initiation of bus setting are executed by the
CPU 1 and theCPU 2 that are controlled by thesystem controller 20. - More specifically, the
CPU 1, which is started by thesystem controller 20, monitors the operation statuses of the other master circuits by referring to themaster status register 8. If the master circuit is in a sleep state, theCPU 1 changes the bus setting and assigns theM1 region 14 to theCPU 2. This enables theCPU 2, which is started by thesystem controller 20, to use theM1 region 14. Thereby, the slave circuit previously assigned to the master circuit in an inactive state is made available to the master circuit to which the slave circuit is now assigned. Accordingly, the use efficiency of system resources in the semiconductor integratedcircuit 51 is improved. - Upon detecting that the processing by the
CPU 2 is ended, theCPU 1, which has been started by thesystem controller 20, initiates the bus setting and reassigns theM1 region 14 previously assigned to theCPU 2 to themaster circuit 1. Thereafter, theslave circuit 6 does not process an access request issued from theCPU 2 as an access request issued from themaster circuit 1. - In this embodiment, as it is clear from the above descriptions, change of bus setting and initiation of bus setting are executed by the
CPU 1 that is controlled by thesystem controller 20. That is to say, changing of bus setting and initiation of bus setting do not have to be executed by a system controller inside a semiconductor integrated circuit. In addition, it is possible to assign theM1 region 14 not to theCPU 2 but to theCPU 1 that is controlled by thesystem controller 20 by adopting an appropriate system configuration. In this case,CPU 1 should be able to access themaster register 8 and control register 13 regardless of change of the bus setting. - A third embodiment is described below with reference to
FIGS. 5 through 7 .FIG. 5 shows a schematic block diagram of a semiconductor integratedcircuit 52.FIG. 6 shows a schematic timing diagram illustrating the operation of a master module.FIG. 7 shows a schematic timing diagram illustrating the operation of the semiconductor integratedcircuit 52. - The semiconductor integrated
circuit 52 according to this embodiment is different from the semiconductor integratedcircuit 50 according to the first embodiment in that the semiconductor integratedcircuit 52 includes amaster module 30 and amode control register 35. Note that themaster circuits - The
master module 30 is a circuit module including multiple master circuits. The master ID “6” is preset in themaster module 30. - The
master module 30 includes an IP circuit (functional circuit) 31 and amaster circuit 32. TheIP circuit 31 is a master circuit that carries out predetermined functions. Themaster circuit 32 is a small-scale CPU that has smaller circuit size then theIP circuit 31. Hereinafter, themaster circuit 32 is occasionally called aCPU 3. - Included inside the
IP circuit 31 are a hardware (for example, an ALU: Arithmetic and Logic Unit) 36 and amemory 37. TheCPU 3 is able to access thehardware 36 and thememory 37, which are located inside theIP circuit 31, via an interface in theIP circuit 31. TheCPU 3 includes an interface circuit (input/output circuit) 38. - The
IP circuit 31 is connected to thebus 10 via abus 34, and theCPU 3 is connected to thebus 10 via thebus 34. TheCPU 3 is also connected to a slave circuit (thehardware 36 and the memory 37) inside theIP circuit 31 via abus 33. Aninterface circuit 38 of theCPU 3 is connected to thebus 10. TheCPU 3 is connected to thesystem controller 7 via thebus 10. - The mode control register 35 is connected to the
system controller 7 via thebus 10. The mode control register 35 holds a predetermined value corresponding to the setting condition of thebus 33 and thebus 34. For example, when the hold value in the mode control register 35 is 1 (level H), thebus 34 is controlled so as to enable theCPU 3 to access thebus 10 and not to enable theIP circuit 31 to access thebus 10. On the other hand, when the hold value in the mode control register 35 is 0 (level L), thebus 34 is controlled so as to enable theIP circuit 31 to access thebus 10 and not to enable theCPU 3 to access thebus 10. That is to say, in response to the change of the hold value in themode control register 35, the mode control register 35 exclusively (selectively) enables either theIP circuit 31 or theCPU 3 to access thebus 10. In addition, when in an operational state, theCPU 3 is accessible to the slave circuit inside theIP circuit 31 via thebus 33 that is in an active state. Moreover, the mode control register 35 outputs to thebuses 33 and 34 a mode signal corresponding to the hold value in themode control register 35. - Here, the operation of the
master module 30 is described with reference toFIG. 6 . - At time t0, the
IP circuit 31 is in an operational (RUN) state, the mode signal is level L, and theCPU 3 is in a sleep state. - At time t1, the
IP circuit 31 goes into a sleep state. At this time, as a state value, in themaster status register 8, indicating the operation status of themaster module 30, a value indicating that themaster module 30 is in an inactive state is set. It is assumed here that the operation statuses of theIP circuit 31 and themaster circuit 32 can be determined by referring to the status value indicating the operation status of themaster module 30. Needless to say, a status value may be assigned to each of theIP circuit 31 and themaster circuit 32. - In response to the change of the status value, the
system controller 7 sets the hold value in the mode control register 35 to level H and the mode signal to level H. This enables theCPU 3 to access the slave circuit inside theIP circuit 31 via thebus 33. Additionally, theCPU 3 is enabled to access thebus 10 via thebus 34. - The
system controller 7 also starts theCPU 3. Consequently, themaster module 30 is set so as to operate independently. In other words, the CPU becomes accessible to thebus 10. Meanwhile, the CPU does not have to be started via theinterface circuit 38. - The
CPU 3 performs a different function which is not implemented in theIP circuit 31. This makes the master module 30 a multi-functional module. TheCPU 3 can use via thebus 33 the slave circuit (thehardware 36 and the memory 37) inside theIP circuit 31 that is in a sleep state. The use efficiency of system resources in the semiconductor integratedcircuit 52 improves as theCPU 3 utilizes the slave circuit inside theIP circuit 31. - In addition, to determine the operation status, instead of referring to the status value, of the
master status register 8, indicating the operation status of themaster module 3, thesystem controller 7 may directly access theIP circuit 31. - At time t2, the
CPU 3 goes into a sleep state. Upon detecting the end of processing by theCPU 3, thesystem controller 7 initiates the setting of themode control register 35. That is to say, thesystem controller 7 puts the hold value in the mode control register back to level L and sets the mode signal back to level L. Accordingly, themaster module 30 is set so that theIP circuit 31 can operate independently. - At time t3, the
IP circuit 31 goes into an operational state. As a status value, in themaster status register 8, indicating the operation status of themaster module 30, a value indicating that themaster module 30 is in an active state is set. - As mentioned above, in this embodiment, a different function is added to the
master module 30 by causing theCPU 3 to function when theIP circuit 31 is not functioning. The use efficiency of system resources in the semiconductor integratedcircuit 52 improves as theCPU 3 can utilize the slave circuit (thehardware 36 and the memory 37) inside theIP circuit 31. - Here, the operation of the semiconductor integrated
circuit 52 is described with reference toFIG. 7 . - When the time is t0, the
master circuit 1 is in an operational (RUN) state, themaster circuit 2 is in an operational (RUN) state, themaster circuit 3 is in an operational (RUN) state, theIP circuit 31 is in an operational (RUN) state, and the mode signal is level L and theCUP 3 is in a sleep state. - At time t1, the
master circuit 2 goes into a sleep state, and themaster module 30 also goes into a sleep state. At this time, as a state value, in themaster status register 8, indicating the operation status of themaster circuit 2, a value indicating that themaster circuit 2 is in an inactive state is set. The same applies to themaster module 30. - The
system controller 7 changes the bus setting and reassigns theM2 region 15 previously assigned to themaster circuit 2 to themaster module 30. This changes the master ID that is transmitted to theslave circuit 6. Specifically, theslave circuit 6 processes an access request issued from themaster module 30 as an access request issued from themaster circuit 2. That is to say, theM2 region 15 is made available to themaster module 30. - After changing the bus setting, the
system controller 7 sets the hold value in the mode control register 35 to level H and the mode signal to level H. Thesystem controller 7 also starts theCPU 3. This allowsCPU 3 to perform a different function which is not implemented in theIP circuit 31 while theIP circuit 31 is in a sleep state. That is, a multi-functional master module is achieved. - Meanwhile, the slave circuit (the
hardware 36 and the memory 37) inside theIP circuit 31 that is in a sleep state is made available to theCPU 3 connected thereto via thebus 33. This improves the use efficiency of system resources in theIP circuit 31. In addition, as is similar to the first embodiment, because the setting of thebus 10 has been changed, theCPU 3 is able to access theM2 region 15 via thebus 10. That is to say, even when the operation status of themaster module 30 is altered with the change in the hold value in themode control register 35, theM2 region 15 can be set in a state in which theM2 region 15 may be useable by theCPU 3. This further improves the use efficiency of system resources in the semiconductor integratedcircuit 52. - At time t2, the
CPU 3 goes into a sleep state. Upon detecting the end of processing by theCPU 3, the system controller initiates the bus setting and reassigns theM2 region 15 previously assigned to themaster module 30 to themaster circuit 2. This operation initiates the master ID that is transmitted to theslave circuit 6. Thereafter, an access request issued from themaster module 30 is not processed as an access request issued from themaster circuit 2. - The
system controller 7 also initiates the setting of themode control register 35. That is to say, thesystem controller 7 sets the hold value in the mode control register 35 back to level L and the mode signal back to level L. Consequently, themaster module 30 is set so that theIP circuit 31 is able to operate independently. - At time t3, the
IP circuit 31 goes into an operational state. At this time, as a state value, in themaster status register 8, indicating the operation status of themaster module 30, a value indicating that themaster module 30 is in an active state is set. - According to this embodiment, a multi-functional master module is achieved by using the
CPU 3. In addition, when theIP 31 is in an inactive state, theCPU 3 can access the slave circuit (thehardware 36 and the memory 37) in theIP circuit 31 via thebus 33 that is in an active state. Accordingly, the use efficiency of system resources inside themaster module 30 is improved. - Like the first and second embodiments, in the semiconductor integrated
circuit 52 in this embodiment, when themaster circuit 2 goes into an inactive state, the bus setting is changed, and theM2 region 15 previously assigned to themaster circuit 2 is reassigned to themaster module 30. Then theM2 region 15 is made available to theCPU 3. By this, the slave circuit previously assigned to the master circuit that is in an inactive state becomes available to theCPU 3 as well. Accordingly, the use efficiency of system resources inside the semiconductor integratedcircuit 52 is further improved. - It is apparent that the present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope and spirit of the invention.
Claims (20)
1. A semiconductor integrated circuit, comprising:
a first master circuit;
a second master circuit; and
a first slave circuit being assigned to said first master circuit, wherein
said first slave circuit is reassigned to said second master circuit based on an operational status of said first master circuit.
2. The semiconductor integrated circuit according to claim 1 , further comprising
a first bus coupled to at least said first master circuit, said first slave circuit and said second master circuit, wherein
said first slave circuit is reassigned to said second master circuit by changing settings of said first bus.
3. The semiconductor integrated circuit according to claim 2 , wherein
a master identifier transmitted to said first slave circuit via said first bus after changing said settings of said first bus is equal to a master identifier pre-set in said first master circuit.
4. The semiconductor integrated circuit according to claim 2 , further comprising
a system controller that changes said settings of said first bus.
5. The semiconductor integrated circuit according to claim 4 , further comprising
a bus controller coupled to said first bus, wherein
said system controller changes settings of said first bus by changing a hold value stored in a register included in said bus controller.
6. The semiconductor integrated circuit according to claim 4 , further comprising
a master status register that holds a state value indicating the operation status of at least said first master circuit, wherein
said system controller changes settings of said first bus when said state value indicates that said first master circuit is in an inactive state.
7. The semiconductor integrated circuit according to claim 4 , wherein
said system controller controls stop-start of at least said first master circuit and said second master circuit.
8. The semiconductor integrated circuit according to claim 6 , wherein
said system controller starts said second master circuit when said state value in said master status register indicates that said first master circuit is in an inactive state.
9. The semiconductor integrated circuit according to claim 4 , wherein
said system controller is coupled to an interface circuit of said second master circuit via said first bus.
10. The semiconductor integrated circuit according to claim 4 , further comprising
a third master circuit having an interface circuit to which the system controller is coupled, wherein
said system controller changes said settings of said first bus by utilizing said third master circuit.
11. The semiconductor integrated circuit according to claim 10 , wherein
the system controller is coupled to said interface circuit of said third master circuit via an external terminal.
12. The semiconductor integrated circuit according to claim 1 , further comprising
a second bus coupled to said first master circuit and said second master circuit.
13. The semiconductor integrated circuit according to claim 12 , further comprising
a third bus coupled to said second master circuit and said first slave circuit.
14. The semiconductor integrated circuit according to claim 12 , further comprising
a system controller that controls said settings of at least said second bus.
15. The semiconductor integrated circuit according to claim 14 , wherein
said system controller changes settings of said second bus based on a change of a hold value in a mode control register coupled to said second bus.
16. The semiconductor integrated circuit according to claim 12 , wherein
said first master circuit and said second master circuit are incorporated in a master module coupled to a first bus.
17. The semiconductor integrated circuit according to claim 16 , further comprising:
a third master circuit; and
a second slave circuit that is assigned to said third master circuit, wherein
said third master circuit and said second slave circuit are further coupled to said first bus, and
said second slave circuit is reassigned to said master module based on said operational status of said third master circuit.
18. A method for controlling a semiconductor integrated circuit including a first master circuit, a second master circuit and at least one slave circuit, the method comprising:
upon detection that an operational status of said first master circuit is in an inactive state, reassigning said slave circuit, which is previously assigned to said first master circuit, to said second master circuit.
19. The method for controlling a semiconductor integrated circuit according to claim 18 , wherein
said slave circuit is reassigned to said second master circuit based on a change of settings of a first bus coupled to at least said first master circuit, said slave circuit and said second master circuit.
20. The method for controlling a semiconductor integrated circuit according to claim 18 , wherein
any one of said first master circuit and said second master circuit is enabled to access a first bus based on a change of settings of a second bus that is coupled to said first master circuit and said second master circuit.
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US20220269628A1 (en) * | 2021-02-25 | 2022-08-25 | Seiko Epson Corporation | Circuit Device And Electronic Apparatus |
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US20130013831A1 (en) | 2013-01-10 |
US8621262B2 (en) | 2013-12-31 |
JP2009087121A (en) | 2009-04-23 |
JP5148236B2 (en) | 2013-02-20 |
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