DE69901255D1 - Mehrprozessorsystem brücke mit zugriffskontrollierung - Google Patents

Mehrprozessorsystem brücke mit zugriffskontrollierung

Info

Publication number
DE69901255D1
DE69901255D1 DE69901255T DE69901255T DE69901255D1 DE 69901255 D1 DE69901255 D1 DE 69901255D1 DE 69901255 T DE69901255 T DE 69901255T DE 69901255 T DE69901255 T DE 69901255T DE 69901255 D1 DE69901255 D1 DE 69901255D1
Authority
DE
Germany
Prior art keywords
bridge
bus
error
processing
device bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69901255T
Other languages
English (en)
Other versions
DE69901255T2 (de
Inventor
Stephen Rowlinson
A Oyelakin
Paul J Garnett
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of DE69901255D1 publication Critical patent/DE69901255D1/de
Application granted granted Critical
Publication of DE69901255T2 publication Critical patent/DE69901255T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1658—Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/004—Error avoidance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2268—Logging of test results
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1608—Error detection by comparing the output signals of redundant hardware
    • G06F11/1625—Error detection by comparing the output signals of redundant hardware in communications, e.g. transmission, interfaces
DE69901255T 1998-06-15 1999-06-03 Mehrprozessorsystem brücke mit zugriffskontrollierung Expired - Fee Related DE69901255T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/097,485 US6587961B1 (en) 1998-06-15 1998-06-15 Multi-processor system bridge with controlled access
PCT/US1999/012431 WO1999066404A1 (en) 1998-06-15 1999-06-03 Multi-processor system bridge with controlled access

Publications (2)

Publication Number Publication Date
DE69901255D1 true DE69901255D1 (de) 2002-05-16
DE69901255T2 DE69901255T2 (de) 2002-10-02

Family

ID=22263618

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69901255T Expired - Fee Related DE69901255T2 (de) 1998-06-15 1999-06-03 Mehrprozessorsystem brücke mit zugriffskontrollierung

Country Status (6)

Country Link
US (1) US6587961B1 (de)
EP (1) EP1090350B1 (de)
JP (1) JP2002518736A (de)
AT (1) ATE216098T1 (de)
DE (1) DE69901255T2 (de)
WO (1) WO1999066404A1 (de)

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US7181705B2 (en) * 2000-01-18 2007-02-20 Cadence Design Systems, Inc. Hierarchical test circuit structure for chips with multiple circuit blocks
US6976217B1 (en) * 2000-10-13 2005-12-13 Palmsource, Inc. Method and apparatus for integrating phone and PDA user interface on a single processor
US6691193B1 (en) * 2000-10-18 2004-02-10 Sony Corporation Efficient bus utilization in a multiprocessor system by dynamically mapping memory addresses
US6684346B2 (en) * 2000-12-22 2004-01-27 Intel Corporation Method and apparatus for machine check abort handling in a multiprocessing system
FR2819603B1 (fr) * 2001-01-16 2003-06-13 Centre Nat Rech Scient Procede d'injecteur d'erreurs par interruptions
US7010715B2 (en) * 2001-01-25 2006-03-07 Marconi Intellectual Property (Ringfence), Inc. Redundant control architecture for a network device
US9552047B2 (en) 2001-03-05 2017-01-24 Pact Xpp Technologies Ag Multiprocessor having runtime adjustable clock and clock dependent power supply
US9436631B2 (en) 2001-03-05 2016-09-06 Pact Xpp Technologies Ag Chip including memory element storing higher level memory data on a page by page basis
US9411532B2 (en) * 2001-09-07 2016-08-09 Pact Xpp Technologies Ag Methods and systems for transferring data between a processing device and external devices
US6950893B2 (en) * 2001-03-22 2005-09-27 I-Bus Corporation Hybrid switching architecture
US20030065861A1 (en) * 2001-09-28 2003-04-03 Clark Clyde S. Dual system masters
US6981079B2 (en) * 2002-03-21 2005-12-27 International Business Machines Corporation Critical datapath error handling in a multiprocessor architecture
US9170812B2 (en) 2002-03-21 2015-10-27 Pact Xpp Technologies Ag Data processing system having integrated pipelined array data processor
US20040059862A1 (en) * 2002-09-24 2004-03-25 I-Bus Corporation Method and apparatus for providing redundant bus control
US7103808B2 (en) * 2003-04-10 2006-09-05 International Business Machines Corporation Apparatus for reporting and isolating errors below a host bridge
US20050193246A1 (en) 2004-02-19 2005-09-01 Marconi Communications, Inc. Method, apparatus and software for preventing switch failures in the presence of faults
US7321985B2 (en) * 2004-02-26 2008-01-22 International Business Machines Corporation Method for achieving higher availability of computer PCI adapters
US7669073B2 (en) * 2005-08-19 2010-02-23 Stratus Technologies Bermuda Ltd. Systems and methods for split mode operation of fault-tolerant computer systems
US7734843B2 (en) * 2006-05-25 2010-06-08 International Business Machines Corporation Computer-implemented method, apparatus, and computer program product for stalling DMA operations during memory migration
US7912068B2 (en) * 2007-07-20 2011-03-22 Oracle America, Inc. Low-latency scheduling in large switches
DE102008012285B3 (de) * 2008-03-03 2009-07-23 Texas Instruments Deutschland Gmbh Rechnerkernsystem mit Selbstschutz
CN103186491B (zh) * 2011-12-30 2017-11-07 中兴通讯股份有限公司 一种端到端硬件消息传输的实现方法和装置
CN113641622A (zh) * 2020-04-27 2021-11-12 富泰华工业（深圳）有限公司 访问数据总线的装置、方法及系统

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US6233702B1 (en) 1992-12-17 2001-05-15 Compaq Computer Corporation Self-checked, lock step processor pairs
JPH06187257A (ja) * 1992-12-17 1994-07-08 Fujitsu Ltd システムバス制御方式
US5426740A (en) * 1994-01-14 1995-06-20 Ast Research, Inc. Signaling protocol for concurrent bus access in a multiprocessor system
US5515516A (en) * 1994-03-01 1996-05-07 Intel Corporation Initialization mechanism for symmetric arbitration agents
US5530946A (en) * 1994-10-28 1996-06-25 Dell Usa, L.P. Processor failure detection and recovery circuit in a dual processor computer system and method of operation thereof
US5642506A (en) * 1994-12-14 1997-06-24 International Business Machines Corporation Method and apparatus for initializing a multiprocessor system
US5586253A (en) * 1994-12-15 1996-12-17 Stratus Computer Method and apparatus for validating I/O addresses in a fault-tolerant computer system
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US6141769A (en) * 1996-05-16 2000-10-31 Resilience Corporation Triple modular redundant computer system and associated method
US5915082A (en) * 1996-06-07 1999-06-22 Lockheed Martin Corporation Error detection and fault isolation for lockstep processor systems
US5953538A (en) * 1996-11-12 1999-09-14 Digital Equipment Corporation Method and apparatus providing DMA transfers between devices coupled to different host bus bridges
US6128711A (en) * 1996-11-12 2000-10-03 Compaq Computer Corporation Performance optimization and system bus duty cycle reduction by I/O bridge partial cache line writes
SE511114C2 (sv) * 1997-12-10 1999-08-09 Ericsson Telefon Ab L M Metod vid processor, samt processor anpassad att verka enligt metoden
US6223320B1 (en) * 1998-02-10 2001-04-24 International Business Machines Corporation Efficient CRC generation utilizing parallel table lookup operations
JP3071752B2 (ja) * 1998-03-24 2000-07-31 三菱電機株式会社 ブリッジ方法、バスブリッジ及びマルチプロセッサシステム
US6163815A (en) * 1998-05-27 2000-12-19 International Business Machines Corporation Dynamic disablement of a transaction ordering in response to an error
US6141718A (en) * 1998-06-15 2000-10-31 Sun Microsystems, Inc. Processor bridge with dissimilar data registers which is operable to disregard data differences for dissimilar data direct memory accesses
US6173351B1 (en) * 1998-06-15 2001-01-09 Sun Microsystems, Inc. Multi-processor system bridge
US6138198A (en) * 1998-06-15 2000-10-24 Sun Microsystems, Inc. Processor bridge with dissimilar data registers which is operable to disregard data differences for dissimilar data write accesses
US5991900A (en) * 1998-06-15 1999-11-23 Sun Microsystems, Inc. Bus controller
US6167477A (en) * 1998-06-15 2000-12-26 Sun Microsystems, Inc. Computer system bridge employing a resource control mechanism with programmable registers to control resource allocation
US6148348A (en) * 1998-06-15 2000-11-14 Sun Microsystems, Inc. Bridge interfacing two processing sets operating in a lockstep mode and having a posted write buffer storing write operations upon detection of a lockstep error
US6247143B1 (en) * 1998-06-30 2001-06-12 Sun Microsystems, Inc. I/O handling for a multiprocessor computer system
US6189117B1 (en) * 1998-08-18 2001-02-13 International Business Machines Corporation Error handling between a processor and a system managed by the processor

Also Published As

Publication number Publication date
EP1090350A1 (de) 2001-04-11
JP2002518736A (ja) 2002-06-25
WO1999066404A1 (en) 1999-12-23
US6587961B1 (en) 2003-07-01
ATE216098T1 (de) 2002-04-15
EP1090350B1 (de) 2002-04-10
DE69901255T2 (de) 2002-10-02

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Legal Events

Date Code Title Description
8339 Ceased/non-payment of the annual fee