DE69901251T2 - Prozessorbrücke mit nachschreibspüffer - Google Patents

Prozessorbrücke mit nachschreibspüffer

Info

Publication number
DE69901251T2
DE69901251T2 DE69901251T DE69901251T DE69901251T2 DE 69901251 T2 DE69901251 T2 DE 69901251T2 DE 69901251 T DE69901251 T DE 69901251T DE 69901251 T DE69901251 T DE 69901251T DE 69901251 T2 DE69901251 T2 DE 69901251T2
Authority
DE
Germany
Prior art keywords
bridge
error mode
bus
processing
operable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69901251T
Other languages
English (en)
Other versions
DE69901251D1 (de
Inventor
Paul J Garnett
Stephen Rowlinson
A Oyelakin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of DE69901251D1 publication Critical patent/DE69901251D1/de
Application granted granted Critical
Publication of DE69901251T2 publication Critical patent/DE69901251T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/165—Error detection by comparing the output of redundant processing systems with continued operation after detection of the error
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1658—Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1608—Error detection by comparing the output signals of redundant hardware
    • G06F11/1625—Error detection by comparing the output signals of redundant hardware in communications, e.g. transmission, interfaces
DE69901251T 1998-06-15 1999-06-04 Prozessorbrücke mit nachschreibspüffer Expired - Fee Related DE69901251T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/094,844 US6148348A (en) 1998-06-15 1998-06-15 Bridge interfacing two processing sets operating in a lockstep mode and having a posted write buffer storing write operations upon detection of a lockstep error
PCT/US1999/012606 WO1999066406A1 (en) 1998-06-15 1999-06-04 Processor bridge with posted write buffer

Publications (2)

Publication Number Publication Date
DE69901251D1 DE69901251D1 (de) 2002-05-16
DE69901251T2 true DE69901251T2 (de) 2002-10-31

Family

ID=22247506

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69901251T Expired - Fee Related DE69901251T2 (de) 1998-06-15 1999-06-04 Prozessorbrücke mit nachschreibspüffer

Country Status (6)

Country Link
US (1) US6148348A (de)
EP (1) EP1088273B1 (de)
JP (1) JP2002518738A (de)
AT (1) ATE216097T1 (de)
DE (1) DE69901251T2 (de)
WO (1) WO1999066406A1 (de)

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US6625756B1 (en) * 1997-12-19 2003-09-23 Intel Corporation Replay mechanism for soft error recovery
US6587961B1 (en) * 1998-06-15 2003-07-01 Sun Microsystems, Inc. Multi-processor system bridge with controlled access
US6138198A (en) * 1998-06-15 2000-10-24 Sun Microsystems, Inc. Processor bridge with dissimilar data registers which is operable to disregard data differences for dissimilar data write accesses
US6366968B1 (en) * 1998-06-26 2002-04-02 Intel Corporation Physical write packets processing when posted write error queue is full, with posted write error queue storing physical write requests when posted write packet fails
US6820213B1 (en) * 2000-04-13 2004-11-16 Stratus Technologies Bermuda, Ltd. Fault-tolerant computer system with voter delay buffer
US6687851B1 (en) 2000-04-13 2004-02-03 Stratus Technologies Bermuda Ltd. Method and system for upgrading fault-tolerant systems
GB2369691B (en) * 2000-11-29 2003-06-04 Sun Microsystems Inc Control logic for memory modification tracking
GB2369692B (en) * 2000-11-29 2002-10-16 Sun Microsystems Inc Processor state reintegration
GB2369694B (en) * 2000-11-29 2002-10-16 Sun Microsystems Inc Efficient memory modification tracking
GB2369690B (en) * 2000-11-29 2002-10-16 Sun Microsystems Inc Enhanced protection for memory modification tracking
US6742136B2 (en) * 2000-12-05 2004-05-25 Fisher-Rosemount Systems Inc. Redundant devices in a process control system
DE10124027A1 (de) * 2001-05-16 2002-11-21 Continental Teves Ag & Co Ohg Verfahren,Mikroprozessorsystem für sicherheitskritische Regelungen und dessen Verwendung
US7165128B2 (en) * 2001-05-23 2007-01-16 Sony Corporation Multifunctional I/O organizer unit for multiprocessor multimedia chips
US6985975B1 (en) * 2001-06-29 2006-01-10 Sanera Systems, Inc. Packet lockstep system and method
US6954819B2 (en) * 2002-01-09 2005-10-11 Storcase Technology, Inc. Peripheral bus switch to maintain continuous peripheral bus interconnect system operation
US7155721B2 (en) * 2002-06-28 2006-12-26 Hewlett-Packard Development Company, L.P. Method and apparatus for communicating information between lock stepped processors
US7085959B2 (en) * 2002-07-03 2006-08-01 Hewlett-Packard Development Company, L.P. Method and apparatus for recovery from loss of lock step
US7168006B2 (en) * 2003-06-30 2007-01-23 International Business Machines Corporation Method and system for saving the state of integrated circuits upon failure
US7415551B2 (en) * 2003-08-18 2008-08-19 Dell Products L.P. Multi-host virtual bridge input-output resource switch
US7194663B2 (en) * 2003-11-18 2007-03-20 Honeywell International, Inc. Protective bus interface and method
US7404017B2 (en) 2004-01-16 2008-07-22 International Business Machines Corporation Method for managing data flow through a processing system
US7296181B2 (en) * 2004-04-06 2007-11-13 Hewlett-Packard Development Company, L.P. Lockstep error signaling
US7366948B2 (en) * 2004-10-25 2008-04-29 Hewlett-Packard Development Company, L.P. System and method for maintaining in a multi-processor system a spare processor that is in lockstep for use in recovering from loss of lockstep for another processor
US7356733B2 (en) * 2004-10-25 2008-04-08 Hewlett-Packard Development Company, L.P. System and method for system firmware causing an operating system to idle a processor
US7627781B2 (en) * 2004-10-25 2009-12-01 Hewlett-Packard Development Company, L.P. System and method for establishing a spare processor for recovering from loss of lockstep in a boot processor
US7818614B2 (en) * 2004-10-25 2010-10-19 Hewlett-Packard Development Company, L.P. System and method for reintroducing a processor module to an operating system after lockstep recovery
US20060107116A1 (en) * 2004-10-25 2006-05-18 Michaelis Scott L System and method for reestablishing lockstep for a processor module for which loss of lockstep is detected
US7624302B2 (en) 2004-10-25 2009-11-24 Hewlett-Packard Development Company, L.P. System and method for switching the role of boot processor to a spare processor responsive to detection of loss of lockstep in a boot processor
US7516359B2 (en) * 2004-10-25 2009-04-07 Hewlett-Packard Development Company, L.P. System and method for using information relating to a detected loss of lockstep for determining a responsive action
US7502958B2 (en) * 2004-10-25 2009-03-10 Hewlett-Packard Development Company, L.P. System and method for providing firmware recoverable lockstep protection
US7308566B2 (en) * 2004-10-25 2007-12-11 Hewlett-Packard Development Company, L.P. System and method for configuring lockstep mode of a processor module
US7272681B2 (en) * 2005-08-05 2007-09-18 Raytheon Company System having parallel data processors which generate redundant effector date to detect errors
US7669073B2 (en) * 2005-08-19 2010-02-23 Stratus Technologies Bermuda Ltd. Systems and methods for split mode operation of fault-tolerant computer systems
US20080123522A1 (en) * 2006-07-28 2008-05-29 David Charles Elliott Redundancy coupler for industrial communications networks
US8131951B2 (en) * 2008-05-30 2012-03-06 Freescale Semiconductor, Inc. Utilization of a store buffer for error recovery on a store allocation cache miss
EP2550598A1 (de) * 2010-03-23 2013-01-30 Continental Teves AG & Co. oHG Redundante zwei-prozessor-steuerung und steuerungsverfahren
WO2011117156A2 (de) * 2010-03-23 2011-09-29 Continental Teves Ag & Co. Ohg Kontrollrechnersystem, verfahren zur steuerung eines kontrollrechnersystems, sowie verwendung eines kontrollrechnersystems
US9146835B2 (en) 2012-01-05 2015-09-29 International Business Machines Corporation Methods and systems with delayed execution of multiple processors
US11494087B2 (en) * 2018-10-31 2022-11-08 Advanced Micro Devices, Inc. Tolerating memory stack failures in multi-stack systems
US11645155B2 (en) 2021-02-22 2023-05-09 Nxp B.V. Safe-stating a system interconnect within a data processing system
DE102021116389A1 (de) 2021-06-24 2022-12-29 ebm-papst neo GmbH & Co. KG Master-Slave-Netzwerk und Verfahren zum Betreiben einesMaster-Slave-Netzwerks

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US4965717A (en) * 1988-12-09 1990-10-23 Tandem Computers Incorporated Multiple processor system having shared memory with private-write capability
US5251227A (en) * 1989-08-01 1993-10-05 Digital Equipment Corporation Targeted resets in a data processor including a trace memory to store transactions
GB2268817B (en) * 1992-07-17 1996-05-01 Integrated Micro Products Ltd A fault-tolerant computer system
US6233702B1 (en) * 1992-12-17 2001-05-15 Compaq Computer Corporation Self-checked, lock step processor pairs
US5838899A (en) * 1994-09-20 1998-11-17 Stratus Computer Digital data processing methods and apparatus for fault isolation
US5694556A (en) * 1995-06-07 1997-12-02 International Business Machines Corporation Data processing system including buffering mechanism for inbound and outbound reads and posted writes
US5784599A (en) * 1995-12-15 1998-07-21 Compaq Computer Corporation Method and apparatus for establishing host bus clock frequency and processor core clock ratios in a multi-processor computer system
TW320701B (de) * 1996-05-16 1997-11-21 Resilience Corp
US5953742A (en) * 1996-07-01 1999-09-14 Sun Microsystems, Inc. Memory management in fault tolerant computer systems utilizing a first and second recording mechanism and a reintegration mechanism
US5881253A (en) * 1996-12-31 1999-03-09 Compaq Computer Corporation Computer system using posted memory write buffers in a bridge to implement system management mode

Also Published As

Publication number Publication date
WO1999066406A1 (en) 1999-12-23
JP2002518738A (ja) 2002-06-25
DE69901251D1 (de) 2002-05-16
ATE216097T1 (de) 2002-04-15
EP1088273A1 (de) 2001-04-04
EP1088273B1 (de) 2002-04-10
WO1999066406A9 (en) 2000-04-06
US6148348A (en) 2000-11-14

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Legal Events

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8339 Ceased/non-payment of the annual fee