DE69900915T2 - Prozessorbrücke mit zugriff zum verschiedenen daten - Google Patents

Prozessorbrücke mit zugriff zum verschiedenen daten

Info

Publication number
DE69900915T2
DE69900915T2 DE69900915T DE69900915T DE69900915T2 DE 69900915 T2 DE69900915 T2 DE 69900915T2 DE 69900915 T DE69900915 T DE 69900915T DE 69900915 T DE69900915 T DE 69900915T DE 69900915 T2 DE69900915 T2 DE 69900915T2
Authority
DE
Germany
Prior art keywords
data
processing
bridge
bus
read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69900915T
Other languages
English (en)
Other versions
DE69900915D1 (de
Inventor
Stephen Rowlinson
Femi A Oyelakin
Paul J Garnett
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Application granted granted Critical
Publication of DE69900915D1 publication Critical patent/DE69900915D1/de
Publication of DE69900915T2 publication Critical patent/DE69900915T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1608—Error detection by comparing the output signals of redundant hardware
    • G06F11/1616—Error detection by comparing the output signals of redundant hardware where the redundant component is an I/O device or an adapter therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1658—Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/845—Systems in which the redundancy can be transformed in increased performance
DE69900915T 1998-06-15 1999-06-03 Prozessorbrücke mit zugriff zum verschiedenen daten Expired - Fee Related DE69900915T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/097,487 US6141718A (en) 1998-06-15 1998-06-15 Processor bridge with dissimilar data registers which is operable to disregard data differences for dissimilar data direct memory accesses
PCT/US1999/012432 WO1999066405A1 (en) 1998-06-15 1999-06-03 Processor bridge with dissimilar data access

Publications (2)

Publication Number Publication Date
DE69900915D1 DE69900915D1 (de) 2002-03-28
DE69900915T2 true DE69900915T2 (de) 2002-08-29

Family

ID=22263628

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69900915T Expired - Fee Related DE69900915T2 (de) 1998-06-15 1999-06-03 Prozessorbrücke mit zugriff zum verschiedenen daten

Country Status (6)

Country Link
US (1) US6141718A (de)
EP (1) EP1088271B1 (de)
JP (1) JP2002518737A (de)
AT (1) ATE213553T1 (de)
DE (1) DE69900915T2 (de)
WO (1) WO1999066405A1 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6587961B1 (en) * 1998-06-15 2003-07-01 Sun Microsystems, Inc. Multi-processor system bridge with controlled access
US6275891B1 (en) * 1999-02-25 2001-08-14 Lsi Logic Corporation Modular and scalable system for signal and multimedia processing
US6301632B1 (en) * 1999-03-26 2001-10-09 Vlsi Technology, Inc. Direct memory access system and method to bridge PCI bus protocols and hitachi SH4 protocols
JP2000315186A (ja) * 1999-05-06 2000-11-14 Hitachi Ltd 半導体装置
US6708244B2 (en) * 1999-07-22 2004-03-16 Cypress Semiconductor Corp. Optimized I2O messaging unit
KR100324279B1 (ko) * 1999-08-24 2002-02-25 서평원 교환기에서 이중화 프로세서 간 메모리 일치 시스템 및 방법
US6687851B1 (en) 2000-04-13 2004-02-03 Stratus Technologies Bermuda Ltd. Method and system for upgrading fault-tolerant systems
US6820213B1 (en) * 2000-04-13 2004-11-16 Stratus Technologies Bermuda, Ltd. Fault-tolerant computer system with voter delay buffer
US6636919B1 (en) * 2000-10-16 2003-10-21 Motorola, Inc. Method for host protection during hot swap in a bridged, pipelined network
GB2369694B (en) * 2000-11-29 2002-10-16 Sun Microsystems Inc Efficient memory modification tracking
US7155721B2 (en) * 2002-06-28 2006-12-26 Hewlett-Packard Development Company, L.P. Method and apparatus for communicating information between lock stepped processors
US7194663B2 (en) * 2003-11-18 2007-03-20 Honeywell International, Inc. Protective bus interface and method
DE102005037217A1 (de) 2005-08-08 2007-02-15 Robert Bosch Gmbh Verfahren und Vorrichtung zum Vergleich von Daten bei einem Rechnersystem mit wenigstens zwei Ausführungseinheiten
US7669073B2 (en) * 2005-08-19 2010-02-23 Stratus Technologies Bermuda Ltd. Systems and methods for split mode operation of fault-tolerant computer systems

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5551035A (en) * 1989-06-30 1996-08-27 Lucent Technologies Inc. Method and apparatus for inter-object communication in an object-oriented program controlled system
FR2685511B1 (fr) * 1991-12-19 1994-02-04 Bull Sa Procede de classification des architectures d'ordinateur.
US5301283A (en) * 1992-04-16 1994-04-05 Digital Equipment Corporation Dynamic arbitration for system bus control in multiprocessor data processing system
GB2268817B (en) * 1992-07-17 1996-05-01 Integrated Micro Products Ltd A fault-tolerant computer system
US5809340A (en) * 1993-04-30 1998-09-15 Packard Bell Nec Adaptively generating timing signals for access to various memory devices based on stored profiles
US6311286B1 (en) * 1993-04-30 2001-10-30 Nec Corporation Symmetric multiprocessing system with unified environment and distributed system functions
EP0731945B1 (de) * 1993-12-01 2000-05-17 Marathon Technologies Corporation Fehler-betriebssichere/fehler tolerante computerbetriebsmethode
US5586253A (en) * 1994-12-15 1996-12-17 Stratus Computer Method and apparatus for validating I/O addresses in a fault-tolerant computer system
EP0727728A1 (de) * 1995-02-15 1996-08-21 International Business Machines Corporation Leistungssteuerung eines Computersystems
AU5368696A (en) * 1995-03-22 1996-10-08 Ast Research, Inc. Rule-based dram controller
TW320701B (de) * 1996-05-16 1997-11-21 Resilience Corp
US5844856A (en) * 1996-06-19 1998-12-01 Cirrus Logic, Inc. Dual port memories and systems and methods using the same

Also Published As

Publication number Publication date
ATE213553T1 (de) 2002-03-15
US6141718A (en) 2000-10-31
WO1999066405A1 (en) 1999-12-23
EP1088271A1 (de) 2001-04-04
EP1088271B1 (de) 2002-02-20
JP2002518737A (ja) 2002-06-25
DE69900915D1 (de) 2002-03-28

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Legal Events

Date Code Title Description
8339 Ceased/non-payment of the annual fee