DE60112998D1 - Automatische Prüfmustererzeugung für Funktional Register Transfer Level Schaltungen mit Zuweisungsentscheindungsdiagramme - Google Patents

Automatische Prüfmustererzeugung für Funktional Register Transfer Level Schaltungen mit Zuweisungsentscheindungsdiagramme

Info

Publication number
DE60112998D1
DE60112998D1 DE60112998T DE60112998T DE60112998D1 DE 60112998 D1 DE60112998 D1 DE 60112998D1 DE 60112998 T DE60112998 T DE 60112998T DE 60112998 T DE60112998 T DE 60112998T DE 60112998 D1 DE60112998 D1 DE 60112998D1
Authority
DE
Germany
Prior art keywords
test pattern
pattern generation
automatic test
register transfer
transfer level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE60112998T
Other languages
English (en)
Other versions
DE60112998T2 (de
Inventor
Indradeep Ghosh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE60112998D1 publication Critical patent/DE60112998D1/de
Publication of DE60112998T2 publication Critical patent/DE60112998T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318371—Methodologies therefor, e.g. algorithms, procedures
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318392—Generation of test inputs, e.g. test vectors, patterns or sequences for sequential circuits
DE60112998T 2000-06-05 2001-06-04 Automatische Prüfmustererzeugung für Funktional Register Transfer Level Schaltungen mit Zuweisungsentscheindungsdiagramme Expired - Fee Related DE60112998T2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US20934000P 2000-06-05 2000-06-05
US209340P 2000-06-05
US09/851,708 US6823486B2 (en) 2000-06-05 2001-05-08 Automatic test pattern generation for functional register transfer level circuits using assignment decision diagrams
US851708 2001-05-08

Publications (2)

Publication Number Publication Date
DE60112998D1 true DE60112998D1 (de) 2005-10-06
DE60112998T2 DE60112998T2 (de) 2006-02-23

Family

ID=26904074

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60112998T Expired - Fee Related DE60112998T2 (de) 2000-06-05 2001-06-04 Automatische Prüfmustererzeugung für Funktional Register Transfer Level Schaltungen mit Zuweisungsentscheindungsdiagramme

Country Status (4)

Country Link
US (1) US6823486B2 (de)
EP (1) EP1162472B1 (de)
JP (1) JP2002049655A (de)
DE (1) DE60112998T2 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6823486B2 (en) * 2000-06-05 2004-11-23 Fujitsu Limited Automatic test pattern generation for functional register transfer level circuits using assignment decision diagrams
US7165231B2 (en) * 2000-12-18 2007-01-16 Yardstick Research, Llc Method and system for incremental behavioral validation of digital design expressed in hardware description language
US6877141B2 (en) * 2003-04-01 2005-04-05 Fujitsu Limited Evaluating a validation vector for validating a network design
US7168014B2 (en) * 2003-04-01 2007-01-23 Fujitsu Limited Propagating an error through a network
US7139929B2 (en) * 2003-04-01 2006-11-21 Fujitsu Limited Generating a test environment for validating a network design
JP4565965B2 (ja) * 2004-10-29 2010-10-20 株式会社システム・ジェイディー 抽出装置、抽出方法及びプログラム
KR100736679B1 (ko) * 2006-08-09 2007-07-06 주식회사 유니테스트 반도체 테스트를 위한 패턴 생성 장치 및 패턴 생성 방법
US8001498B2 (en) * 2008-10-27 2011-08-16 Synopsys, Inc. Method and apparatus for memory abstraction and verification using same
DE102011076780B4 (de) * 2011-05-31 2021-12-09 Airbus Operations Gmbh Verfahren und Vorrichtung zur Zustandsüberwachung, Computerprogrammprodukt
CN102662144B (zh) * 2012-03-30 2017-07-25 北京大学 一种基于活性测度的硬件木马检测方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5572437A (en) 1990-04-06 1996-11-05 Lsi Logic Corporation Method and system for creating and verifying structural logic model of electronic design from behavioral description, including generation of logic and timing models
US5323108A (en) * 1992-01-23 1994-06-21 Hewlett-Packard Company Method for generating functional tests for printed circuit boards based on pattern matching of models
US5602856A (en) 1993-04-06 1997-02-11 Nippon Telegraph And Telephone Corporation Test pattern generation for logic circuits with reduced backtracking operations
JP2974900B2 (ja) 1993-12-13 1999-11-10 株式会社 エイ・ティ・アール人間情報通信研究所 自律進化型ハードウェア設計システム
US5513123A (en) 1994-06-30 1996-04-30 Nec Usa, Inc. Non-scan design-for-testability of RT-level data paths
US5625630A (en) 1996-04-24 1997-04-29 Lucent Technologies Inc. Increasing testability by clock transformation
US5696771A (en) 1996-05-17 1997-12-09 Synopsys, Inc. Method and apparatus for performing partial unscan and near full scan within design for test applications
US5883809A (en) 1996-07-26 1999-03-16 3 Com Corporation Behavioral language models for testing and verification of digital electronic circuits
JPH10222374A (ja) * 1996-10-28 1998-08-21 Altera Corp 遠隔ソフトウェア技術支援を提供するための方法
US5748647A (en) * 1996-10-31 1998-05-05 Nec Usa, Inc. Low cost testing method for register transfer level circuits
US5875196A (en) 1997-01-03 1999-02-23 Nec Usa, Inc. Deriving signal constraints to accelerate sequential test generation
US5991523A (en) 1997-03-18 1999-11-23 Xilinx, Inc. Method and system for HDL global signal simulation and verification
FR2798472B1 (fr) * 1999-09-15 2001-12-14 Centre Nat Etd Spatiales Procede de localisation d'elements defectueux dans un circuit integre
US6823486B2 (en) * 2000-06-05 2004-11-23 Fujitsu Limited Automatic test pattern generation for functional register transfer level circuits using assignment decision diagrams

Also Published As

Publication number Publication date
EP1162472A3 (de) 2004-04-07
DE60112998T2 (de) 2006-02-23
US6823486B2 (en) 2004-11-23
EP1162472A2 (de) 2001-12-12
EP1162472B1 (de) 2005-08-31
JP2002049655A (ja) 2002-02-15
US20020032889A1 (en) 2002-03-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee