DE3750311T2 - Gerät und Verfahren zur Übertragung zwischen Prozessoren. - Google Patents

Gerät und Verfahren zur Übertragung zwischen Prozessoren.

Info

Publication number
DE3750311T2
DE3750311T2 DE3750311T DE3750311T DE3750311T2 DE 3750311 T2 DE3750311 T2 DE 3750311T2 DE 3750311 T DE3750311 T DE 3750311T DE 3750311 T DE3750311 T DE 3750311T DE 3750311 T2 DE3750311 T2 DE 3750311T2
Authority
DE
Germany
Prior art keywords
processors
transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3750311T
Other languages
English (en)
Other versions
DE3750311D1 (de
Inventor
Victor M Morganti
Patrick E Prange
James B Geyer
George J Barlow
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Inc
Original Assignee
Bull HN Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull HN Information Systems Inc filed Critical Bull HN Information Systems Inc
Publication of DE3750311D1 publication Critical patent/DE3750311D1/de
Application granted granted Critical
Publication of DE3750311T2 publication Critical patent/DE3750311T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163Interprocessor communication
    • G06F15/167Interprocessor communication using a common memory, e.g. mailbox
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163Interprocessor communication
    • G06F15/17Interprocessor communication using an input/output type connection, e.g. channel, I/O port
DE3750311T 1986-05-30 1987-05-27 Gerät und Verfahren zur Übertragung zwischen Prozessoren. Expired - Fee Related DE3750311T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US86914786A 1986-05-30 1986-05-30

Publications (2)

Publication Number Publication Date
DE3750311D1 DE3750311D1 (de) 1994-09-08
DE3750311T2 true DE3750311T2 (de) 1995-03-30

Family

ID=25353015

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3750311T Expired - Fee Related DE3750311T2 (de) 1986-05-30 1987-05-27 Gerät und Verfahren zur Übertragung zwischen Prozessoren.

Country Status (5)

Country Link
US (1) US5850521A (de)
EP (1) EP0247604B1 (de)
AU (1) AU597980B2 (de)
CA (1) CA1292808C (de)
DE (1) DE3750311T2 (de)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU630299B2 (en) * 1990-07-10 1992-10-22 Fujitsu Limited A data gathering/scattering system in a parallel computer
US6493407B1 (en) * 1997-05-27 2002-12-10 Fusion Micromedia Corporation Synchronous latching bus arrangement for interfacing discrete and/or integrated modules in a digital system and associated method
US5983303A (en) * 1997-05-27 1999-11-09 Fusion Micromedia Corporation Bus arrangements for interconnection of discrete and/or integrated modules in a digital system and associated method
US7233977B2 (en) * 1998-12-18 2007-06-19 Emc Corporation Messaging mechanism employing mailboxes for inter processor communications
US6678716B1 (en) * 2000-06-19 2004-01-13 J. D. Edwards World Source Company System and method for managing processes
US20020099893A1 (en) * 2001-01-24 2002-07-25 Nguyen Tuyet-Huong Thi System and method for the handling of system management interrupts in a multiprocessor computer system
US20040095948A1 (en) * 2002-11-18 2004-05-20 Chang-Ming Lin Data return arbitration
US7805557B2 (en) * 2005-07-12 2010-09-28 Arm Limited Interrupt controller and method for handling interrupts
US8849940B1 (en) * 2007-12-14 2014-09-30 Blue Coat Systems, Inc. Wide area network file system with low latency write command processing
JP4691153B2 (ja) * 2008-12-10 2011-06-01 富士通株式会社 マルチコアプロセッサ,制御方法および情報処理装置
US8793423B2 (en) * 2012-03-28 2014-07-29 Advanced Micro Devices, Inc. Servicing interrupt requests in a computer system
US9329671B2 (en) * 2013-01-29 2016-05-03 Nvidia Corporation Power-efficient inter processor communication scheduling
US10296469B1 (en) 2014-07-24 2019-05-21 Pure Storage, Inc. Access control in a flash storage system

Family Cites Families (28)

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Publication number Priority date Publication date Assignee Title
US3678467A (en) * 1970-10-20 1972-07-18 Bell Telephone Labor Inc Multiprocessor with cooperative program execution
US3988716A (en) * 1974-08-05 1976-10-26 Nasa Computer interface system
FR2288352A1 (fr) * 1974-10-15 1976-05-14 Burroughs Corp Appareil et procede de traitement de donnees par association
US4041461A (en) * 1975-07-25 1977-08-09 International Business Machines Corporation Signal analyzer system
US4149244A (en) * 1976-06-07 1979-04-10 Amdahl Corporation Data processing system including a program-executing secondary system controlling a program-executing primary system
US4223380A (en) * 1978-04-06 1980-09-16 Ncr Corporation Distributed multiprocessor communication system
DE3069249D1 (en) * 1979-02-13 1984-10-31 Secr Defence Brit Data processing unit and data processing system comprising a plurality of such data processing units
JPS55134459A (en) * 1979-04-06 1980-10-20 Hitachi Ltd Data processing system
NL7907179A (nl) * 1979-09-27 1981-03-31 Philips Nv Signaalprocessorinrichting met voorwaardelijke- -interrupteenheid en multiprocessorsysteem met deze signaalprocessorinrichtingen.
US4349873A (en) * 1980-04-02 1982-09-14 Motorola, Inc. Microprocessor interrupt processing
US4365294A (en) * 1980-04-10 1982-12-21 Nizdorf Computer Corporation Modular terminal system using a common bus
DE3026362C2 (de) * 1980-07-11 1984-12-06 Siemens AG, 1000 Berlin und 8000 München Einrichtung zum schnellen blockorientierten Datentransfer zwischen zwei sich im Betrieb befindlichen Rechnern
JPS57117027A (en) * 1981-01-13 1982-07-21 Nec Corp Signal sending and receiving circuit
US4394727A (en) * 1981-05-04 1983-07-19 International Business Machines Corporation Multi-processor task dispatching apparatus
US4467412A (en) * 1981-05-18 1984-08-21 Atari, Inc. Slave processor with clock controlled by internal ROM & master processor
US4417336A (en) * 1981-06-18 1983-11-22 The Bendix Corporation Method of testing with computers
US4543627A (en) * 1981-12-14 1985-09-24 At&T Bell Laboratories Internal communication arrangement for a multiprocessor system
US4504902A (en) * 1982-03-25 1985-03-12 At&T Bell Laboratories Cache arrangement for direct memory access block transfer
DE3376590D1 (en) * 1982-04-28 1988-06-16 Int Computers Ltd Data processing system
US4731736A (en) * 1983-04-18 1988-03-15 Motorola, Inc. Method and apparatus for coordinating execution of an instruction by a selected coprocessor
US4862351A (en) * 1983-09-01 1989-08-29 Unisys Corporation Method of executing called activities via depictor-linked low level language microcode, hardware logic, and high level language commands; and apparatus for same
US4648030A (en) * 1983-09-22 1987-03-03 Digital Equipment Corporation Cache invalidation mechanism for multiprocessor systems
US4598356A (en) * 1983-12-30 1986-07-01 International Business Machines Corporation Data processing system including a main processor and a co-processor and co-processor error handling logic
JPS61855A (ja) * 1984-03-06 1986-01-06 コ−デツクス・コ−ポレ−シヨン プロセサ・インタフエ−ス回路
JPH0670787B2 (ja) * 1984-06-29 1994-09-07 富士通株式会社 処理装置間指令転送制御システム
US4648034A (en) * 1984-08-27 1987-03-03 Zilog, Inc. Busy signal interface between master and slave processors in a computer system
IT1184553B (it) * 1985-05-07 1987-10-28 Honeywell Inf Systems Architettura di sistema a piu' processori
US4718002A (en) * 1985-06-05 1988-01-05 Tandem Computers Incorporated Method for multiprocessor communications

Also Published As

Publication number Publication date
EP0247604A2 (de) 1987-12-02
CA1292808C (en) 1991-12-03
DE3750311D1 (de) 1994-09-08
AU597980B2 (en) 1990-06-14
EP0247604B1 (de) 1994-08-03
US5850521A (en) 1998-12-15
EP0247604A3 (en) 1988-07-20
AU7345787A (en) 1987-12-03

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: BULL HN INFORMATION SYSTEMS INC., BILLERICA, MASS.

8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee