DE19549661B4 - Supervision equipment for amt. of software use - enforces limit of use for copying of high-vol. storage media by degradation of output video signal when limit is exceeded - Google Patents

Abstract

Video data frames encoded and compressed according to MPEG standards are decoded and extended successively in an expansion circuit (11a). After each expansion of a single frame, this circuit delivers a signal to a host control CPU (14) which counts the signals received and decrements the content of a book-keeping data store (8). When the content falls to zero the CPU delivers symbol pattern image data which are superimposed on the video signal by an addn. circuit (19).

Description

The The present invention relates generally to an apparatus to manage or manage a software usage quantity, such as a computer program, and an image, especially of digitized software. The present invention relates in particular to a device for Manage a software usage amount using this device is able to induce a software user if a software usage amount a usable amount based on one from the software user exceeds the amount of money paid by a software beneficiary, to recognize this effect.

With the progressive development of a high storage volume having storage medium, such as a CD-ROM, etc. and a fast High capacity communication technology such as B-ISDN, etc. not only the computer program, but also image data and audio data distributed in the form of digital information via such a medium. This means that CD-ROMs are sold, on which a picture is stored, which was previously offered in the form of a video tape or game program. Furthermore, there is currently also a sales or sales system in which an image is about a Communication line is supplied to a user.

It However, this type of digital information is fairly simple to copy to other media, with a loss of quality in terms of data quality due to copying as in the case of analog information you can see. Accordingly, absolutely the same information is copied and there is a significant amount possibility for this activities hurt the author's profit. So a third party can easily do so the content of the CD-ROM on other record carriers with the mere knowledge to copy the computer operation if it is simply a writable magneto-optical disk device and a magnetic disk device high capacity has. As described above, in the majority of cases, one is Rental of this type of digital information carrier based on an impossibility the implementation an adequate security check forbidden the author. So an end user is not allowed use the software unless the end user uses the software acquires. However, this type of software is currently expensive. Therefore the end user has no alternative, but must change from Hold back the software until until he confirms that the Software is identical to that which he or she actually owns wants to get or that can be used by your own hardware. Accordingly, the earnings make little progress from this type of software.

to Eliminating this situation starts realizing a new one Software distribution system, in which a CD-ROM on which a variety of Software sets stored, which are restricted in terms of functions, for one low price is brought to the market, and the end user is about informs you of a code to remove the functional limitation after he paid a license fee for one lawful use a desired one Software set paid. Granting the right to use includes however, a difficulty in creating restrictions with regard to a useful life and the number of uses.

It is therefore no alternative to the right to use the permanent Define or grant usage. Accordingly, this is license fee inevitably high as in the case of conventional distributors of the Software.

In this context, the JP-OS 6-19707 a system for previously registering an amount of money corresponding to a software usage amount on an IC card. In this system, a user inserts this IC card into an information facility in which this software is usable (executable and reproducible) when the software requires payment of money, and the software is made usable or unusable according to a balance of the registered money supply. According to this system, the information facility allows the software to be used by removing the functional restriction on condition that the amount of money registered is equal to or larger than the minimum limit required for the use of the software. Furthermore, the information device subtracts the balance of the registered amount of money each time the software is used. In this system, if the amount of money registered on the IC card as a result of the subtraction falls below the minimum amount of money required for the use of the software, then the software is rendered unusable again by removing the functional limitation of the software is stopped. In this case, all image, sound and computer program output signals are interrupted by this information device.

If all Output signals are so interrupted, however, is the software user unable to see that this Interruption due to an error in this information facility or due to the end or consumption of the registered amount of money has been caused.

In the US 5,014,234 discloses a system which serves to protect computer programs from unauthorized use, the use of which should initially also be permitted without registration. During the original installation of the computer program, three parameters are stored on the computer, a system file being provided as storage space, which remains on the computer even when the protected computer program is uninstalled. To check the authorization to use the computer program, the three parameters are checked. For this purpose, a program is integrated in each module of the executable computer program, which can check the three parameters. A parameter is checked which can have three different values, the system being permanently deactivated for a specific value when the computer program has been registered.

A The main object of the present invention is a device to manage a software usage amount, this being Device should be able to prevent the use of the software, during a Software users about the fact that a software usage amount is informed has reached a certain usable amount by storing data in one incomplete Form are output if the software has the particular usable Amount beyond that is used.

Based The invention is explained in more detail below by drawings. In show the drawings

1 a block diagram of a structure that is common to the corresponding embodiments,

2 a block diagram of a structure of a software playback device according to a first embodiment of the present invention,

3 in a block diagram the internal functions of a DES device according 2 .

4 in a block diagram functions of central control units or CPU units according to 2 .

5 in a flowchart according to a control CPU 2 processing carried out,

6 in a flowchart according to another control CPU 2 processing carried out,

7 in a time diagram signal states in corresponding units according to 2 .

8th in a block diagram a structure of the software playback device according to a second embodiment of the present invention,

9 in a time diagram signal states in the corresponding units according to 8th .

10 a block diagram of a structure of the software playback device according to a third embodiment of the present invention,

11 in a block diagram a speech output disabling circuit according to 10 .

12 a block diagram of a structure of the software playback device according to a fourth embodiment of the present invention,

13 in a time diagram signal states in the corresponding units according to 12 .

14 a block diagram of a structure of the software playback device according to a fifth embodiment of the present invention,

15 in a time diagram according to signal states in corresponding units 14 .

16 a block diagram of a structure of the software playback device according to a sixth embodiment of the present invention,

17 FIG. 1 is a block diagram showing a device that causes a CD-ROM to store data used in the sixth embodiment of the present invention.

18 in a block diagram a configuration of a processing unit according to 16 , and

19 a timing diagram in which signal states with respect to units 16 are illustrated.

in the the preferred embodiments are described below. To reference is made to the drawings.

1 illustrates a structure that is common to the following embodiments. A software playback device 100 includes a software usage amount detection unit 101 , a determination unit 102 and a delivery / disabling unit 103 , When the software enters the software playback device 100 is entered, and when a software user uses this software, the software usage amount detection unit determines 101 a usage amount of this software. The destination unit 102 compares that by this software usage amount detection unit 101 determined software usage amount with a certain available usage amount. The levy disability unit 103 prevents delivery to the outside when the destination unit 101 determines that the software usage amount reaches the certain available usage amount.

The structure of the first embodiment will now be described with reference to 2 explained in which the structure of a software playback device as used in the first embodiment according to the present invention is illustrated in a block diagram.

According to 2 is a software playback device 2 an information device capable of using a variety of software which has a record carrier such as a CD-ROM 1 and is offered through communication over a telephone line. The variety of software has forms of digital data such as audio data, image data, character data and a computer program, etc. The content of the software variety can be determined by a computer program and data for the program which has hitherto been offered on a floppy disk, by a television program which has hitherto been broadcast by an analog television system, by a film program which hitherto has been offered on videotape, and can be provided by a video disc which contains music data which have hitherto been offered via radio broadcast, as well as by a compact floppy disk and photo still image data, etc.

This means that this software playback device 2 is an information facility capable of working in conjunction with the variety of software offered in the common data format. The playback device 2 specifically includes functions for reading the multiple software to execute the computer program, play the movie program, play the television program (video and audio signals) and music data (audio signal reproduction), and also perform still picture reproduction. It should be noted that the video signal and the audio signal are related to one another in such a way that these signals are reproduced or output in a synchronized manner in the film and in television programs.

The following is the format of the CD-ROM 1 stored multiple software explained. With regard to the video and audio data, this means that frames are formed in succession, which thus form a software set. The video and audio data frames are then subjected to an analog-to-digital conversion before being stored in the CD-ROM 1 get saved. Subsequently, the data frames subjected to the analog-digital conversion are compressed in accordance with the standards of MPEG-2. MPEG-2 refers to the video data compression standards recommended by MPEG (Motion Picture Image Coding Experts Group), with the basic video format the CCIR601 standards (4: 2: 2 format) and HDVT (up to 1920 × 1080 Lines / picture). The data frames compressed in this way are encrypted using a specific encryption key. On the other hand, with regard to the computer program, the data is directly encrypted without undergoing compression processing based on MPEG-2, since the MPEG standards are related to video and voice signals. The data encrypted (and compressed) by such processing is written on the CD-ROM.

The data processed in this way, in or on the CD-ROM 1 are stored, are read by a control unit, not shown. The data frames read by this control unit, not shown, become a demodulation / control circuit 3 the software playback device 2 fed on the input side. The demodulation / control circuit 3 includes a function for demodulating the data frames supplied on the input side and transmits these data items to a decoder 4 ,

The decoder 4 performs error correction and bit rearrangement and transfers the data frames to an SD circuit 9 with a maximum speed of 2 megabytes / sec (on average 1 Megabytes / sec). The decoder 4 is for the transmission of data frames on a system bus 8th within the SD circuit 9 via an input / output (I / O) unit 6a connected.

An interface unit 17 is also about the I / O unit 6a on the system bus B within this SD circuit 9 connected. This interface unit 17 performs input / output processing between the SD circuit 9 and an operation keyboard formed on the outside of this software playback device 23 , a floppy disk drive unit 18 and a modem Ness 51 by. Then, the software data transmitted from a software vendor over a communication network is transmitted through this modem unit 51 and the interface unit 17 into the SD circuit 9 entered. The software delivered through the connection has the same format as that from the CD-ROM 1 was delivered; it is encrypted (and compressed) beforehand.

The SD (super-distribution) circuit is then explained 9 using the decoder 4 and the interface unit 17 connected is. The to the software playback device 2 A variety of software is distributed via an easily available medium, such as the CD-ROM mentioned above 1 and communication channels are distributed, which is why there is the problem of how a booking or billing system is structured in order to take a usage authorization into account when booking. The SD circuit 9 is used for this purpose. This means that the software playback device 2 usable variety of software is distributed in an encrypted state. The multitude of encrypted software is from the CD circuit 9 sequentially decrypted. Furthermore, the SD circuit subtracts 9 a booking count X in synchronism with the use of the software. This booking count X is defined as a point that is in the SD circuit 9 is registered in accordance with an amount of money that has previously been paid to a software owner (copyright owner) by the user.

The SD circuit 9 maintains a backup of the software by stopping the decoding process when this posting count X becomes zero.

It should be noted that this SD circuit 9 is updated in the form of an IC card, which is releasably in a card slot (eg a card slot corresponding to PCMCI1) of the software playback device 2 is introduced. Since the IC card shape is selected, the SD circuit can be 9 easy to transport. Accordingly, the user brings them to a software shop (software vendor) or the like, and the booking count X can be added in exchange for payment of an amount.

The SD circuit 9 consists of a control CPU 5 , a DES (Data Encryption Standard) facility 7 , a booking data storage 8th and input / output units 6a . 6b , which are connected to each other by bus or bus line B.

The control CPU or central unit 5 takes a division of labor with a host control CPU 14 in the software playback device 2 to control the transmission and recording of data between the decoder 4 , a demultiplexer 10 and the DES facility 7 in front. The control CPU also includes 5 a function to control the DES device 7 and the invoice or booking data storage 8th ,

The invoice or booking data storage 8th is a memory that stores the above-mentioned booking count X. It should be noted that the booking count X is in the booking data memory 8th is encrypted. It is therefore impossible for anyone other than the software holder to write or re-write the booking count X by using this booking data memory 8th is analyzed.

The DES facility 7 has a function to decrypt the decoder 4 video / audio data obtained here and a function for encrypting user data (a usage time and the number of times the software is used), which are generated during operation of the software. It should be noted that the software vendor over the communication network from the modem 51 is informed about the user data or that the user data is on the floppy disk 7 written or are, which are then collected by the software seller the next time the user pays costs. 3 schematically illustrates a configuration or structure of the DES device 7 , The DES facility 7 includes, as in 3 illustrates a DES execution unit 20 , in which a function to decrypt input data (ON) based on key data 21 and the delivery of this decrypted result in the form of delivery data (AUS) is included. According to this embodiment, the DES execution unit 20 an operating mode identification unit 22 on. This operating mode identification unit 22 has a function for selecting an optimal operating mode based on a data format, etc. from a plurality of DES operating modes and informs the DES execution unit 20 regarding the selected optimal operating mode. The key dates 21 are a key evaluation key, which the software vendor uses to communicate over the communication link when the software vendor has confirmed that the software user has received the cost of using the software. It should be noted that this DES facility 7 the use of an IC chip (called 46 DATA ENCRYPTION STANDARD NIST), as manufactured by the Phillips Publication Corporation.

Coming back on 2 it should be noted that the DES 7 decrypted data (video and audio data, etc.) frame to the demultiplexer 10 outside the SD circuit 9 via the I / O unit 6b be transmitted. The demultiplexer 10 demultiplexes the audio data frame, the video data frame and the computer program as well as the data for the program. The video data frame is then connected to an MPEG expansion circuit (MPEG-2) 11a delivered while the audio data frame to an MPEG stretching circuit (MPEG-2) 11b is delivered. The computer program and the data for the program are then sent to an MPEG expansion circuit (MPEG-2) 11c issued.

The MPEG Strain Circuits (MPEG-2) 11a . 11b are circuits for stretching the video or audio data frame, which is transmitted in the compressed state, on the basis of the MPEG standard, in order to restore the signal possible from the delivery of the picture or the speech. If the data frames through these MPEG stretching circuits (MPEG-2) 11a . 11b are stretched, takes a VRC circuit 12 synchronization of the output signals of the circuits 11a . 11b in front. This means that the MPEG expansion circuits (MPEG-2) 11a . 11b the stretched data frames deliver in synchronism with sync signals from the VRC circuit 12 be delivered. It should be noted that the MPEG stretch circuits 11 may include the use of an IC chip (ISO / IEC CD 13188'1-3).

The output signal from the MPEG stretching circuit (MPEG-2) 11a for video data is by means of a digital-analog (D / A) converter 13a converted into an analog signal. This analog signal is output to a television monitor unit, not shown, via an adder circuit 19 on the software playback device 2 connected. Furthermore, the output signal from the MPEG stretching circuit (MPEG-2) 11b for audio data using a digital-analog (D / A) converter 13b converted into an analog signal. This analog signal is sent directly to the software playback device 2 connected speakers, not shown. In contrast, the computer-oriented program and the data for the program arrive directly via the MPEG expansion circuit (MPEG-2) 11c and are sent to one with the software playback device 2 connected connected personal computer, not shown.

The MPEG expansion circuit (MPEG-2) 11a for video data, a frame stretch completion signal is emitted each time a stretching process of the individual compressed data frame has ended. This completion completion signal is provided by the host control CPU 14 the software playback device 2 recorded and then used to control the booking or booking creation. This means that the host control CPU 14 in the event that it receives this frame completion stretch signal, with a control CPU 5 cooperates, which is provided in the SD circuit and which on the bus line with respect to subtracting the booking count X, as it is in the booking data memory 8th is displayed with the CPU 14 connected is. The host control CPU 14 controls a delivery handicap when the booking count X is zero. It should be noted that the host control CPU 14 a processor for controlling the software playback device 2 as a whole as well as the booking.

The following is a detailed explanation regarding the special content of the booking process carried out by this host control CPU 14 and the control CPU 5 within the SD circuit 9 is executed on what 4 and 5 Reference is made.

4 illustrates function blocks of these two control CPUs in a diagram 14 and 5 , According to 4 is the host control CPU 14 from a frame counter block 29 for the inclusion of the MPEG expansion circuit 11a transmitted frame completeness expansion signal and a mode selection block 24 for recording an input signal (via the interface 17 , the input / output unit 6a and the bus line B) from an operating keyboard 33 built up on the outside of the software playback device 2 is provided. The host control CPU 14 is also from a show jumping control block 27 for receiving a signal from this mode selection block 24 , a normal playback operation control block 26 for the reception of signals from the mode selection block 24 and the jumping control block 27 and a stand transport operation control block 25 for receiving a signal from the mode selection block 24 built up. The host control CPU is also from a converter block 28 for the reception of signals from the control block 26 pertaining to the ordinary playback operation, the stand transport operation control block 25 and the frame counter block 29 and a handicap signal delivery block 30 for receiving a signal from the control CPU 5 the SD circuit 9 built up. In contrast is the control CPU 5 the SD circuit 9 from an image extraction block 33 for recording a signal from the decoder 4 , a DES decryption block 34 for recording a signal from the image extraction block 33 and a frame selection block 35 for receiving signals from the stand transport operation control block 25 as well as from the DES decryption block 34 built and gives these signals to the MPEG expansion circuit 11a from. The control CPU 5 is also from a subtracting block 31 For receiving a signal from the converter unit block 28 and a booking counter registration block 32 for picking up a signal from the subtracting block 31 constructed and outputs the signals to the handicap signal output block 30 and the subtractor block 31 from. The above functional blocks are described below.

The operating mode selection block 24 determines that a key from a series of keys, including a "renew key", a "stand transport key" and a "jump transport key", is pressed, which are the operation keys 23 form. The operating mode selection block 24 then takes a block from the jump mode control block according to the pressed or depressed key 27 , the normal playback operation control block 26 and the stand transport operation control block 25 in operation. It should be noted that the corresponding control blocks 25 . 26 and 27 on pressing or pressing a "stop button", the part of the operating buttons 23 is. The normal playback operation control block 26 control of the delivery of all leads to the SD circuit 9 frame transmitted sequentially at a certain interval. When the normal playback operation control block 26 is put into operation, a start-up indication signal is sent to the block converter 28 for the duration of actuation of the control block 26 fed on the input side. The jumping operation control block 27 the control leads to the intermittent operation of the normal playback operation control block 26 out. The stand transport operation control block 25 causes the control to select and deliver the to the SD circuit 9 given frame in accordance with a certain algorithm. In stand transport mode, the video data is displayed as a time-lapse image of the delivered images (jump search). If the stand transport operation control block 25 is set in operation, an operation display signal to the block converter 28 and the image or frame selection block 35 for the duration of actuation of the control unit 25 transfer.

On the other hand, when the normal playback operation control block 26 or the stand transport operation control block 25 are actuated or triggered, a CD-ROM drive, not shown, a demodulation / control circuit 3 and the decoder 4 put into operation (alternatively the data frame is operated via a modem 51 downloaded), which causes the data frame to the image extraction block 33 is transmitted there. The image extraction block 33 only extracts the video data frame from the transmitted data frame and transmits the extracted data frame to the DES decryption block 34 out.

This DES decryption block 34 operates the DES facility 7 and decrypts the transmitted video data frame. The one by the DES decryption block 34 decrypted video data frame is the frame selection block 35 fed on the input side.

The frame selection block 35 selects for the duration of receipt of the operation display signal from the stand transport operation control block 25 outputs some of the received video data frames or video data images in accordance with the specific algorithm and outputs them to the MPEG stretching circuit 11a from. As an algorithm for this video data frame selection, for example, algorithms for the selection of only one frame or image in which a specific indicator or flag is set, for the selection of a frame or image in an interval of a specific number of frames or images and for selection a frame or picture selectively used in a certain time interval. It should be noted that the frame or image selection block 35 all received video data frames or images to the MPEG stretching circuit 11a for the duration during which no operation display signal from the stand transport operation control block 25 is obtained.

The MPEG stretch circuit 11a for video data that accommodates the video data frame, causes a sequential expansion process with respect to the received video data frames. The MPEG stretch circuit 11a returns every time the circuit 11a completes the stretching process with respect to the individual frame, the video signal to the D / A converter 13a and transmits the frame completion stretch signal to the frame counter block 29 out.

The frame counter block 29 is a counter for incrementing a count n by 1 when the block 29 receives the frame completion stretch signal. The frame counter block 29 shows the converter block 28 this count n at all times. The frame counter block also clears 29 in the event that an erase signal from the converter unit block 28 is obtained, the counter value n and makes it 0.

The converter unit block 28 compares the count n over which the frame counter block 29 informs with a certain reference value for the duration of the reception of the operation display signal from the normal playback operation control block 26 or from the stationary transport control block 25 ago. This specific reference value is set to R (for example, R = 100,000,000) when the operation display signal from the normal playback operation control block 26 is obtained while set to 2R when the operation display signal from the stand transport operation control block 25 he will hold. Then there is the converter unit block 28 in the event that the count value n reaches the determined reference value, a booking unit subtraction command to the subtraction or subtraction block 35 from. The converter unit block 28 in particular gives a subtraction value "1" to the subtraction block 31 from. It should be noted that the converter unit block 28 in the event that the operation display signal is stopped, is stopped, or in the event that the booking block subtraction command is issued, the clear signal to the frame counter block 29 emits. A software usage amount detector is out of the MPEG stretching circuit for the video signal 11a , the frame counter block 29 and the converter unit block 28 built up.

The booking counter registration block 32 reads the booking count value X from the booking data memory 8th and shows this value to the subtracting block 31 on. The booking counter registration block 32 updates the booking count X of the booking data store at the same time 8th ,

The subtraction block 31 takes in the event that the booking block subtraction command from the converter unit block 28 there is a decrease in the booking count value X by 1, via which the booking counter registration block 32 provides an ad. Subsequently, the subtracting block 31 shows the booking counter registration block 32 this new reduced booking count X (X = X - 1). The booking counter registration block 32 overwrites the new booking count value X (X = X - 1) over which the subtraction block 31 has delivered an advertisement in the booking data store 8th ,

The booking counter registration block 32 determines whether the booking count X that is in the booking data store 8th is described, 0 becomes (unusable value) or not. Then, in the event that the posting count X becomes 0, the posting counter registration block shows 32 the delivery handicap signal output block 30 this effect. It should be noted that the booking counter block 32 in the event that the booking count X is in the booking data memory 8th is rewritten by the software vendor from "0" to "1" or a higher value, the delivery obstruction signal output block 30 indicates this effect. The subtraction block 31 and the booking counter registration block 32 are combined to form a determination device.

The delivery handicap signal output block 30 in the event that an indication is received that the booking count X = 0, from the booking count registration block 32 , a video disability signal.

In addition, the video obstruction signal delivery block gives 30 in the event that he receives an indication that the booking count X is greater than 0 from the booking counter registration block 32 , a reset signal.

With reference to the in 5 and 6 Flowcharts shown will now be one by the control CPUs described above 5 . 14 executed workflow are explained.

5 illustrates in a flowchart the flow of the booking process as it is by the host control CPU 14 the software playback device 2 is performed. This process begins by determining that one of the operation buttons 23 representative keys, namely the "play key", the "stand transport key" and the "jump transport key" is pressed. At the initial step S101, the host control CPU determines 14 that an image display operation is to be performed based on a type of the key pressed. This means that when the "play key" or the "jump transport key" is pressed, the host control CPU 14 this is determined as a "normal playback operation".

In contrast, the host control CPU determines 14 then when the "stand transport button" is pressed, this as a "stand transport operation". The subsequent processes vary depending on the particular playback modes.

In the case of the "stand transport operation", the frame completion stretch signal is output from the MPEG stretch circuit at step S102 11a determined. When the frame completion stretch signal in question is determined, the processing proceeds to step S103, at which the count n of the frame counter unit 120 is incremented by 1.

At subsequent step S104, the CPU determines 14 whether the count value n reaches a reference value 2R (eg 2R = 200,000,000) or not. Then, if the count value n does not reach the reference value 2R, the CPU becomes step S105 14 determine whether the booking process has ended or not. This determination is made on the basis of whether the operation display signal from the stand transportation operation control operation 25 has been received or not. This means that in the event that the operation indication signal has not been received, the processing proceeds to step S116 by determining that the booking process is to be ended. On the other hand, if the operation display signal is received, the processing goes to step S101. by determining that the booking process continues is clogged.

On the other hand, when it is determined that the count value n reaches the reference value 2R at step S104, the processing proceeds to step S106. At step S106, the booking block subtraction command is sent to the control CPU 5 the SD circuit 9 issued.

At subsequent step S107, the count n of the frame counter block 29 deleted to 0.

At subsequent step S108, the CPU determines 14 in the same manner as in step S105 whether the booking control process is finished or not. If it is determined that the booking control process is continuing, then processing returns to step S102. In contrast, processing proceeds to step S116 when it is determined that the booking control process is to be ended.

In contrast, in the case of "normal playback operation", the frame completion stretch signal from the MPEG stretch circuit 11a at the step 109 determined. If the frame completion stretch signal is determined, processing continues to block S110, according to which the count n of the frame counter block 29 is counted up by 1. The CPU then determines 14 at step S111, whether or not the count value n reaches a reference value R (for example, R = 100,000,000). If the count value n does not yet reach the reference value R, the CPU determines 14 then at step S112 whether the booking process has ended or not. This determination is made based on whether the operation display signal from the normal playback operation control block 26 has been received or not. This means that in the event that the operation indication signal has not been received, the processing proceeds to step S116, where it is determined that the booking process is to be ended. On the other hand, if the operation indication signal is received, the processing goes back to step S109 by determining that the booking process is to be continued.

On the other hand, when it is determined that the count value n reaches the reference value R at step S111, the processing proceeds to step S113. At step S113, the booking block subtraction command is sent to the control CPU 5 the SD circuit 9 issued.

In the following step S114, the count value n of the frame or frame counter block 29 deleted to "0".

At subsequent step S115, the CPU determines 14 in the same manner as in step S112 whether the booking control process is ended or not. If it is determined that the booking control process is continuing, then processing goes back to step S109. In contrast, if it is determined that the booking control process is to be ended, the processing proceeds to step S116.

In any case, at step S116, the count n of the frame counter block 29 deleted and made "0".

The CPU then waits 14 on the dispense handicap command issued by the control CPU 5 the SD circuit 9 is released at step S117. Then, if the issuing obstruction command is issued from the subject device, the video obstruction signal is issued at step S118. After the above process, this booking process is ended.

6 illustrates in a flowchart a sequence of a booking process, such as that of the control CPU 5 the SD circuit 9 is performed.

This process begins when the CD circuit 9 including IC card in the software playback device 2 is inserted or inserted. Then, in the initial step S201, the control CPU 5 carry out the authorization. This authorization implies checking the control CPUs 14 . 5 if the SD circuit 9 is set.

The control CPU then checks 5 whether the booking block subtraction command from the host control CPU 14 has been received or not at step S202. If no booking block subtraction block has been received, the check at step S202 is repeated.

On the other hand, if the booking unit subtraction command has been received, the booking count X becomes from the booking data memory in step S203 8th read. Then a "1" is subtracted from this booking count X, and the read subtracted value (X-1) is set as the new booking count X.

At the subsequent step S204, the CPU sets 5 determines whether the new booking count X is 0 or less. If the new booking count X is greater than 0, processing proceeds to step S206. At step S206, the new booking count X is stored in the booking data memory 8th written. Processing then goes back to step S202. If against it the booking count X is 0 or less, the delivery prohibition command to the host control CPU becomes step S205 14 issued. Then this processing is ended.

It should be noted that a repeated execution of the in 6 illustrated processing entails operation such that the SD circuit 9 briefly from the software playback device 2 it is removed that the software seller stores the booking count in the booking data memory 8th in exchange for a payment of the fee to use the software and the SD circuit 9 again in the software playback device 2 is to be installed.

Coming back on 2 a configuration of the delivery obstruction device for performing incomplete delivery by superimposing image patterns on the video signal displayed on the television monitor is explained in accordance with the delivery obstruction signal output from the host control CPU 14 is delivered.

The output disable signal from the host control CPU 14 becomes a pattern generator 16 and a sequence control device 15 fed on the input side. The sequence control device 15 emits a signal which is switched on / off in a specific time sequence with which the video impairment signal is received. This means that the sequencer 15 , as in

7 (c) illustrates the output signal turns off before receiving the video handicap signal, however, after receiving the relevant video handicap signal, the output signal turns on / off several times. Then the sequence control device sets 15 the output of the switched-on output signal continues. The output signal of the sequence control device 15 becomes the pattern generator 16 fed on the input side.

The pattern generator 16 generates image pattern data for display of the character data in the event that it receives the delivery obstruction signal to draw attention to the software user that, for example, the "booking count = 0". The pattern generator 16 outputs the image pattern data thus generated only when the output signal of the sequence control device 15 is switched on. The one from this pattern generator 16 Output image pattern data are the adder circuit 19 fed on the input side.

The adder circuit 19 overlays that from the pattern generator 16 emitted image pattern signal one of the digital / analog converter 13a for the video signal output analog video signal and outputs the superimposed signals to the television monitor unit. If that's from the pattern generator 16 transmitted or output image pattern signal is turned off, accordingly, that of the digital / analog converter 13a output analog video signal as it is. In contrast, when the image pattern signal is switched on, such a video signal is emitted in which the image pattern is superimposed on the analog video signal which is generated by the digital / analog converter 13a is delivered. It should be noted that this adder circuit 19 only on the output side of the video-oriented digital / analog converter 13a is provided. Accordingly, even in the case that the host control CPU 14 outputs the delivery disabling signal, delivers the analog audio signal, the computer program and the data for the program (hereinafter referred to as "PC signal") normally as before.

It should be noted that the sequencer 15 and the pattern generator 16 stop signaling when a reset signal from the host control CPU 14 is delivered.

in the the operation of the embodiment will now be explained.

Now it is assumed that part of the operating buttons 23 forming "play button" is pressed. Then the audio and video data frames that are related to each other such that these frames are output in synchronism with each other are sent to the SD circuit 9 from the CD-ROM 1 transfer. These audio and video data frames are created by the DES device or circuit 7 decrypted.

The SD circuit 9 passes all decrypted audio and video data frames to the demultiplexer one after the other 10 on the input side. The one through the demultiplexer 10 Video frames are demultiplexed into the MPEG stretching circuit 11a for video data supplied on the input side, while the audio data frame of the MPEG expansion circuit 11b for video data is supplied on the input side. Each of the MPEG stretching circuits 11a . 11b stretches the received frames in sequential order and passes the stretched frames to the digital-to-analog converters 13a . 13b from.

Every time the MPEG stretch circuit 11a for video data has completely stretched the individual video data frame, the frame completion stretch signal becomes the host control CPU 14 fed on the input side. This host control CPU 14 counts the number of frames completeness stretch signal recordings and causes the CPU 5 in the SD circuit 9 , the Bu count X in the invoice data memory 8th to decrease or decrement each time when this count value n reaches the determined reference value R.

Consequently will be in agreement with this embodiment a charge imposed on the number of frames submitted even in the event that the user has any area of a movie image, or even in the event that the user repeats the same area of a film image (e.g. a film) considered. If the picture is stopped, it will go beyond no new frame is given, and therefore no burden is imposed. Thus, no nonsensical situation is created, as with conventional accounting procedures can be seen; much more an appropriate charge is imposed. As a result, there is none Need for it existing, non-collectable charges for the use of the charge for one use add up beforehand, thus reducing the usage burden to a relatively low level Amount of money can be brought.

It should be noted that in the event that part of the operation buttons 23 representing "stand transport button" is pressed, the SD circuit 9 to the demultiplexer 10 only the video data frames that are selected in a Spring Art, based on the particular algorithm, and the corresponding audio data frames.

That through the demultiplexer 10 A demultiplexed video data frame becomes the MPEG stretch circuit 11a for video data supplied on the input side, while the audio data frame of the MPEG expansion circuit 11b for audio data are fed in on the input side. If the MPEG stretch circuit 11a for video data completes the expansion process on the individual video data frame, a frame expansion completion signal is sent to the host control CPU 14 issued. In this case, the host control CPU initiates 14 but not the CPU 5 in the SD circuit 9 to decrement the booking count value X in the booking data storage unit until the count value n of the number of recordings of the frame expansion completion signals reaches a value which is twice the reference value R. This means that the booking count X is decremented each time the count n reaches 2R.

Even then if the same number of frames within the same period of time is delivered the load imposed during step mode is generally half of the Load imposed during normal playback. Consequently is generally a part related to the case of normal playback switched off or prevented, and on the other hand, a charge for the delivery of the Data are also imposed. Accordingly, a fair profit sharing between the software holder and the user.

As a result of decrementing the booking count X in this way, the booking count X becomes 0. In this case, the signal state in each unit is as shown in FIG 7 is illustrated. In 7 (g) illustrates that the booking count X becomes 0 at time "A".

After the DES device decrypts the data even in the case that the booking count X has become 0, the analog / digital A / D converter sets 13a for video data, the delivery of the normal analog video signal continues after the time "A" (see 7 (a) ).

Then the host control CPU gives 14 in the event that the booking count X becomes 0 at time "A", the pulse-like output obstruction signal (see 7 (b) ).

Thereupon the sequence control device gives 15 the signal, which is alternately repeatedly switched to ON / OFF states with a fixed period of time because the output obstruction signal is picked up. After this fixed period of time has elapsed, a continuous output signal output is kept in the ON state (see 7 (c) ).

The pattern generator 16 takes on the input side the delivery obstruction signal (b) and the output signal of the sequence control device 15 and then outputs the character pattern data (a video signal for displaying a character "booking count = 0") only at a time when the output signal of this sequencer 15 is switched on. The time course at which the pattern generator 16 that returns character pattern data is in 7 (c) illustrated.

The adder circuit 19 for the superimposition of the video signal (a) and the character pattern data (c), the normal video signal (a) outputs on the output side, as long as a booking count value X (g) is greater than 0. During a fixed period of time from the time "A" in in the event that the booking count X (g) becomes 0, the output signal for superimposing the character pattern on the image and the normal image output signal are repeatedly passed alternately (see 7 (d) ).

It should be noted that an audio signal (e) and a PC signal (f) are normally before and after the time "A" continue to be submitted.

Accordingly, after the time "A", in the case that the booking count becomes 0, such an output inhibition signal is brought about that the character pattern is only made with respect to the image signal from the three output signals (image signal, voice signal and PC signal) is superimposed. Therefore, the software user who views the television monitor (not shown) will not misunderstand the occurrence of a failure or error in the device, but rather will be able to recognize that the booking count becomes 0. At this point, the audio signal and the PC signal are normally passed on as they are. If the software is mainly based on the image (e.g. a film, an animation, etc.), the profit or benefit of the software owner is not violated. Rather, as can be seen, this produces such an effect that the desire for continued use by the software user is increased. As a result, the software user will be willing to pay the fee to the software vendor for compensation for adding the booking count X after or by removing the SD circuit 9 from the software playback device 2 to be paid.

in the The structure of the second embodiment is explained below.

8th illustrates in a block diagram the structure of the software playback device used in the second embodiment of the present invention.

This embodiment has such a structure in the same manner as the first embodiment on that the Number of operations of stretching the compressed video data frame is counted on the basis of the MPEG standards and that the booking count X in accordance is reduced with the number of these operations. The output disable signal also closes in the event that the Booking count X becomes 0, the use of such a structure that the image signal and the PC signal completely to be stopped while the normal audio signal continues to be output.

The format of the to the software playback device 2 Software released in this embodiment is absolutely the same as that in the first embodiment. Furthermore, the same components of the software playback device 2 in this embodiment like those in the first embodiment with the same reference numerals as there. Explanation of these common elements will be omitted below, while only explaining the configuration of a delivery obstruction device in accordance with the delivery obstruction signal output from the host control CPU 14 is delivered or transferred.

The output disable signal from the host control CPU 14 forth the input side of a register 40 fed. The registry 40 outputs a logic value L in an initial state and then continues to output a logic value H when an increase in the output impedance signal supplied on the input side is determined.

An output signal from the register 40 is through an inverter 41 inverted. With that the inverter gives 41 the logic value H in the initial state, but continues to output the logic value L after the output disabling signal has been output.

An output signal from the inverter 41 becomes an input terminal of an AND circuit 42 supplied for video data. The other input terminal of this AND circuit 42 for video data is with an output terminal of the MPEG stretching circuit 11a connected for video data (MPEG-2). Accordingly, this AND circuit serves 42 for video data as a gate or key circuit for the video signal, this to the digital / analog converter 13a for video data from the MPEG stretch circuit 11a for video data to be fed in on the input side. For this reason, the video signal can only be forwarded if the output signal of the inverter 41 takes the logic value H, whereupon the analog video signal from the digital / analog converter 13a for video data is delivered to a television monitor device, not shown. If the output signal of the inverter 41 assumes the linkage value L, the forwarding of the video signal is prevented or blocked, and thus no analog video signal from the digital / analog converter 13a submitted for video data.

The output signal of the inverter 41 also becomes an input terminal of an AND circuit 43 fed for a PC signal. The other input terminal of the AND circuit 43 for the PC signal is with an output terminal of the MPEG expansion circuit 11c connected for the PC signal (MPEG-2). Accordingly, this AND circuit serves 43 for the PC signal as a gate or push-button circuit for the PC signal by allowing this PC signal to be forwarded only when the output signal of the inverter 41 takes the logic or logic value H, but blocks the forwarding of the PC signal in the event that the output signal of the inverter 41 shows the link value L.

It should be noted that the and push-button serving AND circuit not at the output terminal of the MPEG expansion circuit 11b is provided for audio data. Thus, even in the event that the output obstruction signal is output from the host control CPU-14, the analog audio signal from the digital-to-analog converter 13b for audio data as previously delivered normally.

Incidentally, the register gives 40 the logic value L when the reset signal from the host control CPU 14 is delivered or transferred.

below the operation of the considered embodiment is explained.

The software playback device 2 this embodiment operates in the same manner as the first embodiment until the host control CPU 14 outputs the output handicap signal. Therefore, only the operation after the output control signal is output by the host control CPU will be described below 14 are explained.

If the in the booking data storage 8th stored booking count X becomes 0, as a result of the decrementation, the signal status in each unit is as shown in FIG 9 is illustrated. 9 shows that the booking count X becomes 0 at a time "B" (see 9 (b) ).

The DES facility 7 decrypts the data even after the booking count X has become 0, which is why the normal video signal continues from the MPEG stretching circuit 11a for video data after the time "B" (see 9 (a) ).

The host control CPU 14 then, when the booking count X becomes 0 at time "B", outputs the pulse-like output obstruction signal (see 9 (b) ).

The registry 40 , which gives the link value L before the time "B", gives the link value H after the time B, synchronization being carried out with an increase in the received output impedance signal.

Accordingly, the inverter gives 41 which is the output signal of the register 40 records the logic value H before the time "B", but the logic value L after the time "B" (see 9 (c) ).

The AND circuit 42 for video data that the forwarding of the image signal in accordance with the output signal of the inverter 41 allows or blocks, a normal video signal "A" before such a time "B" if a booking count X (g) is greater than 0. The AND circuit 42 then blocks the delivery of the video signal after the time "B" when the booking count X (g) becomes 0 (see 9 (d) ).

The AND circuit outputs in a corresponding manner 43 for the PC signal, which is a forwarding of the PC signal in accordance with the output signal of the inverter 41 allows or blocks the PC signal to the outside of the facility 2 before time "B" if the booking count X (g) is greater than 0 while it is delivering the PC signal to the outside of the facility 2 after time "B" locks when the booking count X (g) becomes 0 (see 9 (f) ).

It should be noted that the audio signal continues to be output normally before and after time "B" (see 9 (e) ).

Accordingly, after the time "B", in the case that the booking count becomes 0, such a delivery hindrance is caused that the delivery to the outside of the software player 2 solely based on the image signal and the PC signal among the three output signals (image signal, voice signal and PC signal) is prevented. At this point, however, the audio signal remains for normal forwarding. Therefore, the software user is able to recognize that the booking count X has become 0 without developing a misconception that there is a malfunction in the facility 2 occured.

As described above in connection with this embodiment, the PC signal is passed on to the outside of the software playback device 2 prevented, which is why it is possible to prevent illegal use of the computer program. It should be noted that the audio signal continues to be output normally, but that the profit or profit of the software beneficiary is not violated if the software on the image (eg a film, environmental or environmental video, etc.) does not violate is. Rather, as can be seen, this produces such an effect that the desire for continued use by the software user is increased. As a result, the software user is ready to charge the usage fee to the software beneficiary as compensation for adding the booking count X by removing the SD circuit 9 from the software playback device 2 to be paid.

below becomes the structure of the third embodiment explained.

10 illustrated in a block slide The structure of the software playback device used in the third embodiment of the present invention.

The only difference between this embodiment and the second embodiment is that an audio signal obstruction circuit 50 that the from the register 40 outputs the signal emitted between the MPEG stretching circuit 11b for audio data and the digital / analog converter 13b for audio data is connected. Accordingly, only added configurations compared to the second embodiment will be explained here, while the remaining explanations are omitted.

11 illustrates a detailed structure of the audio signal obstruction circuit 50 , How out 11 can be seen, the output signal of the MPEG expansion circuit 11b for audio data an input terminal "b" of a multiplexer 501 fed on the input side. An output signal of a mute signal generating circuit 500 becomes an input terminal "a" of this multiplexer 501 fed on the input side. In contrast, an output signal of the register 40 as a counter start signal a first counter 502 and a second counter as a reset signal 506 supplied on the input side and also a first control connection of the multiplexer 501 via an AND gate 509 fed. A counter value signal of the first counter 502 becomes a memory access circuit 503 fed on the input side. Furthermore, a pulse output signal of the first counter 502 a timer 507 and the second counter 506 fed on the input side. An output signal of the memory access circuit 503 becomes a code memory 504 fed on the input side. An output signal from this code memory 504 becomes a speech signal generating circuit 505 fed on the input side. An output signal of this speech signal generating circuit 505 becomes an input terminal "c" of the multiplexer 501 fed on the input side. An output signal of the timer 507 is by means of an inverter 508 inverted and the other input terminal of the AND gate 509 fed. An output signal from the second counter 506 becomes a second control connection of the multiplexer 501 fed on the input side.

The first counter 502 starts recording the start signal by counting up within a fixed period of time and gives its count to the memory access circuit 503 from. This memory access circuit 503 serves to store the code 504 to access according to the counter value that the first counter 502 indicates. The first counter then works 502 as the address counter of the code memory 504 , The first counter 502 gives a single pulse to the timer when its count reaches the maximum value 507 and the second counter 506 and stops counting up. The first counter 502 resumes counting up when the count is on an erase signal from the timer 507 is reset to a minimum value.

The code memory 504 stores language codes corresponding to individual languages (vowels, consonants, etc.), which form a language entity to be delivered, such as an alarm if the software usage quantity exceeds a usage limit in a generation or reproduction sequence. Accordingly, every time the first counter 502 counts up to the code memory 504 via the memory access circuit 503 accessed, and the language codes corresponding to the alarm voice entity are output in succession. The content of the language sections is, for example, "The amount of use has reached the limit. Follow the procedures again and please use the system. The image is not output." This means that the corresponding language codes are stored in successive addresses in the code memory 504 are arranged sequentially to compile the sentences or sentences. One from the code memory 504 Output speech code string is sent to the speech signal generating circuit 505 issued.

The speech signal generation circuit 505 is a commercially available voice IC chip; it outputs a digital speech signal corresponding to the entered speech code string. Thus, the voice signal generation circuit gives 505 in the event that a voice code string corresponding to the alarm voice entity is supplied on the input side, the digital voice signal corresponding to the alarm voice entity is fed to the input terminal "c" of the multiplexer 501 from.

The timer 507 gives a signal with the logic value L to the inverter 508 during a normal state. The timer 507 gives on the impulse of the first counter 502 then the linkage value H during a fixed period of time of, for example, about 10 to 20 seconds. After this fixed period of time has elapsed, the inverter is then sent to the inverter 508 output logic value set to L, and the clear signal is sent to the first counter 502 issued. The first counter 502 leads up again to deliver the alarm voice entity from the voice signal generating circuit 505 in response to this delete signal.

The inverter 508 inverts that of the timer 507 output logic value and gives the inverted logic value to the input terminal of the AND gate 509 from. Accordingly ver starts the inverter 508 the AND gate 509 , the output signal of the register 40 directly to the multiplexer 501 to be supplied only when the output signal of the timing element 507 takes the link value L, while the link value L the multiplexer 501 regardless of the initial state of the register 40 is then supplied when the output signal of the timer 507 assumes the logic value H from the timing element.

The second counter 506 always gives the logic value L to the multiplexer 501 when the output signal of the register 40 takes the linkage value L. This second counter 506 is when the output signal of the register 40 assumes the logic value H, reset and countable. If the second counter 506 countable, it counts the pulse it receives from the first counter each time 502 receives. When this count reaches "5", the second counter gives 506 the link value H to the multiplexer 501 from.

The mute signal generation circuit 500 is a circuit that delivers a fixed voltage.

The multiplexer 501 outputs a signal received via one of the input connections "a" to "c" to the digital / analog converter 13b for audio data, which is from the AND gate 509 forth recorded signal and that from the second counter 506 signal received here serve as control signals. This means that the multiplexer 501 the audio signal of the MPEG stretching circuit 11b for audio data that is received via the input terminal "b" when the output signal of the AND gate 509 assumes the L level and the output signal of the second counter 506 shows or assumes the L level. The multiplexer 501 outputs the digital output speech signal to the speech signal generating circuit 505 from which has been received via the input terminal "c" when the output signal of the AND gate 509 assumes the H level and the output signal of the second counter 506 shows the L level. The multiplexer 501 gives the fixed voltage of the mute signal generating circuit 500 , which has been received via the input terminal "a", then decreases when the output signal of the second counter 506 shows the H level.

in the The following is the operation of the embodiment under consideration explained.

The software playback device 2 in this embodiment operates in the same manner as in the first embodiment until the host control CPU 14 outputs the output handicap signal. The software playback device also works 2 in this embodiment in the same manner as in the second embodiment in terms of the image signal and the PC signal after the host control CPU 14 has issued the exit handicap signal. Accordingly, only the operation related to the audio signal will be described.

As explained above, the register sets 40 the signal output with the logic value L before the output control signal from the host control CPU is received 14 continued. This logic value L becomes the first counter 502 , the AND gate 509 and the second counter 506 fed on the input side. Accordingly, the first counter begins 502 not counting up, which is why there is no impulse to the timer 507 is fed on the input side. For this reason, the AND gate 509 brought into an open state, with which the logic value L output by the register connects the first control connection of the multiplexer 501 is fed on the input side. The second counter 506 sets the output of the logic value L to the second control connection of the multiplexer 501 continued. Accordingly, the multiplexer gives 501 the audio signal of the MPEG stretching circuit 11b for audio data from the digital / analog converter via the input connection "b" 13b for audio data are fed in on the input side. As a result, announcements and sounds corresponding to the software are reproduced by the loudspeaker.

The registry 40 relies on receiving the output disable signal from the host control CPU 14 the output of the logic value H continues. This logic value H becomes the first counter 502 , the AND gate 509 and the second counter 506 fed on the input side. The first counter 502 begins counting up within the fixed period of time and sequentially counts to the memory access circuit 503 leave. The memory access circuit 503 takes access to the code memory 504 in accordance with this count value and reads out the language code string corresponding to the alarm voice entity. The speech signal generation circuit 505 , which is fed this voice code string on the input side, generates the digital alarm voice signal and emits this signal to the input terminal "b" of the multiplexer. Before the count of the first counter 502 the first counter gives the maximum value 502 no output pulses to the timer 507 and the second counter 506 from. The AND gate thus remains open before the count of the first counter 502 reached the maximum value. Accordingly, that of the register 40 given logic value H the first control terminal of the multiplexer 501 fed on the input side. It should be noted that the reset signal shows the logic value H and that the second counter 506 thereby reset and thus in the count brought into a state. At this time, however, the count is less than "5" and thus remains the second control port of the multiplexer 501 from the second counter 506 logic value supplied at L. Thus, the multiplexer gives 501 the digital speech signal of the speech signal generating circuit 505 which, via the input connection "c", the digital / analog converter 13b for audio data is fed in on the input side. As a result, alarm announcements are made from the speaker, not shown.

The alarm announcements are counted up by the first counter 502 issued. If the count of the first counter 502 the first counter gives the maximum value 502 the pulse to the timer 507 and the second counter 506 from. The timer 507 , which picks up the pulse, gives the logic value H to the inverter 508 only for 10 to 20 sec. Therefore the AND gate closes 509 only for 10-20 sec and gives the logic value L to the first control connection of the multiplexer 501 on the input side. It should be noted that the second counter 506 increases by 1 by receiving the pulse. At this time, however, the counter value is lower than "5", which is why it is connected to the second control terminal of the multiplexer 501 from the second counter 506 given link value at L remains. Hence the multiplexer gives 501 to the digital / analog converter 13b for audio data the audio signal of the MPEG expansion circuit 11b for the audio signal, which is supplied via the input connection "b", only for 10-20 seconds. As a result, the software-based announcements or languages and sounds from the speaker, not shown, are only emitted for 10-20 seconds.

After 20 seconds have elapsed since the input pulse was input, the timer gives 507 the clear signal to the first counter 502 and the link value L to the inverter 508 off to the AND gate 509 to open. So the first counter leads 502 again counting up from the minimum value and the speech signal generating circuit 505 again outputs the digital alarm voice signal to the input port "c" of the multiplexer 501 from. There is also the AND gate 509 the logic value H to the first control connection of the multiplexer 501 from. That is why the multiplexer gives 501 again the digital speech signal of the speech signal generating circuit 505 , which has been supplied via the input terminal "c", to the digital / analog converter 13b for the audio signal. As a result, the alarm announcements are output from the speaker, not shown.

In the manner described above, corresponding software announcements and speeches and tones are given alternately to the software. If the alarm announcements have been repeated five times, the count of the second counter is reached 506 to "5", and that of the second control terminal of the multiplexer 501 from the second counter 506 Link value supplied here shows the H level. So the multiplexer gives 501 always a low voltage of the mute signal generating circuit 500 from the via the input connection "a" the language-oriented Digi tal / analog converter 13b irrespective of the logic value that is supplied to the first control connection from the AND gate 501 from the input side. The one from the second control port from the second counter 506 The logic value supplied on the input side remains at the H level, provided the output signal from the register does not assume the L level. Consequently, the announcements or utterances and sounds are no longer emitted by the loudspeaker, not shown.

It should be noted that the output signal of the mute signal generating circuit 500 can be a signal of a fixed audible frequency, for example an audio signal of 1000 Hz.

As explained above in connection with this embodiment, in addition to the image signal and the PC signal, the output of the audio signal after the alarm is stopped completely for a fixed period of time. However, it can be taken into account that the desire of the software user for continued use is promoted by the speech output, which is provided intermittently at alarm intervals. As a result, the software user is ready to charge the use to the software beneficiary as compensation for adding the booking count X by taking out the SD circuit 9 from the software playback device 9 to settle.

in the The structure of the fourth embodiment will now be explained.

12 illustrates in a block diagram the structure of the software playback device used in a fourth embodiment of the present invention.

This embodiment, in the same manner as the first embodiment, has such a construction that the number of operations of stretching the video data frame compressed according to the MPEG standards is counted, and the booking count X is subtracted according to the number of operations involved becomes. This embodiment also has such a structure that the audio signal and the PC signal are completely stopped as the output restriction, while the normal image signal is output when the booking count X becomes 0.

According to this embodiment, the format is to the software playback device 2 software delivered is absolutely the same as in the first embodiment. Furthermore, the same components of the software playback device 2 in this embodiment denoted by the same reference numerals as those in the first embodiment. Explanation of these common elements will be omitted below, while only a configuration of a dispenser prohibiting device in accordance with the dispensing prohibitive signal output from the host control CPU will be explained 14 is delivered.

The output inhibit signal from the host control CPU 14 becomes the register 40 fed on the input side. This register 40 outputs the link value L in the initial state, but then continues to output the link value H when an increase in the input-side disabling signal is detected.

An output signal from the register 40 is by means of an inverter 41 inverted. With that the inverter gives 41 in the initial state, the link value H from, but continues the delivery of the link value L after delivery of the delivery obstruction signal.

An output signal from the inverter 41 becomes the input terminal of an AND circuit 44 supplied for audio data. The other input terminal of this AND circuit 44 for audio data is with an output terminal of the MPEG stretch circuit 11b for audio data (MPEG-2) connected. Accordingly, the AND circuit serves 44 for audio data as a gate or key switch for the speech signal, which the D / A converter 13b for audio data from the MPEG stretch circuit 11b for audio data is fed in on the input side.

For this reason, the voice signal can only be forwarded if the output signal of the inverter 41 has the logic value H, and this becomes the D / A converter 13b Analog voice signal output for audio data is output to the loudspeaker, not shown. If the output signal of the inverter 41 has the logic value L, the forwarding of the voice signal is prevented, and thus no analog voice signal from the D / A converter 13b submitted for audio data.

The output signal of the inverter 41 also becomes the input terminal of the AND circuit 43 supplied for the PC signal. The other input terminal of the AND circuit 43 for the PC signal is with the output terminal of the MPEG expansion circuit 11c connected for the PC signal (MPEG-2). Accordingly, this AND circuit allows 43 for the PC signal, which serves as a gate or key circuit for the PC signal, the forwarding of the PC signal only when the output signal of the inverter 41 has the logic value H, while the forwarding of the relevant PC signal is prevented or blocked in the case that the output signal of the inverter 41 has the linkage value L.

It should be noted that an AND circuit, which serves as a gate or key circuit, at the output terminal of the MPEG expansion circuit 11a is not intended for video data. Thus, even in the event that the output inhibit signal from the host control CPU 14 is output, the analog video signal from the D / A converter 13a for video data as previously delivered normally.

Incidentally, the register gives 40 the logic value L when the reset signal from the host control CPU 14 is transmitted.

in the the operation of the embodiment will now be explained.

The software playback device 2 according to this embodiment operates in the same manner as that in the first embodiment until the host control CPU 14 emits the delivery disability signal. Accordingly, only the operation after the host control CPU will be explained here 14 has issued the delivery disability signal.

If the in the booking data store 8th stored booking count X becomes 0 as a result of decrementing, the signal state in each unit is as shown in FIG 13 is illustrated. 13 shows that the booking count X becomes 0 at a time "C" (see 13 (g) ).

The DES facility 7 decrypts the data even after the booking count X has become 0, which is why the normal audio signal continues from the MPEG stretching circuit 11b for audio data after the time "C" (see 13 (a) ).

Then the host control CPU gives 14 the pulse-like delivery obstruction signal when the booking count X becomes 0 at time "C" (see 13 (b) ).

The registry 40 , which gives the link value L before the time "C", delivers the time "C" the logic value H, which is synchronized with an increase in the received disabling signal.

Accordingly, the inverter gives 41 which is the output signal of the register 40 records the logic value H before the time "C" and the logic value L after the time "C" (see 13 (c) ).

The AND circuit 44 for audio data that the forwarding of the speech signal in accordance with the output signal of the inverter 41 Allows or blocks a normal audio signal before time "C" if the booking count X (g) is greater than 0. The AND circuit 44 on the other hand blocks the output of the audio signal after the time "C" when the booking count X (g) becomes 0 (see 13 (e) ).

The AND circuit outputs in a corresponding manner 43 for the PC signal, which is the forwarding of the PC signal in accordance with the output signal of the inverter 41 Allows or disables the PC output signal to the outside of the device 2 before time "C" if the booking count X (g) is greater than 0 while it is delivering the PC output signal to the outside of the facility 2 after the time "C" locks or prevents when the booking count X (g) becomes 0 (see 13 (f) ).

It should be noted that the image signal normally continues to be emitted before and after the time "C" (see 13 (d) ).

Accordingly, after the time "C", in the case that the booking count becomes 0, such a delivery handicap is caused that the delivery to the outside of the software player 2 only with respect to the audio signal and PC signal among the three output signals (image signal, voice signal and PC signal) is hindered or blocked. At this point, however, the normal forwarding of the image signal is retained. Therefore, the knowledgeable software user is able to recognize that the booking count X becomes 0 without a misinterpretation that there is a malfunction in the facility 2 is present.

As described above, according to this embodiment, the forwarding of the PC signal to the outside of the software playback device 2 blocked, which is why it is possible to prevent illegal use of the computer program. It should be noted that the normal delivery of the image signal continues, but that the profit of the software owner is not hurt if the software is based on speech or sound (e.g. a video of a classical concert, a karaoke video, a language course - Video, etc.). Rather, what can be considered is such an effect that the desire for continued use by the software user is increased. As a result, the software user is ready to charge the usage fee to the software beneficiary as compensation for adding the booking count X by removing the SD circuit 9 from the software playback device 2 to be paid.

below becomes the structure of the fifth embodiment explained.

14 Fig. 3 is a block diagram showing the structure of the software playback device used in the fifth embodiment of the present invention.

This embodiment has such a structure in the same manner as the first embodiment on that the Number of operations stretching the video data frame compressed based on the MPEG standards counted and the booking count in accordance is subtracted with the number of operations involved. This embodiment also has such a structure that light and dark of the image signal during the output of the normal audio signal and PC output signal as Tax disability be inverted when the booking count becomes 0.

According to this embodiment, the format is to the software playback device 2 software delivered is absolutely the same as in the first embodiment. Furthermore, the same components of the software playback device 2 in this embodiment, identified by the same reference numerals as those components in the first embodiment. Explanation of these common elements will be omitted below, whereas only a configuration of a delivery obstruction device in accordance with the delivery obstruction signal output from the host control CPU will be explained 14 is transmitted.

In this embodiment, the adding circuit used in the first embodiment is 19 not provided. Therefore the output signal of the A / D converter 13a for video data directly to the outside of the software playback device 2 issued. According to this embodiment is an exclusive OR circuit 45 between the MPEG stretch circuit 11a for video data (MPEG-2) and the A / D converter 13a intended for video data. Described in more detail, this means that one of the MPEG stretch scarves tung 11a for video data (MPEG-2) output line consists of an output line for a blue color video signal, an output line for a green color video signal and an output line for a red color video signal. The output line for each color video signal then consists of an output line for a signal indicating the intensity and an output line for a signal indicating a polarity. The above exclusive OR circuit 45 is provided in the output line, which shows the polarity in the respective color. This means that this polarity signal is the one input terminal of the exclusive OR circuit 45 is fed. Furthermore, an output signal of the register 40 the other input terminal of the exclusive OR circuit 45 fed. The registry 40 takes the output prohibition signal from the host control CPU 14 come on. Then there is the register 40 the link value L in the initial state, but thereafter continues to output the link value H when an increase in the input-side delivery inhibition signal is detected. The exclusive OR circuit 45 enables in the event that the output of the register 40 has the logic value L, a forwarding of the polarity signal of the MPEG expansion circuit 11a for video data while it is the polarity signal of the MPEG stretching circuit 11a for video data inverted when the output signal of the register 40 assumes the logic value H, and then enables this inverted signal to be forwarded. As a result, this shows from the D / A converter 13a analog video signal forwarded for video data in the event that the output of the register 40 has the logic value L, a normal picture on the TV monitor unit, not shown, while in the event that the output of the register 40 has the linkage value H, displays an image inverted in brightness on the television monitor unit, not shown.

It should be noted that the above-mentioned logic circuit does not connect to the output terminal of the MPEG expansion circuits 11b and 11c is connected for the audio signal or the PC signal. Thus, even in the event that the output prohibition signal from the host control CPU 14 is output, the analog audio signal and the PC signal are output as normal.

It should be noted that the register 40 outputs the link value L when the reset signal from the host control CPU 14 is transmitted.

below becomes the operation of the embodiment explained.

The software playback device 2 according to this embodiment operates in the same manner as in the first embodiment until the host control CPU 14 emits the delivery disability signal. Accordingly, only the operation after the host control CPU is explained below 14 has issued the delivery disability signal.

If the in the booking data store 8th stored booking count X becomes 0 due to the decrementation, the signal state in each unit is as shown in FIG 15 is illustrated. 15 shows that the booking count X becomes 0 at a time "D" (see 15 (g) ).

The DES device or circuit 7 decrypts the data even after the booking count X becomes 0, and thus the delivery of the normal analog video signal from the MPEG stretching circuit 11a for video data also continued after time "D" (see 15 (a) ).

The host control CPU 14 then, when the booking count X becomes 0 at time "D", outputs the impulsive delivery obstruction signal (see 15 (b) ).

The registry 40 , which outputs the link value L before the point in time "D", supplies the linkage value H after the point in time "D", there being a synchronization with an increase in the received delivery obstruction signal.

The exclusive OR circuit 45 which is the output signal of this register 40 via its one input connection directly outputs the video polarity signal recorded via the other input connection before the time "D". Accordingly, the normal analog video signal from the video D / A converter 13a submitted for video data. In contrast, the exclusive OR circuit inverts 45 after the time "D" the video polarity signal received via said other input connection and emits this inverted signal. Thus, the analog video signal inverted in brightness from the D / A converter 13a for video data (see 15 (d) ).

It should be noted that the output of the audio signal and the PC output signal normally continue to take place (see 15 (e) and 15 (f) ).

Accordingly, after the time "D" when the booking count becomes 0, such a delivery hindrance is caused that the brightness of the image is inverted with respect to the image signal alone among the three output signals (image signal, audio signal, PC signal). At that time point, however, the voice signal and the PC signal continue to be delivered normally. Therefore, the user viewing the TV monitor unit, not shown, is able to recognize that the booking count X becomes 0 without such an erroneous idea that there is a malfunction in the equipment 2 is present.

At this moment, the audio signal and the PC signal are still routed normally. If the software is mainly based on the image (e.g. a film, an animation, etc.), a profit of the software owner is not violated. Rather, what can be considered has such an effect that the desire for continued use by the software user is increased. As a result, the software user is ready to charge the usage fee to the software beneficiary as compensation for adding the booking count X by removing the SD circuit 9 from the software playback device 2 to be paid.

in the The structure of the sixth embodiment will be explained below.

16 illustrates in a block diagram the structure of the software playback device or the software playback device used in the sixth embodiment of the present invention.

This embodiment has such a structure in the same manner as the first embodiment on that the Number of operations of stretching the video data frame is counted based on that of the MPEG standards is compressed, and that the booking count X in accordance is reduced with the number of operations concerned. This embodiment otherwise has one such a structure that Handicap for the case that the Booking count X 0, the output of the image signal on which a dummy signal is superimposed is done while the delivery of the normal audio signal and the PC signal are continued.

According to this embodiment, the format of the variety is in the CD-ROM 1 stored software explained.

17 illustrates in a block diagram a configuration of a circuit used when this CD-ROM 1 saves the video data. According to 17 denote F1, F2, ... analog picture frames. The symbol D also indicates dummy or blind data. This blind data item includes the use of the image data for the display of patterns which are based, for example, on random numbers. These frames D, F1, F2, .... are successively an A / D converter 51 fed on the input side. This A / D converter 51 converts frames D, F1, F2, .... into digital data. An output signal from the A / D converter 51 becomes a dummy data acquisition circuit 52 and an adder circuit 53 fed. This dummy data acquisition circuit 52 only extracts the blind data D from the data parts supplied on the input side. In the adder circuit 53 through this dummy data acquisition circuit 52 extracted dummy data D superimposed on the frame F1, F2, ... that of the adder circuit 53 from the A / D converter 51 are fed directly. Thus, the adder circuit outputs D, F1 + D, F2 + D, .... The output signals D, F1 + D, F2 + D, ... of the adder circuit 53 are then an MPEG-2 encoder 54 supplied and then compressed based on the MPEG-2 standards. The through this MPEG-2 encoder 54 compressed frames D, F1 + D, F2 + D, ... are hereinafter referred to as D ', F' (F1 + D), F '(F2 + D), ... The output signals D ', F' (F1 + D), F '(F2 + D), ... of the MPEG-2 encoder 54 are then an encryption circuit 55 fed on the input side. This encryption circuit 55 effects encryption by using a specific encryption key. The frames D ', F' (F1 + D), F '(F2 + D), ... through this encryption circuit 55 are then encrypted on the CD-ROM 1 written. In fact, these frames are briefly written on an original disc, and then bit patterns are made from them onto the commercially available CD-ROM 1 printed.

It should be noted that the dummy data D is not placed at the beginning or head of the speech signal, which is why the dummy data D is added by the adder circuit 53 not added, but directly to the MPEG-2 encoder 54 are fed on the input side. Furthermore, the blind data D are not used with regard to the computer program and therefore directly to the MPEG-2 encoder 54 fed on the input side. However, the computer program is not compressed according to the MPEG-2 standard, but only by the encryption circuit 55 encrypted.

The CD-ROM 1 stores the data subjected to analog / digital processing, encryption processing and compression processing. The data with the same format is this software playback device 2 via the connection from the software vendor, demodulated by a modem 51 fed on the input side.

The majority of the components of the software playback device 2 according to this embodiment is the same as that of the software playback device 2 according to the first embodiment. Accordingly, they are the same components th of the software playback device here as in the first embodiment with the same reference numerals as in the first embodiment. Explanation of these common elements will be omitted below, while only constructing a device for preventing delivery in accordance with the delivery preventing signal from the host control CPU 14 is explained.

According to this embodiment, the adder circuit used in the first embodiment is 19 not used. Therefore the output signal of the A / D converter 13a for video data directly to the outside of the software playback device 2 issued. According to this embodiment, a processing unit as shown in FIG 18 between the MPEG stretching circuit 11a for video data (MPEG-2) and the A / D converter 13a intended for video data.

The MPEG stretch circuit 11a for video data that the signal to this processing unit 46 releases, the stretches through the DES facility 7 decrypted data frames D ', F' (F1 + D), F '(F2 + D), .... The restored data frames D, F1 + D, F2 + D, ... are the processing unit 46 fed on the input side.

In contrast, the output inhibition signal from the host control CPU 14 the register 40 fed on the input side. This register 40 outputs the link value L in the initial state, but continues to output the link value H thereafter when the increase in the supplied output inhibiting signal is detected.

The output signal of the register 40 is through the inverter 41 inverted. With that the inverter gives 41 the link value H in the initial state, but continues to output the link value L after the output obstruction signal is output.

The output signal of the inverter 41 becomes an input terminal of an AND circuit 43 fed for a PC signal. The other input terminal of this AND circuit 43 for a PC signal is with an outside of the MPEG expansion circuit 11c connected for video data (MPEG-2). Accordingly, this AND circuit serves 43 for a PC signal as gate or push-button circuit for the PC signal. For this reason, this PC signal can only be forwarded if the output signal of the inverter 41 has the logic value H, while it is blocked in the case that the output signal of the inverter 41 has the linkage value L.

The output signal of the inverter 41 is also the processing unit 46 fed on the input side. With reference to 18 here is a special configuration of the processing unit 46 described. According to 18 is an output line from the MPEG stretch circuit 11a for video data (MPEG-2) with the dummy data acquisition circuit 47 and a subtracting circuit 49 connected. An output line from this dummy data acquisition circuit 47 is via a switch circuit 48 with the subtracting circuit 49 connected. The dummy data acquisition circuit 47 only extracts the dummy data frame D from the data frames D, F1 + D, F2 + D, ... that are generated by the MPEG stretching circuit 11a for video data (MPEG-2) and continues to deliver this dummy data frame D. The switch circuit 48 takes an opening and closing of a signal line between the blind data acquisition circuit 47 and the subtracting circuit 49 in accordance with the output signal of the inverter 41 in front. If the output signal of the inverter 41 assumes the logic value H, then this signal line in particular is used to deliver the dummy data frame D to the subtracting circuit 49 closed. In contrast, if the output signal of the inverter 41 has the logic value L, the switch circuit opens 48 this signal line to thereby deliver the dummy data frame D to the subtractor circuit 49 to lock. The subtracting circuit 49 Linkally takes a subtraction of that from the dummy data acquisition circuit 47 forth recorded dummy data D from the data frames F1 + D, F2 + D, ... before that from the MPEG expansion circuit 11a (MPEG-2) have been recorded. The output data frames of the subtraction circuit thus occur after the subtraction has been carried out 9 with D, F1, F2, ... on. However, performing the rest of the subtraction is limited to a case where the switch circuit 48 the signal line to the recording of the output signal with the logic value H from the inverter 41 closes.

In contrast, the switch circuit opens 48 when the inverter 41 outputs the logic value L, and the dummy data D are therefore the subtracting circuit 41 not supplied on the input side. Accordingly, the data frames F1 + D, F2 + D, ... that of the MPEG stretching circuit 11a for video data (MPEG-2) were not subtracted. The subtractor is now in charge 49 the received data frames D, F1 + D, F2 + D, ... directly to the digital / analog converter 13a for video data.

It should be noted that the processing unit mentioned above 46 not with the output sides of the MPEG stretch circuit 11b for video data and the MPEG expansion circuit 11c is connected for the PC signal. That’s why even in the event that the delivery obstruction signal from the host control GPU 14 is given, the analog audio signal and the PC signal as normal before.

It should be noted that the register 40 the output of the logic value L then stops when the reset signal from the host control CPU 14 is transmitted. The operation of the embodiment is explained below.

The software playback device 2 according to this embodiment operates in the same manner as in the first embodiment until the host control CPU 14 emits the delivery disability signal. Accordingly, only the operation after the host control CPU is explained below 14 has issued the delivery disability signal.

If the in the booking data store 8th stored booking count value X becomes 0 as a result of the incrementation, the signal state in each unit is as shown in FIG 19 is illustrated. 19 shows that the booking count X becomes 0 at a time "E" (see 19 (g) ).

The DES facility 7 decrypts the data even after the booking count X has become 0, which is why the same video signal to which blind data has been added as the previous one continues to be output after the time "E" (see 19 (a) ). The host control CPU 14 in the event that the booking count X becomes 0 at time "E", outputs the impulsive delivery obstruction signal (see 19 (b) ).

The registry 40 , which gave the link value L before the time "E", supplies the link value H after the time "E", which is synchronized with an increase in the received delivery disability signal. Accordingly, it gives the output of the register 40 on taking inverters 41 the link value H before the time "E", but the link value L after the time "E" (see 19 (c) ).

The AND circuit 43 for the PC signal, which is the forwarding of the PC signal in accordance with the output signal of the inverter 41 allows or disables, the PC signal "E" before such a time if the booking count X (g) is greater than 0 while it is delivering the PC signal to the outside of the facility 2 after the time "E" locks when the booking count X (g) becomes 0 (see 19 (f) ).

The circuit 48 enables or disables the forwarding of data through the dummy data acquisition circuit 47 extracted dummy data D in accordance with the output signal of the inverter 41 , As a result, the subtraction circuit gives 47 , that is the processing unit 46 the data frames D, F1, F2, ... to the D / A converter 13a for the video data before the time "E" if the booking count X (g) is greater than 0. For this reason, the D / A converter 13a for video data capable of outputting the analog video signal for displaying a normal picture on the television monitor unit, not shown. However, the initial dummy data frame D is not displayed. Furthermore, the subtraction circuit 47 , namely the processing unit 46 the data frames D, F1 + D, F2 + D, ..., which remain added to the dummy data D, to the D / A converter 13a for video data before the time "E" when the booking count X (g) becomes 0. It follows from this that the D / A converter 13a for video data, the video signal (to which the blind data are added) for displaying an unrecognizable image to the television monitor unit, not shown.

It should be noted that the audio signal continues to be output normally before and after the time "E" (see 19 (e) ).

Accordingly, after the time "E", in the event that the booking count becomes 0, such a delivery restriction is caused that the dummy data D for the display of the unrecognizable image with respect to the image signal is not eliminated and that there is further such a delivery restriction, that the delivery to the outside of the software playback device 2 is blocked with respect to the PC signal among the three output signals (image signal, audio signal and PC signal). At this time, however, the normal delivery of a speech signal C is maintained. Therefore, the user viewing the television monitor unit, not shown, is able to recognize that the booking count X becomes 0 without causing an erroneous evaluation, after which in the facility 2 a malfunction occurs. If the software is mainly based on the image (e.g. a film, an animation, etc.), a win by the software owner is incidentally not violated even if the audio signal remains to be delivered as normal. Rather, what can be considered has such an effect that the desire for continued use by the software user is increased. As a result, the software user is ready to charge the usage fee to the software beneficiary as compensation for adding the booking count X by removing the SD circuit 9 from the software playback device 2 to be paid.

in the The following are further modified examples.

at everyone explained above Embodiment will the disability processing is done so that the image or announcements or sounds processed with respect to the image signal and the audio signal. However, the following disability device is for a personal computer oriented one Acceptable signaling, that is for the in each of the figures the relevant execution forms PC signal shown.

For example, this disability facility is referenced to 2 explained.

The operating program of the host control CPU 14 is an operating program for outputting a disability image signal program through the input / output I / O unit 6b added before the DES establishment 7 the booking destination software decrypts when the booking count X in the booking data memory 8th becomes 0.

In this case, the host control CPU is required 14 is provided with a memory for storing the disability image signal program. At the same time, it is necessary to connect a circuit for separation or as an interface to a read output of the memory for or with respect to the PC signal. A disability image program is made on the basis of a program system with the present device 2 connected personal computer generated. The disability image program is designed to be started immediately after the personal computer executes a program from the CD-ROM 1 installed. The handicap image program is constructed from handicap image data and a command to read this item of the handicap image data from an address location in which the data is stored and to output the data to a display device such as a CRT, etc. of the personal computer. The disability image data is used, for example, to display a message "The requested installed program cannot be used due to the booking limit. Please bring the SD card to your nearby shop".

The following are the operations of the host control CPU 14 explained.

The control CPU 5 shows immediately when a content of the booking data storage 8th is present, that is, it has the effect that the booking count X becomes 0, the relevant effect of the host CPU 14 on. The host control CPU 14 stores this effect in a register area of a memory and starts the operation program for reading the disability image signal program. The operating program thus started works in such a way that the image obstruction output program is read byte by byte from a memory, not shown. The image obstruction output is then sent to the demultiplexer 10 via the I / O unit 6b issued. Then, this image obstruction output program in the form of the PC signal is demultiplexed and then via the MPEG stretching circuit 11c for video data to the personal computer, not shown. The output signal for this personal computer, not shown, is effected in a serial or byte-serial manner. When the reading and the delivery of the image obstruction handler are completed, the host control CPU ends 14 operation, but is placed in a waiting or standby state for the next processing. In contrast, this begins with this software playback device 2 connected personal computer, in the case that the output image obstruction output program is fully installed, this image obstruction output program as an initialization program. Upon this start-up, the image impairment output program is assigned to a specific address area in the main memory of the personal computer. The disability image data is then developed in an image memory, etc.

The developed disability image is displayed on a monitor display unit of the personal computer by submission. The delivery handicap can thereby be carried out for the PC-oriented application software from the CD-ROM 1 is read. The software user is then able to recognize the need to pay the fee for use from the displayed disability image.

As explained in detail above, the disability mechanisms for the corresponding levies are taken into account independently of one another in the illustrated embodiments. The disability mechanisms illustrated in the individual embodiments discussed above can be combined in a variety of forms within the scope of the present invention. For example, in 2 illustrated first embodiment of the structure of the superimposition and delivery of the disability display pattern on the decrypted image signals. However, such a structure can be made that the audio signal is through a speech signal inhibiting circuit 50 arrives as in 10 and 11 is illustrated. Furthermore, with regard to the PC signal, the circuit structure as described above with reference to a further modified embodiment can be entered into the control CPU 14 be involved. Moreover, the in 16 illustrated sixth embodiment of the structure illustrated, according to which the digital / analog conversion is carried out, the blind data ent encoded image signal can be added. However, such a structure can be made that the audio signal is through the speech signal inhibiting circuit 50 arrives like this in 10 and 11 is illustrated. Furthermore, with regard to the PC signal, the circuit arrangement described with reference to the further embodiment explained above can be inserted into the control CPU 14 be involved.

According to the present In the case of using the software, the invention can be made via the certain usable amount hinders the use of the software be while the fact that the software usage quantity is made known to the software user The certain usable amount is reached by the data in incomplete form be delivered.

In the device for managing software use in a system for emitting a signal to the outside by using software, it is advantageous that a detection device 101 is provided which determines the amount of use of the software that a determining device 102 is provided which determines that by the detector 101 determined software use reaches a certain amount of use, and that a disposal facility 103 it is provided that the blind data, which have previously been superimposed on the software, are removed from the software only in the event that the determination device 102 determines that software usage is within the specified usage amount.

It is also advantageous that a detection device 101 is provided, which determines the software use that a determination device 102 is provided which determines that by the detector 101 determined software use reaches a certain amount of use, and that a delivery device is provided which delivers an image signal or image signal program, which runs when the computer is started up, for displaying an alarm set to the computer, which is connected to the device for managing software use and in which the computer program is installed when said determination device 102 determines that software usage reaches a certain amount of usage.

Claims (16)

Device for managing software usage, the software comprising a number of frames in a compressed format, with a detection device ( 101 ) for determining usage of software by counting the number of stretched frames that are delivered, a determination device ( 102 ) to determine whether the use of the software by the recording device ( 101 ) is detected, has reached a predetermined value, and a delivery control device ( 103 ) for emitting an alarm signal without completely switching off the software output signal if the determination device ( 102 ) determines that the use of the software reaches the predetermined value. Device according to claim 1, characterized in that this Alarm signal generated by the software to output the software to deliver in another form. Apparatus according to claim 1 or 2, characterized in that the delivery control device ( 103 ) gives an output signal in an incomplete form when the determining device determines that the use of the software has reached the determined value. Device according to claim 3, characterized in that this Signal is a video signal. Apparatus according to claim 4, characterized in that the delivery control device ( 103 ) a second signal is superimposed on the video signal and then emits the superimposed signal when the determination device ( 102 ) determines that the use of the software has reached the certain value. Apparatus according to claim 5, characterized in that this second signal is a character data signal for displaying a character is. Apparatus according to claim 4, characterized in that the delivery control device ( 103 ) inverts a polarity of the video signal and outputs the signal inverted in polarity when the determination device ( 102 ) determines that the use of the software has reached the certain value. Apparatus according to claim 3, characterized in that blind data are superimposed on the software and that the delivery control device ( 103 ) the blind data is only removed by the software if the determination device ( 102 ) determines that the use of the software is within the specified value. Device according to Claim 3, characterized in that the signal comprises a plurality of signals which are emitted synchronously with one another, and in that the dispensing control device ( 103 ) blocks at least one of the plurality of signals with respect to the delivery in the event that the determination device ( 102 ) determines that the software use the has reached a certain value. Device according to claim 9, characterized in that the plurality of signals comprises a video signal and an audio signal and in that the delivery control device ( 103 ) blocks the delivery of the audio signal while the delivery of the video signal takes place when the determination device ( 102 ) determines that the software usage has reached the certain value. Apparatus according to claim 9, characterized in that the plurality of signals comprises a video signal and an audio signal and that the delivery control device ( 103 ) blocks the delivery of the video signal while the delivery of the audio signal takes place when the determination device ( 102 ) determines that the software usage has reached the certain value. Device according to claim 3, characterized in that the signal comprises an audio signal and in that the delivery control device ( 103 ) stops the delivery of the audio signal and emits an alarm tone signal when the determination device ( 102 ) determines that the software usage has reached the certain value. Device according to claim 12, characterized in that the delivery control device ( 103 ) includes a timer for controlling a period of time during which the alarm tone signal and, alternately, the audio signal and the alarm tone signal are repeatedly output in accordance with the timer. Apparatus according to claim 13, characterized in that the delivery control device ( 103 ) further comprises a counter with which the number of operations of the output of the alarm tone signal is counted and which blocks the output of the audio signal and the alarm tone signal in the event that a count value of the relevant counter reaches a certain value. Device according to claim 12, characterized in that a Time control device for restricting a duration is provided during which the alarm tone signal is given, after the duration in question no sound signal and no audio signal is emitted. Apparatus according to claim 3, characterized in that the delivery control device ( 103 ) outputs an image signal program, which runs when a computer is connected, which is connected to the device for managing software use, in order to display an alarm when the determination device ( 102 ) determines that the software usage has reached a certain value.