CN1512354A - 用于后期重映射虚拟机存储器页面的机制 - Google Patents

用于后期重映射虚拟机存储器页面的机制 Download PDF

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CN1512354A
CN1512354A CNA2003101235665A CN200310123566A CN1512354A CN 1512354 A CN1512354 A CN 1512354A CN A2003101235665 A CNA2003101235665 A CN A2003101235665A CN 200310123566 A CN200310123566 A CN 200310123566A CN 1512354 A CN1512354 A CN 1512354A
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CN100445964C (zh
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C・D・哈尔
C·D·哈尔
坎贝尔
R·L·坎贝尔
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Intel Corp
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10Address translation
    • G06F12/1027Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1036Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation

Abstract

依照一个实施例,公开了一种计算机系统。所述计算机系统包括处理器、与处理器相耦合的芯片组以及与芯片组相耦合的存储器。所述芯片组将从处理器接收的分区虚拟机存储器地址转换为页面级地址。

Description

用于后期重映射虚拟机存储器页面的机制
技术领域
此发明涉及诸如微处理器的计算机处理器的虚拟机。具体来讲,本发明涉及对虚拟机的存储器管理。
背景技术
在此包含的是受到版权保护的材料。正如在专利商标局的专利文件或记录中所公开的那样,版权所有人不反对任何人对专利公开内容的复制,但是另外无论如何都保留对于版权的所有权利。
操作系统(OS)是用于控制物理计算机硬件(例如,处理器、存储器以及盘和CD-ROM驱动器)的一种软件程序,并且给应用程序提供一组统一的抽象服务(例如,文件系统)。虚拟机管理器(VMM)也是一种控制物理计算机硬件的软件程序,所述物理计算机硬件例如像处理器、存储器以及磁盘驱动器。与OS不同,VMM给在虚拟机(VM)内部执行的程序提供一种错觉,好像所述程序是在真的物理计算机硬件上执行,所述物理计算机硬件例如是处理器、存储器和磁盘驱动器。
每个VM通常作为自包含实体来运行,使得在VM中执行的软件好像正单独运行在“裸”机上,而非在虚拟机内部那样来执行,其中所述虚拟机与其它VM共享处理器和其它物理硬件。这就是VMM,其仿效“裸”机的确定功能,以便使在VM内部执行的软件执行起来就好像它是一个在计算机上执行的单独实体一样。
已经开发了各种技术来为运行在系统上的虚拟机分配物理系统存储器。一种这样的技术是利用分区存储器。所述分区存储器是将物理系统存储器分为多个连续区域的情形。虽然分区存储器在CPU中实现起来不算昂贵,但是存储器在虚拟机之间却不能够被容易地动态重新配置。
还开发了多种技术以用于通过给定的存储容量来获得更多的性能。一种这样的技术是利用虚拟存储器。虚拟存储器是基于这样一种概念,即当运行程序时,不必将整个程序一次载入主存储器。相反,计算机的操作系统将根据执行的需要将程序段从二级存储器设备(例如硬盘驱动器)载入主存储器。
为使该方案可行,操作系统维护了如下的表,所述表用于持续跟踪每个程序段驻留在主存储器和二级存储器中的位置。作为以该方式执行程序的结果,程序的逻辑地址不再对应于主存储器中的物理地址。为处理这种情况,中央处理单元(CPU)将程序的有效地址或虚拟地址映射成它们对应的物理地址。
然而,在执行分区存储器技术的计算机系统中,常常希望为每个虚拟机动态地重新分配存储器。还希望以单个页面为基础,而不是以大容量的区域为基础来管理存储器。采用当前分区存储器系统,不可以动态地重新分配存储器。当前分区存储器系统还对页面级的灵活性强加了许多限制,而许多操作系统都需要所述页面级的灵活性来支持虚拟存储器。
附图说明
通过下面所给出的详细描述以及通过本发明不同实施例的附图,将会更加全面地理解本发明。然而,不应该将所述附图理解为将本发明限定为具体的实施例,而仅仅是为了说明和理解。
图1是计算机系统的一个实施例的框图;
图2是耦合到芯片组和存储器设备的处理器的一个实施例的框图;
图3是芯片组重映射机制的一个实施例的框图;
图4是将虚拟地址转换为页面地址的一个实施例的流程图;以及
图5是耦合到芯片组和存储器设备的总线主控器的一个实施例的框图。
具体实施方式
下面描述用于将分区虚拟机存储器重映射到页面粒度存储器(page granular memory)的机制。在说明书中提及的“一个实施例”或“一实施例”意指就该实施例所描述的特定特征、结构或特性,包括在本发明的至少一个实施例中。在说明书不同地方出现的短语“在一个实施例中”未必都指的是同一实施例。
在随后的描述中,提出了很多细节。然而,对于本领域技术人员而言,显而易见的是,在没有这些具体细节的情况下也可以实施本发明。在其他情况下,为了避免模糊本发明,以框图形状示出了公知的结构和设备,而没有以细节的方式示出。
图1是计算机系统100的一个实施例的框图。计算机系统100包括用于处理数据信号的处理器101。处理器101可以是复杂指令集计算机(CISC)微处理器、精简指令集计算(RISC)微处理器、超长指令字(VLIW)微处理器、实现指令集组合的处理器或其它处理器设备。
在一个实施例中,处理器101是包括奔腾IV系列和移动奔腾的奔腾系列处理器中的一种处理器,并且括奔腾IV可以从California的Santa Clara的Intel公司购买到。作为选择,还可以使用其它处理器。图1示出了采用单一处理器计算机的计算机系统100的例子。然而,本领域普通技术人员将会意识到,计算机系统100可以使用多个处理器来实现。
处理器101与处理器总线110相耦合。处理器总线110在计算机系统100中的处理器101和其它部件之间传送数据信号。计算机系统100还包括存储器113。在一个实施例中,存储器113是动态随机存取存储器(DRAM)设备。然而,在其它实施例中,存储器113可以是静态随机存取存储器(SRAM)设备,或其它存储器设备。
存储器113可以存储由数据信号表示的指令和代码,所述指令和代码可以由处理器101执行。依照一个实施例,高速缓冲存储器102驻留在处理器101内,并存储如下的数据信号,这些数据信号还被存储在存储器113中。高速缓冲存储器102由处理器101通过利用其访问的局部性来加速存储器访问。在另一个实施例中,高速缓冲存储器102驻留在处理器101的外部。
计算机系统100进一步包括芯片组111,所述芯片组111与处理器总线110和存储器113相耦合。芯片组111控制计算机系统100中的处理器101、存储器113以及其它部件之间的数据信号,并且桥接在处理器总线110、存储器113以及第一输入/输出(I/O)总线120之间的数据信号。
在一个实施例中,I/O总线120可以是单条总线或多条总线的组合。在其它的实施例中,I/O总线120可以是遵守2。1版本规范的外围部件互连(Peripheral Component Interconnect)总线,其是由设立于Oregon的Portland的PCI专业组开发的。在另一个实施例中,I/O总线120还可以是由设立于California的San Jose的PCMCIA开发的个人计算机存储卡国际协会(PCMCIA)总线。作为选择,还可以使用其它总线来实现I/O总线。I/O总线120提供了计算机系统100中的部件之间的通信链路。
网络控制器121与I/O总线120相耦合。网络控制器121将计算机系统100链接到计算机网络(图1中未示出)中,并且支持机器之中的通信。在一个实施例中,计算机系统100经由网络控制器121从计算机110接收流式视频数据。
显示设备控制器122也与I/O总线120相耦合。显示设备控制器122允许将显示设备耦合到计算机系统100,并且充当显示设备和计算机系统100之间的接口。在一个实施例中,显示设备控制器122是单色显示适配器(MDA)卡。
在其它实施例中,显示设备控制器122还可以是彩色图形适配器(CGA)卡、增强型图形适配器(EGA)卡、扩展型图形阵列(XGA)卡,或其它显示设备控制器。该显示设备可以是电视机、计算机监视器、平板显示器或其它显示设备。该显示设备经由显示设备控制器122从处理器101来接收数据信号,并向计算机系统100的用户显示信息和数据信号。
视频译码器123也与I/O总线120相耦合。视频译码器123是用于将所接收到的编码数据转换为其原始格式的硬件设备。依照一个实施例,视频译码器123是运动图像专家组4(MPEG-4)译码器。然而,本领域普通技术人员将会意识到,视频译码器123还可以采用其它类型的MPEG译码器来实现。
依照一个实施例,计算机系统100支持使用分区存储器的虚拟机。在其它实施例中,计算机系统100包括用于后期将虚拟机存储器重映射到页面粒度存储器的机制。图2是与芯片组111和存储器设备113相耦合的处理器101的一个实施例的框图。处理器101包括分区逻辑210以及转换后援缓冲器(TLB)218。
分区逻辑210通过存储器113中的地址分区来支持虚拟机系统。分区逻辑210存储映射信息,该映射信息表示存储器113中的页在TLB218的位置。具体来讲,分区逻辑210为每个虚拟机生成一地址范围。例如,可以将0-1Gb的范围分配给第一虚拟机,同时将1-2Gb、以及2-3Gb的范围分别分配给第二和第三虚拟机。
TLB218与分区逻辑210相耦合。TLB218是在存储器113中最频繁使用的页表项(PTE)的高速缓存器。具体来讲,TLB218包括正在存储器113中使用的当前有效地址。因此,每当执行地址转换时,未必要访问存储器113中的PTE。
在常规的虚拟机系统中,分区逻辑210以及TLB218执行所有必要的地址转换。然而,常常希望以单个页面为基础来管理存储器113,而不是以大容量的区域为基础。采用当前分区存储器系统,不可以指定如下页面级灵活性的存储器,所述页级灵活性是大多数操作系统所要求的。
芯片组111包括TLB220。TLB220是一高速缓冲存储器,其包括在存储器113内的重映射表中正在使用的当前有效地址。存储器113包括页表236以及重映射表238。页表236将分区虚拟机地址转换为物理存储器地址。页表236包括PTE的集合。页表236为每个映射的虚拟页保持一个PTE。为了访问物理存储器中的页,查找适当的PTE以便找到该页驻留的位置。
与页表236相似,重映射表238包括一表项的列表,该表项用于规定分区虚拟地址到页面级地址的重映射。在一个实施例中,实现TLB220以及重映射表238,以便相反地转换存储器地址从而支持页面级操作,由此,规避了由处理器101强加的分区范围。
图5是与芯片组111及存储器设备113相耦合的处理器101和总线主控器530的另一个实施例的框图。总线主控器530是I/O设备(例如,磁盘控制器、图形控制器等),其有权访问存储器113。偏移寄存器550耦合在总线主控器530和TLB220之间。
偏移寄存器550提供到虚拟机地址空间的映射,所述虚拟机控制总线主控器530。通常,计算机系统100的操作系统期望分区虚拟机物理地址是实际地址。然而,由于所述地址因为芯片组进行的重映射而不是真的物理地址,所以由总线主控器使用的地址是不正确的。由此,偏移管理器550以及TLB220纠正该地址,以便将该地址转换为与在VM中运行的操作系统的地址相同的地址。依照一个实施例,TLB220可以根据TLB220的基址内的标志位阻塞总线主控器530访问存储器113。该标志可以依据由具体特定实现所提供的定义来阻止读访问或写访问或者它们两者。
图3是芯片组111的一个实施例的框图。如上所述,芯片组111包括TLB220。TLB220包括TLB输入305、TLB输出310、重映射目录320以及重映射表330。TLB输入305接收来自于处理器101内部的分区逻辑210的分区地址。TLB输出310将已转换的物理地址传送到存储器113。
目录项320接收分区地址的底部10位,以便在重映射表330定义起始位置。重映射表330接收下面的10个位,所述下面的10个位表示重映射表330内的、包括对应的物理地址的实际表项。在选择了物理地址之后,将该地址连同分区地址的最先12位一起从TLB输出310被传送。
图4是将虚拟地址转换为页面地址的一个实施例的流程图。在处理块410处,处理器101中的页表(例如TLB218)将逻辑地址转换为虚拟存储器物理地址。在处理块420处,分区逻辑210将虚拟存储器物理地址转换到分区地址空间。在处理块430处,芯片组重映射机制将分区地址空间转换到物理地址空间。在处理块440处,将物理地址传送到存储器113。
芯片组重映射机制结合了存储器分区和页面粒度重映射的优点。由此,芯片组重映射机制能够使处理器支持具有分区存储器空间的虚拟机充分利用由页面粒度存储器空间提供的灵活性。例如,现在可以实现为虚拟机动态调整存储器大小,而这在常规系统中几乎是不可能的。
然而,对于本领域普通技术人员来说,在已阅读前面的描述之后,本发明的多种替换和修改无疑是显而易见的,应该理解的是,为了举例说明而所示出以及所描述的具体实施例不能理解为是对本发明的限制。因此,提及各种实施例的细节不意味限制权利要求书的范围,该权利要求书本身陈述了被视为本发明的那些特征。

Claims (17)

1.一种计算机系统,包括:
处理器;
芯片组,与所述处理器相耦合,用于将从处理器接收的分区虚拟机存储器地址转换为页面级地址;以及
与芯片组相耦合的存储器设备。
2.如权利要求1所述的计算机,其中,所述芯片组包括用于将分区机器存储器地址转换为页面级地址的转换后援缓冲器(TLB)。
3.如权利要求2所述的计算机,其中所述TLB包括:
用于接收分区地址的输入;
与所述输入相耦合的重映射目录;
与所述目录和输入相耦合的重映射表;以及
与所述重映射表相耦合的输出,用于传送物理地址。
4.如权利要求3所述的计算机,其中存储器设备包括:
重映射表,用于将分区虚拟机地址转换为物理存储器地址;以及
页表,用于规定分区虚拟机地址到页面级地址的重映射。
5.如权利要求2所述的计算机,其中所述TLB进一步包括:
总线主控器设备;以及
与总线主控器设备和TLB相耦合的偏移寄存器。
6.如权利要求5所述的计算机,其中所述TLB根据TLB基址内的标志位来控制总线主控器设备访问存储器的权限。
7.如权利要求6所述的计算机,其中所述总线主控器设备是图形控制器。
8.如权利要求6所述的计算机,其中所述总线主控器设备是磁盘控制器。
9.一种包括转换后援缓冲器(TLB)的芯片组,所述转换后援缓冲器用于将从处理器接收的分区机器存储器地址转换为页面级地址。
10.如权利要求9所述的芯片组,其中所述TLB包括:
用于接收分区地址的输入;
与所述输入相耦合的重映射目录;
与所述目录和输入相耦合的重映射表;以及
与所述重映射表相耦合的输出,用于向存储设备器传送物理地址。
11.如权利要求10所述的芯片组,其中所述TLB进一步包括:
总线主控器设备;以及
与总线主控器设备和第一TLB相耦合的偏移寄存器。
12.如权利要求11所述的芯片组,其中所述TLB根据TLB基址内的标志位来控制总线主控器设备访问存储器的权限。
13.如权利要求11所述的芯片组,其中所述总线主控器设备是图形控制器。
14.如权利要求11所述的芯片组,其中所述总线主控器设备是磁盘控制器。
15.一种方法,包括:
在芯片组接收分区虚拟机存储器地址;以及
在芯片组将从处理器接收的分区虚拟机存储器地址转换为页面级地址。
16.如权利要求15所述的方法,进一步包括:
在处理器将逻辑地址转换为虚拟机存储器物理地址;以及
将虚拟机存储器物理地址转换为分区虚拟机存储器地址。
17.如权利要求16所述的方法,进一步包括:将分区虚拟机存储器地址传送到芯片组。
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