CN105068951A - On-chip system bus with anisochronous transmission structure - Google Patents
On-chip system bus with anisochronous transmission structure Download PDFInfo
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- 230000005540 biological transmission Effects 0.000 title abstract description 21
- 238000004891 communication Methods 0.000 claims abstract description 12
- 238000012546 transfer Methods 0.000 claims description 15
- 238000013475 authorization Methods 0.000 claims description 8
- 230000006399 behavior Effects 0.000 claims description 6
- 230000008054 signal transmission Effects 0.000 claims description 4
- 230000004044 response Effects 0.000 claims description 3
- 238000012544 monitoring process Methods 0.000 claims 1
- 230000000875 corresponding effect Effects 0.000 description 24
- 238000010586 diagram Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000000737 periodic effect Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
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- 235000012364 Peperomia pellucida Nutrition 0.000 description 1
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- 239000003795 chemical substances by application Substances 0.000 description 1
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/4031—Coupling between buses using bus bridges with arbitration
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/404—Coupling between buses using bus bridges with address mapping
Abstract
The invention discloses an on-chip system bus, comprising a request priority queue, an arbiter group, an address and control signal selector, an internet and an address decoder. A primary device transmits a bus request signal to the address decoder; the address decoder transmits an application signal to the request priority queue according to the bus request signal; the request priority queue latches the application signal and generates a chip selection signal, and transmits the chip selection signal to the internet, and transmits the application signal to the arbiter group at the same time; the arbiter group transmits an arbitration result signal to the internet; the internet selects data and a handshake signal from the primary device to slave device according to the arbitration result signal, and the internet controls the data and the handshake signal from the primary device to slave device according to the chip selection signal. The on-chip system bus of the invention has different transmission time among different primary devices and slave devices on a large-area chip to achieve high-speed, parallel and real-time communication among devices.
Description
Technical field
The invention belongs to chip-on communication field, particularly relate to a kind of SOC (system on a chip) bus with non-isochronous transfers structure.
Background technology
Along with the development of integrated circuit technique, the more processor core of SOC (system on a chip) demand, coprocessor core and more On-Chip peripheral.And the fast development of the technology such as multimedia, communication, require between each equipment on sheet, to have high speed, parallel, real-time communication mode.
In order to pursue higher transfer rate, the frequency of system bus is improving constantly, but because the more functional requirement such as multinuclear, many peripheral hardwares, even if under the support of more precision process, the area of chip is also in continuous expansion, and this causes the contradiction on sheet between device transmission time and bus frequency.The multiple bus system of current existence, when being used on the high frequency high bandwidth system communication in large-area chips, superimpose data carries out the transmission of continuous-flow type, and person uses more pipeline register by causing, and consumes ample resources; Otherwise can only Bus Clock Rate be reduced, so just affect the performance of bus entirety.
If only have a data bus, when two equipment carry out data communication, if other equipment wishes to conduct interviews to another equipment, although do not conflict between equipment with equipment, but this equipment can only be waited for, or the equipment of higher priority is allowed to interrupt current communication.Forms data bus limits the data throughout of whole system, the system higher to data throughput requirement needs to communicate between many groups equipment simultaneously: be correlated with (such as two main equipments access one from equipment simultaneously) so long as not because equipment produces, the carrying out that just can walk abreast communicates.
Fig. 1 is the connection diagram of equipment on sheet in certain system of prior art, wherein can only be accessed by main equipment 0 and main equipment 1 from equipment 0 (from 0), from equipment 1, can be accessed by all main equipments from equipment group 2.From equipment 0, from equipment 1 with can walk abreast accessed by three different main equipments from equipment group 2.The structure 10 i.e. simple signal of bus in figure.The arbitration mechanism of bus can make the equipment of high priority preferentially use bus, so the equipment of lower priority just needs to wait for.If do not have suitable mode, the equipment higher when priority constantly sends bus request, and low priority equipment can not get the right to use of bus for a long time.For the system that requirement of real-time is higher, such as communication system, needs bus to have the ability guarantee equipment within the bus cycles of specifying, and obtains the right to use of bus.
Summary of the invention
(1) technical matters that will solve
The object of the invention is to, provide a kind of SOC (system on a chip) bus, there is between particularly different in large-area chips master-slave equipments the different transmission times (clock period), realize high speed, parallel, real-time communication between devices.
(2) technical scheme
The invention provides a kind of SOC (system on a chip) bus, for main equipment with from the communication between equipment, comprise Request Priority queue, moderator group, address and control signal selector switch, internet and address decoder; Wherein,
Main equipment sends bus request signal to address decoder, and sends corresponding address signal and control signal to address and control signal selector switch;
Described address decoder, according to described bus request signal, sends to moderator group and immediately applies for vector, described instant application vector is sent to Request Priority queue simultaneously;
Described instant application vector latches by described request priority query, generates chip selection signal, and described chip selection signal is sent to described internet, meanwhile, generates queue application vector and is sent to described moderator group;
Moderator group sends arbitration result signal to address and control signal selector switch according to application signal, and address and control signal selector switch according to the address signal of arbitration result signal behavior main equipment and control signal, and transfer to from equipment;
Moderator group also sends arbitration result signal to internet, internet is according to arbitration result signal behavior main equipment extremely from data and the handshake of device orientation, and internet also controls from equipment to the data in main equipment direction and handshake according to chip selection signal.
(3) beneficial effect
1, the invention provides a kind of SOC (system on a chip) bus, transmission cycle in this bus between permission equipment is different, and bus frequency is determined by the equipment that the wherein transmission time is shorter, the equipment room path of transmission range more than one bus cycles is retrained by multi-cycle path, make with unified bus form, minimum hardware spending solves the contradiction in bus frequency and equipment room transmission time in large-area chips, and bus frequency therefore can be higher according to design requirement; Data at a high speed can be carried out with the bus cycles between the equipment that transmission time is short to transmit; Between the equipment that transmission time is longer without the need to using pipeline register and bus agent, reduce resource consumption.
2, SOC (system on a chip) bus provided by the invention, give respective bus agreement, this agreement is the continuous-flow type bus protocol on monolateral edge, this agreement is by bus application, the transmission of address and control signal and the transmission of data divide and operate at two pipelining-stages, key does not need extra bus application operation, address and control signal is provided when applying for bus, next is clapped according to handshake sending and receiving data, the operation of monolateral edge is made to ensure that high bus frequency, continuous-flow type operation and without the need to the extra bus application time, even if ensure that the bus efficiency when bus-handover, especially, when non-burst is transmitted, the main equipment of multi-cycle path can not affect bus and the response efficiency from equipment.
3, SOC (system on a chip) bus provided by the invention, has Request Priority queue, determines the priority of request, ensure that the real-time that device request responds with the priority entering queue.
Accompanying drawing explanation
Fig. 1 is the rough schematic that in prior art, system-on-chip apparatus connects.
Fig. 2 is the structural drawing of the SOC (system on a chip) bus that the embodiment of the present invention provides.
Fig. 3 is the structural drawing of moderator group in the embodiment of the present invention.
Fig. 4 be in the embodiment of the present invention between master-slave equipment 3 to 3 complete interconnected schematic diagram.
Fig. 5 is the structural drawing of request priority queue in the embodiment of the present invention.
Fig. 6 is main equipment and the interface framework from equipment in the embodiment of the present invention.
Fig. 7 is man-to-man transmission time sequence figure between master-slave equipment in the embodiment of the present invention.
Fig. 8 is main line handing-over sequential chart in the embodiment of the present invention.
Fig. 9 is that the main equipment in a binary cycle path and a monocycle path in the embodiment of the present invention uses bus to carry out the sequential chart read and write mutually.
That sequential and bus-handover timing diagram are write in a burst in Figure 10 embodiment of the present invention.
It is the burst transfer sequential chart of two periodic path in Figure 11 embodiment of the present invention.
It is the sequential chart that multiple main equipment competes a bus simultaneously in Figure 12 embodiment of the present invention.
Embodiment
The invention provides a kind of SOC (system on a chip) bus, comprise Request Priority queue, moderator group, address and control signal selector switch, internet and address decoder; Main equipment sends bus request signal to address decoder, and sends corresponding address signal and control signal to address and control signal selector switch; Address decoder, according to bus request signal, sends to moderator group and Request Priority queue and immediately applies for vector; Request Priority queue will apply for signal latch, generate chip selection signal, and chip selection signal is sent to internet, simultaneously, provide each application from equipment group vector according to first in first out, queue empty directly selects the result of address decoder to be sent to moderator group as the application signal of current period; Moderator group sends arbitration result signal to address and control signal selector switch according to application signal, address and control signal selector switch are according to the address signal of arbitration result signal behavior main equipment and control signal, and transfer to and also send arbitration result signal to internet from equipment arbitration device group, internet is according to arbitration result signal behavior main equipment extremely from data and the handshake of device orientation, and internet also controls from equipment to the data in main equipment direction and handshake according to chip selection signal.
In one embodiment, this SOC (system on a chip) bus also comprises an address and control signal storer, described moderator group also returns an authorization signal to Request Priority queue, make the bus request signal of main equipment enter Request Priority queue according to authorization signal, make the address signal of main equipment and control signal enter address and control signal storer simultaneously.
In one embodiment, this SOC (system on a chip) bus also comprises a first selector, when Request Priority queue is empty, Request Priority queue transmit queue spacing wave is to the control end of first selector, the first selector address signal of directly selecting main equipment to send and control signal to address and control signal selector switch, otherwise first selector is selected the address signal in address and control signal storer and is controlled signal to address and control signal selector switch.
In one embodiment, this SOC (system on a chip) bus also comprises a second selector, when Request Priority queue is empty, Request Priority queue transmit queue spacing wave is to the control end of second selector, the application signal that second selector directly selects address decoder to send is to moderator group, otherwise the application signal that second selector selects Request Priority queue to send is to moderator group.
In one embodiment, moderator group comprises one or more moderator, and the quantity of moderator is identical with the quantity from equipment.
In one embodiment, the arbitrated logic in moderator is priority encoder.
In one embodiment, this SOC (system on a chip) bus also comprises arbitration result register, moderator group first sends described arbitration result signal to described arbitration result register, then by described arbitration result register, arbitration result signal is sent to described internet.
In one embodiment, main equipment, after this cycle sends signal, without the need to waiting for authorization signal, directly sending at next cycle and writing data to from equipment, and monitors the described handshake sent from equipment.
In one embodiment, the SOC (system on a chip) bus Signal transmissions that main equipment sent by one or more clock period is to from equipment.
In one embodiment, with main equipment time sequence information in the control signal that main equipment sends, control the described response cycle from equipment by main equipment time sequence information, to mate main equipment and from the transfer rate between equipment.Between the master-slave equipment that SOC (system on a chip) bus of the present invention is different in large-area chips, there is the different transmission times (clock period), realize high speed, parallel, real-time communication between devices.
For making the object, technical solutions and advantages of the present invention clearly understand, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
Fig. 2 is the structural drawing of SOC (system on a chip) bus provided by the invention, as shown in Figure 2, bus 10 comprises Request Priority queue 201, moderator group 202, address and control signal storer 203, address and control signal selector switch 204, arbitration result register 205, internet 206, address decoder 207, first selector 208 and second selector 209 (this structure of expression that in figure, the lower left corner of structured flowchart has clock to input warning triangle is sequential logic or wherein there is sequential logic, and this mark is applicable to other figure herein).Each main equipment can send bus request signal at any time, provides address and the control signal of this request simultaneously; Vector is applied for immediately to providing from equipment (group) of correspondence in the address that address decoder 207 provides according to main equipment, and will immediately apply for that vector is sent to Request Priority queue 201, control from equipment end to the data selection of main equipment extreme direction as chip selection signal after latch, Request Priority queue is according to the principle of first-in first-out simultaneously, to dequeue application vector; For each from equipment (group), according to " queue empty " signal from device queue corresponding in Request Priority queue 201, if sky, select immediately to apply for vector, if non-NULL, select queue application vector, selection result is as the input of moderator group 202 and bus request signal; After arbitration, the result of each moderator returns answer signal to Request Priority queue 201, enablely do not entered Request Priority queue 201 by the request of immediately authorizing bus, simultaneously relevant address/control signal enters in address and control signal storer 203, and be awarded the address of the main equipment of bus and control signal and control address and control signal selector switch 204 by arbitration result and select to transfer to each from device port, latch by from equipment, being convenient to next cycle reads and writes data; Arbitration result also will be latched in arbitration result register 205 simultaneously, select main equipment to from the data (writing data) of device orientation and handshake for internet 206, be latched in chip selection signal in Request Priority queue 201 and will control the data (read data) of internet 206 from equipment to main equipment direction and handshake.Main equipment, in the next operating cycle sending request signal, just can provide the data write data or read since equipment, provide next bus request simultaneously.Wherein, the moderator quantity in moderator group 202 is identical with the current quantity from equipment (group), and both corresponding relations are as moderator in Fig. 1 and the corresponding relation from equipment (group).
Fig. 3 is the cut-away view of moderator 202 in the present embodiment.The input of first each moderator is a bit wide and can access this and apply for vector from identical one of the main equipment quantity of equipment (group), vector intermediate value be that " height " represents that the application of corresponding main equipment needs is to this access from equipment (group), and arbitrated logic exactly from these are applied for a selection main equipment give bus.Because the existence of bus request priority queue 201, the Main Function of arbitrated logic is herein exactly select one from the main equipment simultaneously applying for bus, so arbitrated logic can be the arbitrated logic of a comparatively simple fixed priority, such as priority encoder.Each moderator output is the vector with the same bit wide of input, and the output that effectively input is corresponding is " solely hot ", namely only has a main equipment to be awarded bus; Invalid input (0 vector) corresponding invalid output (0 vector).The output of each moderator will control the corresponding input selection from equipment (group), and the data/control signals of authorized main equipment can drive this from the data/control bus of equipment (group).For same main equipment, each moderator can provide authorization signal, the authority bit of all corresponding main equipments is carried out OR operation, it is exactly the authorization signal of this main equipment, this signal is mainly used in the stored logic on control bus: Request Priority queue 201, address and control signal storer 203.
Fig. 4 be one 3 of internet 206 in the present embodiment to 3 complete interconnected exemplary plot.Wherein, the value of arbitration result register 205 is for selecting main equipment to the selector switch from device orientation, and the chip selection signal in Request Priority queue 201 is for selecting the selector switch from equipment to main equipment direction.Wherein address and control signal selector switch 204 are similar to the selector switch that right side one in Fig. 4 arranges, and difference is, the selection signal of address and control signal selector switch 204 be not deposit after arbitration result, but the current arbitration result produced by moderator.
Fig. 5 is the structural drawing of Request Priority queue 201 in the present embodiment.It comprises first memory 501, second memory 502 and the 3rd storer 503, and wherein, first memory 201 is for storing effective address decoding value, and storage size is m × n position (m represents main equipment number, and n represents from equipment group number, lower same); Second memory 502 is for storing from the maximum preferred value of equipment group, and storage size is n × log
2m, namely each from the corresponding width of equipment group be log
2the storer of m; 3rd storer 503 is for storing main equipment preferred value, and storage size is m × log
2m, the i.e. corresponding log of each main equipment
2the storer of m.The initial value of storer 502 is 0, and representing corresponding is empty from the application queue of equipment group, and the queue empty's signal produced with this is for controlling first selector 208 and second selector 209.3rd storer 503 is the priority of each main equipment, needs are not immediately authorized to fall in lines when there being request, select the preferred value of " from increasing 1 " value as this main equipment of the second memory 502 of application object, this second memory 502 also needs " from increasing 1 " simultaneously.Preferred value is only selected to equal the request of the main equipment of " 1 " as output when queue exports.When being only heat for certain from the request of equipment group in output, and effectively " SValid " signal should be provided from equipment group, then corresponding second memory 502 needs " certainly subtracting 1 ", and should be selected by chip selection signal by " certainly subtracting 1 " signal, enable main equipment preferred value " subtracts 1 " certainly.For second memory 502, when " from increasing 1 " signal identical with " certainly subtracting 1 " signal (inclusive OR), then keep initial value.
The using method of this bus is hereafter described, i.e. its bus protocol.
Initiate bus request from main equipment and be divided into two stages to use bus transfer data, the stage one is that main equipment initiates request, and the stage two is data transmission between master-slave equipment.Stage one and stage two are two pipelining-stages in bus operation, and namely when first request carries out the stage two, main equipment can provide the signal in the stage one of second request (for same from equipment group) simultaneously.
S1 main equipment sends request, address and control signal, and judge that input is from equipment useful signal, this belongs to the stage one simultaneously;
S2 is after being effectively height from equipment, and in the next clock period, if write operation, main equipment sends and writes data, and provides main equipment useful signal, if read operation, main equipment latches read data when being high from equipment useful signal, and this belongs to the stage two;
S3 is while S2 carries out, and main equipment can carry out the S1 of next bus request simultaneously;
S4 is while S1 carries out, and will receive address that main equipment sends and control signal latches from equipment, this belongs to the stage one;
S5 while S2 carries out, according to address and control signal, if write operation, then will write data write corresponding address when main equipment useful signal is high from equipment, if read operation, then send corresponding address data and from equipment useful signal, this belongs to the stage two;
S6 while S5 carries out, the next S1 that can carry out according to main equipment from equipment and carry out S4.
Differently from other on-chip bus agreement be, other on-chip bus need an independent bus application link, and after bus grant, equipment occupies bus, send address signal, control signal and read and write data; And in the present invention, bus application and address, control signal are sent as the stage one simultaneously, as long as there is no the application vector of corresponding main equipment in current request priority queue, then automatically enter the stage two, transmission is write data or is received read data, if both sides' handshake effectively, terminates this request (except burst operation).
The operating cycle of each equipment is not identical, the concrete operations time by main equipment and bus marco, select the transmission time between logic to determine.The Signal transmissions of main equipment exceedes the cycle of Current bus frequency requirement to the time needed for certain specific structure, then this equipment will be downconverted to corresponding frequency sampling automatically from the data of bus and handshake.Receive the burst request of multi-cycle path main equipment when one from equipment, be also automatically downconverted to corresponding frequency from equipment and carry out data and handshake sampling.
Fig. 6 is main equipment and the interface framework from equipment in the present invention.Wherein data bit width is determined according to the actual bit wide demand of equipment, and general bit wide is 16/32/64/128.The control informations such as read/write, burst, main equipment time sequence information are at least comprised in control signal (Ctrl).From the chip selection signal (Sel) of equipment for from equipment group, if certain moderator corresponding single from equipment, then should need not this signal from equipment.
Table 1 is the specific descriptions to master-slave equipment interface signal.
Table 1
Sequential chart shown in Fig. 7, be for certain from equipment (group) and corresponding requests queue for time empty, certain main equipment is to this accessing time sequence figure from equipment (group).In figure, main equipment have issued four non-burst read/write requests continuously, and wherein SValid signal is by the handshake sent from equipment, and whether bus and main equipment terminate current operation by reading this signal determination current data, or maintain the data in a upper cycle.Wherein Req signal represents that this main equipment current proposes once effective bus application, and this signal is mainly as one of enable signal of joining the team of request priority queue 201, if this request is not authorized to, then can enter in request queue.Because the request for address C cannot respond in time in figure, main equipment is write while data export in maintenance, also needs to maintain its request to address D, because current request cannot enter queue when SValid signal is low.
Shown in Fig. 8 be for certain from equipment (group) and corresponding requests queue for time empty, the time diagram of two main equipments handing-over buses.In figure, two main equipments send bus request respectively in two cycles of continuous print, and the right to use obtaining bus of N-free diet method smoothly.
Fig. 9 is that the main equipment in a binary cycle path and a monocycle path uses bus to carry out the sequential chart read and write mutually.Wherein suffix is that the signal of " _ p1 " represents the value of this bars near output terminal, and " _ p2 " represents the value near input end." WData#1_p1 " represents the write data line near main equipment 1, and after these data enter second round, the selector switch through moderator drives " WData " bus; " RData#1_p2 " represents near the read data line of main equipment 1, is " RData " bus at the extended line of only main equipment 1 section.As can be seen from the figure, the main equipment in binary cycle path when initiating non-burst request, to identical with the main equipment in monocycle path with the holding time of bus from equipment.But this multi-cycle path main equipment needs use, and four bus cycles just can confirm to terminate this bus access, then carry out next bus application.
Figure 10 is that sequential and bus-handover schematic diagram are write in a burst.In figure, main equipment 1 is initiated burst write request and is responded, and provides burst end signal " BLast " terminate burst with main equipment.When burst transfer, main equipment and all need to provide handshake from equipment, " MValid " " SValid " signal namely in figure, as long as one of them signal is low, just represents current transmission data invalid, needs to transmit current data again.Further illustrate the competition of simple bus in figure, carry out in burst transfer process at main equipment 1, main equipment 2 proposes bus application, and because bus is hurried, bus is low to the handshake of main equipment 2, so main equipment needs to maintain data, until handshake is high.While main equipment 1 provides burst end signal, main equipment can send simultaneously for this from equipment another request, in the present invention, due to Request Priority queue 201, bus can the request of preferential corresponding main equipment 2, and then second of corresponding main equipment 1 request.
Figure 11 is the burst transfer sequential chart of two periodic path.As can be seen from the figure, substantially be that two bus cycles do not transmit data, but apply for that signal, handshake, burst end signal are all provide with monocyclic form, so after data send, sample from the second clock cycle (containing) handshake, effectively then next cycle sends new data.So the transmission time of data is for being more than or equal to for 2 cycles, instead of the positive integer of 2 doubly.It is worth mentioning that, if be high-speed equipment from equipment in two equipment of multi-cycle path transmission, do not advocate and use the mode of burst transfer to transmit, the bus access mode of suggestion non-burst, so can not have an impact to the operational efficiency from equipment.
Figure 12 is the sequential chart that multiple main equipment competes a bus simultaneously.What illustrate in figure is that three main equipments are to the same competition from equipment group.Apply for for while main equipment 1,2,3, first bus responds the request of main equipment 1, and then the request of main equipment 2,3 will enter Request Priority queue 201.Although second operating cycle main equipment 1 have issued again an application, owing to also having the application of main equipment 2,3 in application queue, so second of main equipment 1 application will enter request queue.The right to use of the second period of bus, passes through main equipment 2, and the request arbitration of 3, authorizes main equipment 2.When main equipment waits for bus grant, if write operation, demand main equipment maintains the data writing FPDP, knows and samples from the effective handshake of bus.
Above specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; these are only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (11)
1. a SOC (system on a chip) bus (10), for main equipment with from the communication between equipment, it is characterized in that, comprise Request Priority queue (201), moderator group (202), address and control signal selector switch (204), internet (206) and address decoder (207); Wherein,
Described main equipment sends bus request signal to described address decoder (207), and sends corresponding address signal and control signal to described address and control signal selector switch (204);
Described address decoder (207), according to described bus request signal, sends to moderator group and immediately applies for vector, described instant application vector is sent to Request Priority queue (201) simultaneously;
Described instant application vector latches by described request priority query (201), generate chip selection signal, and described chip selection signal is sent to described internet (206), meanwhile, generate queue application vector and be sent to described moderator group (202);
Described moderator group (202) sends arbitration result signal to described address and control signal selector switch (204) and described internet according to described application signal;
The address signal of described address and control signal selector switch (204) main equipment according to described arbitration result signal behavior and control signal, and transfer to described from equipment;
Described internet (206), and to control from equipment to the data in main equipment direction and handshake according to described chip selection signal to from the data of device orientation and handshake according to described arbitration result signal behavior main equipment.
2. SOC (system on a chip) bus (10) according to claim 1, it is characterized in that, also comprise an address and control signal storer (203), described moderator group (202) also returns an authorization signal to Request Priority queue (201), make the described bus request signal of described main equipment enter described request priority query (201) according to described authorization signal, make the address signal of described main equipment and described control signal enter address and control signal storer (203) simultaneously.
3. SOC (system on a chip) bus (10) according to claim 2, it is characterized in that, also comprise a first selector (208), when described request priority query (201) is empty, described request priority query (201) transmit queue spacing wave is to the control end of described first selector, the described first selector address signal of directly selecting described main equipment to send and control signal to described address and control signal selector switch (204), otherwise, described first selector is selected the address signal in described address and control signal storer (203) and is controlled signal to described address and control signal selector switch (204).
4. SOC (system on a chip) bus (10) according to claim 1, it is characterized in that, also comprise a second selector, when described request priority query (201) is empty, described request priority query (201) transmit queue spacing wave is to the control end of described second selector, the instant application vector that described second selector directly selects address decoder (207) to send is to described moderator group (202), otherwise, the queue application vector that described second selector selects described request priority query (201) to send is to described moderator group (202).
5. SOC (system on a chip) bus (10) according to claim 1, is characterized in that, described moderator group (202) comprises at least one moderator, and the quantity of described moderator is identical with the described quantity from equipment.
6. SOC (system on a chip) bus (10) according to claim 5, is characterized in that, the arbitrated logic in described moderator is priority encoder.
7. SOC (system on a chip) bus (10) according to claim 1, it is characterized in that, also comprise arbitration result register (205), described moderator group (202) first sends described arbitration result signal to described arbitration result register (205), then by described arbitration result register (205), arbitration result signal is sent to described internet (206).
8. SOC (system on a chip) bus (10) according to claim 1, it is characterized in that, described request priority query (201) comprising: first memory (501), second memory (502) and the 3rd storer (503), wherein, described first memory (501) is for storing effective address decoding value, described second memory (502) is for storing from the maximum preferred value of equipment group, and described 3rd storer (503) is for storing main equipment preferred value.
9. SOC (system on a chip) bus (10) according to claim 1, it is characterized in that, it carries out Signal transmissions by following agreement:
Described main equipment, after this cycle sends signal, without the need to waiting for authorization signal, directly sending at next cycle and writing data to described from equipment, and monitoring the described handshake sent from equipment.
10. SOC (system on a chip) bus (10) according to claim 1, is characterized in that, its Signal transmissions described main equipment being sent by one or more clock period is extremely described from equipment.
11. SOC (system on a chip) buses (10) according to claim 1, it is characterized in that, with main equipment time sequence information in the control signal that described main equipment sends, the described response cycle from equipment is controlled, to mate described main equipment and described transfer rate between equipment by described main equipment time sequence information.
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