CN100510640C - Adjustable sample-taking velocity high speed high-accuracy data collection card - Google Patents
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- CN100510640C CN100510640C CN 200710191032 CN200710191032A CN100510640C CN 100510640 C CN100510640 C CN 100510640C CN 200710191032 CN200710191032 CN 200710191032 CN 200710191032 A CN200710191032 A CN 200710191032A CN 100510640 C CN100510640 C CN 100510640C
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Abstract
A high-speed high-precision data collecting card with adjustable sampling speed relates to a special device which collects weak signal with an extremely high Signal-to-Noise and an extremely high sampling speed. The output end of an impedance matching network (1) is connected with the input end of a difference convertor (2). The output end of the difference convertor (2) is connected with the simulating input end of a high-speed high-precision data convertor (3). The output of a low phase noise clock source (4) is respectively connected with the clock input end of the high-speed high-precision data convertor (3) and the input end of a clock buffer driver (6). The high-speed high-precision data convertor (3) is connected with the input end of a high-speed FIFO (5). The data output end in the high-speed FIFO (5) is connected with the data input end of a CPLD control circuit (7). The output of the clock buffer driver (6) is connected with the CPLD control circuit (7) and an interface circuit (8) by passing through an isolated clock signal with the same frequency. The CPLD control circuit (7) outputs the clock from the clock buffer driver (6) after frequency demultiplication and is connected with the input end of the interface circuit (8).
Description
Technical field
The present invention is a kind of data collecting card that is used for data acquisition system (DAS), especially a kind of specialized equipment with high signal to noise ratio (S/N ratio), high sampling rate collection feeble signal.
Background technology
High speed high-accuracy data collection card be a kind of with high signal to noise ratio (S/N ratio), high sampling rate with collection of simulant signal and be quantified as the specialized equipment of data.Can accurately recover, detect and measure the feeble signal of being flooded, be particularly suitable for fields such as the application of very noisy input, medical biotechnology parameter measurement, radar, sonar signal reception, Fibre Optical Sensor data processing by noise background.
Existing data collecting card mainly contains following several deficiency:
At first, speed index and precision index are realized seldom simultaneously.According to our investigation, sampling rate reaches the data collecting card of 100MSPS, and quantified precision is all below 10 basically.And the data collecting card of 14 above quantified precisions, its sampling rate seldom can be accomplished more than the 10MSPS.By 2006, the best index of the high speed high-accuracy data collection card of Asian-Pacific area commercialization was 14 quantified precisions, 50MSPS.This is for many high-end applications, and performance is appointed inadequate slightly.
Secondly, existing various commercial data capture cards are often only paid attention to quantified precision, and do not consider actual acquisition result's precision.Owing to ignored the peculiar character of high speed high-accuracy data collection, there are many unreasonable parts in system design, causes the degeneration of performance, and realistic accuracy is far below quantified precision.
Summary of the invention
Technical matters: the objective of the invention is at sampling rate more than or equal to 100MHz, quantified precision is more than or equal to 16 high-performance data acquisition system, for it provides a kind of high speed high-accuracy data collection card of sample rate adjusted.
Technical scheme: the present invention has provided sampling rate more than or equal to 100MHz, and quantified precision is more than or equal to the implementation method of 16 high-performance data capture card.
This data collecting card comprises impedance matching network, differential transformation device, A/D converter with high speed and high precision, low phase noise clock source, high speed FIFO, clock buffering driver, CPLD control circuit, interface circuit; The simulating signal of being gathered enters the input end of impedance matching network, the input end of the output termination differential transformation device of impedance matching network, the analog input end of the output termination A/D converter with high speed and high precision of differential transformation device, low phase noise clock source produces the output of high accuracy clock signal and connects the input end of clock of A/D converter with high speed and high precision and the input end of clock buffering driver respectively, the input end that data that A/D converter with high speed and high precision produces and synchronous clock connect high speed FIFO, the defeated data input pin that connects the CPLD control circuit that brings out of data in the high speed FIFO, the output of clock buffering driver connects CPLD control circuit and interface circuit through the same frequency clock signal of isolating, the CPLD control circuit receives the instruction from interface circuit, the clock that comes the self-clock buffering driver is done the input end of output connection interface circuit behind the frequency division.
The peripheral interface of differential transformation device is made up of signal input port, differential signal positive output port, differential signal negative output port, and this transducer comprises AC coupling pattern and DC coupling pattern; Wherein under the AC coupling pattern, signal output port connects differential signal positive output port and differential signal negative output port by radio-frequency coil; Under the DC coupling pattern, signal output port connects differential operational amplifier and connects positive input terminal, and differential signal positive output port connects the differential operational amplifier positive output end, and differential signal negative output port connects the differential operational amplifier negative output terminal.
The peripheral interface of A/D converter with high speed and high precision is made up of differential signal positive input terminal, differential signal negative output terminal, sampling clock input end, synchrodata output terminal, synchronous clock output terminal, A/D converter with high speed and high precision is under the control of sampling clock input end input clock, the simulating signal of importing on differential signal positive input terminal, the differential signal negative output terminal is gathered, the result who gathers, under the control of synchronous clock output terminal output clock, export by the synchrodata output terminal.
The performance parameter in low phase noise clock source must satisfy the constraint of following two formulas,
SNR＝-20log(2π?f
ana?logt
jtter)dB
Integration=10log (2 πs of phase noise on the broadband
2f
Clk 2t
Jitter 2)
Wherein, SNR is the output signal-to-noise ratio of data acquisition system (DAS), f
AnalogIt is the frequency of analog input signal; t
JtterBe the shake of clock in time domain, f
ClkFrequency for sampling clock.
The peripheral interface of high speed FIFO is made up of first input end, second input end, signal input end, data output end, high speed FIFO buffer memory under the control of the second input end input clock is exported data in buffer under the clock control of signal input end input from the data of first input end from data output end.
The clock buffering driver is made up of gate circuit at a high speed, and its frequency of operation is higher than 100MHz, but its fan out capability drive CPLD control circuit.
The CPLD control circuit is made up of data input module, clock load module, counter, data cache module, clock distribution module, frequency divider, control signal generation module, the output termination data buffer of data input module, the output termination clock distribution module of clock load module, the output termination data buffer of counter, the output terminal of clock distribution module connects frequency divider and control signal generation module respectively.
The peripheral interface of interface circuit is made up of instruction output end, input end of clock, data input pin, control signal output ends is an instruction output end, the working method of control CPLD control circuit, the data of interface circuit on reading of data input end under the control of input end of clock input clock.
Described data buffer is done optionally and is abandoned the data of input, and the method that abandons comprises the output of averaging, get match value exports, and has reduced the sample frequency of data collecting card indirectly and has promoted the precision of collection result.
Beneficial effect: the present invention uses well-designed low phase noise clock 4 as sampling clock, and 3 pairs of simulating signals of control a slice A/D converter with high speed and high precision are gathered.Analog-to-digital result does buffer memory by high speed FIF05.7 pairs of data from high speed FIFO 5 of CPLD control circuit process, and according to the difference of setting sampling rate, do not abandon or selectivity abandons data.After 7 pairs of data processing of CPLD control circuit, export interface circuit 8 to, the result of data acquisition is delivered to the equipment in the external world from high speed FIFO 5.
The present invention has provided the highest sampling rate more than or equal to 100MHz, and quantified precision is more than or equal to the implementation of 16 high-performance data capture card.When guaranteeing quantified precision, proposed to regulate the new method of sampling rate.With to use digital circuit directly to regulate sampling clock in the traditional design different, the present invention abandons the data of analog to digital converter output by selectivity, has realized the adjusting to sampling rate.
Description of drawings
Fig. 1 is a schematic block circuit diagram of the present invention.
Fig. 2 is the AC coupling pattern of differential transformation circuit 2.
Fig. 3 is the DC coupling pattern of differential transformation circuit 2.
Fig. 4 is the peripheral connection layout of A/D converter with high speed and high precision 3.
Fig. 5 is the peripheral connection layout of high speed FIFO 5.
Fig. 6 is the internal frame diagram of CPLD control circuit 7.
Fig. 7 is the peripheral connection layout of interface circuit 8.
Embodiment
The present invention is by impedance matching network 1, differential transformation device 2, A/D converter with high speed and high precision 3, low phase noise clock source 4, high speed FIFO 5, clock buffering driver 6, CPLD control circuit 7, interface circuit 8.
The simulating signal of being gathered enters the input end of impedance matching network 1, and the output of impedance matching network 1 connects the input of differential transformation device 2.Differential transformation device 2 is transformed to input signal the signal of difference to exporting to improve the inhibition ability to common mode interference.The output of differential transformation device 2 connects the analog input end of A/D converter with high speed and high precision 3.Low phase noise clock source 4 produces the output of high accuracy clock signal, connects the input end of clock of A/D converter with high speed and high precision 3 and the input end of clock buffering driver 6 respectively.A/D converter with high speed and high precision 3 is done collection to the output differential pair signal of differential transformation device 2 under the control of the high accurate clock signal of low phase noise clock source 4 generations.A/D converter with high speed and high precision 3 turns to digital quantity output with the result quantities that collects.The input end that data that A/D converter with high speed and high precision 3 produces and synchronous clock connect high speed FIFO 5.High speed FIFO 5 reads the data of A/D converter with high speed and high precision 3 outputs under the control of A/D converter with high speed and high precision 3 synchronous clocks.The high accurate clock signal that clock buffering driver 6 buffering low phase noise clock sources 4 produce, the same frequency clock of output through isolating, this clock signal connects CPLD control circuit 7 and interface circuit 8.CPLD control circuit 7 receives the instruction from interface circuit 8, sets sampling rate, exports the input end of the clock connection interface circuit 8 behind the frequency division after the clock that comes self-clock buffering driver 6 is done frequency division.CPLD control circuit 7 reads data in the high speed FIFO 5 with the speed identical with A/D converter with high speed and high precision 3 picking rates.The defeated data input pin that connects CPLD control circuit 7 that brings out of data in the high speed FIFO 5.CPLD control circuit 7 according to sampling rate to from the optionally buffer memory output of the data of high speed FIFO 5.CPLD control circuit 7 outputs control signals to the input end of interface circuit 8, and control interface circuit 8 is taken the data of CPLD control circuit buffer memory output away.
The high speed high-accuracy data collection system is extremely responsive to the quality of sampling clock.Data acquisition is an optical mixing process from seeing in essence, any noise, distortion and the shake of sampling clock all can with mixed by acquired signal.Traditional design is not done deep research to the requirement of clock performance, often only pays attention to the frequency stability of clock, uses digital circuit to produce sampling clock.And the clock that produces by digital circuits such as frequency divider, DDS, its shake is very serious.The validity of data acquisition system (DAS) quantified precision can be weighed by output signal-to-noise ratio.The relation of the output signal-to-noise ratio of data acquisition system (DAS) and sampling clock shake is provided by formula 1.
SNR＝-20log(2πf
ana?logt
jitber)dB (1)
Wherein, SNR is the output signal-to-noise ratio of data acquisition system (DAS), f
AnalogIt is the frequency of analog input signal; t
JtterBe the shake of clock in time domain, the relation of the phase noise of itself and clock is provided by formula 2.
Integration=10log (2 πs of phase noise on the broadband
2f
Clk 2t
Jitter 2) (2)
F wherein
ClkFrequency for sampling clock.Obviously in order to guarantee the performance of data acquisition system (DAS), the phase noise of sampling clock is necessary may be low.More than or equal to 100MHz, quantified precision is more than or equal to 16 high-performance data capture card for sampling rate, and the phase noise of sampling clock should be lower than-165dBc/Hz.This can obtain by well-designed low phase noise sampling clock source 4.
Because the frequency in low phase noise sampling clock source 4 can't be regulated usually, we propose a kind of scheme of brand-new realization sample rate adjusted.Press some cycles by the CPLD control circuit, optionally abandon a part of data, reach the purpose of regulating sampling rate indirectly.Because the data number that abandons can only be an integer.The frequency in low phase noise sampling clock source 4 is always regulated the integral multiple of post-sampling frequency.Especially, as if the discarding method of well-designed data, can further improve the signal to noise ratio (S/N ratio) of output signal.For example, if sample frequency is the 1/N of low phase noise sampling clock source 4 frequencies, then getting an adjacent N data is one group, output after every group data are averaged.The theoretical demonstration, if noise is Gaussian distribution, then adjacent two data is average, just can bring the signal to noise ratio (S/N ratio) of 6dB to promote.
Comprise impedance matching network 1 in the present embodiment, differential transformation device 2, A/D converter with high speed and high precision 3, low phase noise clock source 4, high speed FIFO 5, clock buffering driver 6, CPLD control circuit 7, interface circuit 8.Wherein, differential transformation device 2 is by interchange, DC coupling difference, the radio-frequency coil that uses is ADT1-1WT, use differential operational amplifier to be AD8138, A/D converter with high speed and high precision 3 is AD9460, and low phase noise clock source 4 is a constant-temperature crystal oscillator, high speed FIF05 is IDT72V2103, it is EPF10KI0A that the clock buffering drives 6, and CPLD control circuit 7 is EPF10K30A, and interface circuit 8 is USB chip CY7C68013.
The simulating signal that 1 pair of quilt of impedance matching network is gathered is done 50 Ω impedance matchings, prevents distorted signals.The output of impedance matching network 1 connects the input end of differential transformation device 2, wherein by interchange, DC coupling, two kinds of connections of Fig. 2, Fig. 3 is arranged respectively.Use radio-frequency coil to be connected into the AC differential transducer among Fig. 2.Use differential operational amplifier to constitute direct current differential transformation device among Fig. 3.Differential transformation device input end 2-1 is arranged in the differential transformation device 2, and the output differential signal is to 2-2,2-3.Two paths of differential signals is to the A/D converter with high speed and high precision input end 3-1,3-2 of input A/D converter with high speed and high precision 3.A/D converter with high speed and high precision 3 also comprises sampling clock input end 3-3, connects the output terminal in low phase noise clock source 4.The synchronous clock of A/D converter with high speed and high precision 3 and output data connect first input end 5-1, second input end 5-2 of high speed FIFO 5 by synchrodata output terminal 3-4,3-5 outputs of synchronous clock output terminal.Clock buffering driver 6 uses the gate circuit of a high speed to realize.The data output end 5-4 of high speed FIFO 5 connects the input end of CPLD control circuit 7, connects the data input module 7-1 of CPLD control circuit 7 inside, and data input module 7-1 connects data buffer 7-4.The output termination CPLD control circuit 7 clock internal load modules 7-2 of clock buffering driver 6.Clock load module 7-2 connects clock distribution module 7-5.The data 8-1 that counter 7-3 receives from interface circuit 8, set the data relevant with sampling rate and abandon at interval, do local counting, count results connects data buffer 7-4, control data buffer 7-4 after at regular intervals data being averaged is exported averaged result.Data after data buffer 7-4 will abandon through selectivity export the data input pin 8-3 of interface circuit 8 to.Clock distribution module 7-5 clock of self-clock load module 7-2 in the future is divided into two-way, wherein one the tunnel connects frequency divider 7-6, and the signal of frequency divider 7-6 after with frequency division exports the input end of clock 8-2 of interface circuit to as the clock of control interface circuit 8.Another road of clock distribution module 7-5 exports control signal generation module 7-8 to.Control signal generation module 7-8 generates the control signal of control high speed FIFO and reads clock, connects the signal input end 5-3 of high speed FIFO 5.
Claims (9)
1. the high speed high-accuracy data collection card of a sample rate adjusted is characterized in that this data collecting card comprises impedance matching network (1), differential transformation device (2), A/D converter with high speed and high precision (3), low phase noise clock source (4), high speed FIFO (5), clock buffering driver (6), CPLD control circuit (7), interface circuit (8); The simulating signal of being gathered enters the input end of impedance matching network (1), the input end of the output termination differential transformation device (2) of impedance matching network (1), the analog input end of the output termination A/D converter with high speed and high precision (3) of differential transformation device (2), low phase noise clock source (4) produces the output of high accuracy clock signal and connects the input end of clock of A/D converter with high speed and high precision (3) and the input end of clock buffering driver (6) respectively, the input end that data that A/D converter with high speed and high precision (3) produces and synchronous clock connect high speed FIFO (5), data output end in the high speed FIFO (5) connects the data input pin of CPLD control circuit (7), clock buffering driver (6) output connects CPLD control circuit (7) and interface circuit (8) through the same frequency clock signal of isolating, CPLD control circuit (7) receives the instruction from interface circuit (8), the clock that comes self-clock buffering driver (6) is done the input end of output connection interface circuit (8) behind the frequency division.
2. the high speed high-accuracy data collection card of sample rate adjusted according to claim 1, the peripheral interface that it is characterized in that differential transformation device (2) is made up of signal input port (2-1), differential signal positive output port (2-2), differential signal negative output port (2-3), and this transducer comprises AC coupling pattern and DC coupling pattern; Wherein under the AC coupling pattern, signal output port (2-1) connects differential signal positive output port (2-2) and differential signal negative output port (2-3) by radio-frequency coil; Under the DC coupling pattern, signal output port (2-1) connects differential operational amplifier and connects positive input terminal, differential signal positive output port (2-2) connects the differential operational amplifier positive output end, and differential signal negative output port (2-3) connects the differential operational amplifier negative output terminal.
3. the high speed high-accuracy data collection card of sample rate adjusted according to claim 1, the peripheral interface that it is characterized in that A/D converter with high speed and high precision (3) is by differential signal positive input terminal (3-1), differential signal negative output terminal (3-2), sampling clock input end (3-3), synchrodata output terminal (3-4), synchronous clock output terminal (3-5) is formed, A/D converter with high speed and high precision (3) is under the control of sampling clock input end (3-3) input clock, to differential signal positive input terminal (3-1), differential signal negative output terminal (3-2) is gone up the simulating signal of input and is gathered, the result who gathers, under the control of synchronous clock output terminal (3-5) output clock, export by synchrodata output terminal (3-4).
4. the high speed high-accuracy data collection card of sample rate adjusted according to claim 1 is characterized in that the performance parameter in low phase noise clock source (4) must satisfy the constraint of following two formulas,
SNR＝—20log(2πf
ana?logt
jitter)dB
Integration=10log (2 πs of phase noise on the broadband
2f
Clk 2t
Jitter 2)
Wherein, SNR is the output signal-to-noise ratio of data acquisition system (DAS), f
AnalogIt is the frequency of analog input signal; t
JtterBe the shake of clock in time domain, f
ClkFrequency for sampling clock.
5. the high speed high-accuracy data collection card of sample rate adjusted according to claim 1, the peripheral interface that it is characterized in that high speed FIFO (5) is made up of first input end (5-1), second input end (5-2), signal input end (5-3), data output end (5-4), high speed FIFO (5) buffer memory under the control of second input end (5-2) input clock is exported data in buffer under the clock control of signal input end (5-3) input from the data of first input end (5-1) from data output end (5-4).
6. the high speed high-accuracy data collection card of sample rate adjusted according to claim 1 is characterized in that clock buffering driver (6) is made up of gate circuit at a high speed, and its frequency of operation is higher than 100MHz, its output energy drive CPLD control circuit (7).
7. the high speed high-accuracy data collection card of sample rate adjusted according to claim 1, it is characterized in that CPLD control circuit (7) is by data input module (7-1), clock load module (7-2), counter (7-3), data cache module (7-4), clock distribution module (7-5), frequency divider (7-6), control signal generation module (7-7) is formed, the output termination data cache module (7-4) of data input module (7-1), the output termination clock distribution module (7-5) of clock load module (7-2), the output termination data cache module (7-4) of counter (7-3), the output terminal of clock distribution module (7-5) connect frequency divider (7-6) and control signal generation module (7-8) respectively.
8. the high speed high-accuracy data collection card of sample rate adjusted according to claim 1, the peripheral interface that it is characterized in that interface circuit (8) is made up of instruction output end (8-1), input end of clock (8-2), data input pin (8-3), control signal output ends is an instruction output end (8-1), the working method of control CPLD control circuit (7), the data of interface circuit (8) on reading of data input end (8-3) under the control of input end of clock (8-2) input clock.
9, the high speed high-accuracy data collection card of sample rate adjusted according to claim 7, it is characterized in that described data buffer (7-4), data to input are done optionally and are abandoned, the method that abandons comprises the output of averaging, get match value output, reduced the sample frequency of data collecting card indirectly and promoted the precision of collection result.
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| CN102968513B (en) * | 2012-11-28 | 2015-08-26 | 南京理工大学 | A kind of high-speed digital signal gather and analysis method based on FPGA |
| CN103067005A (en) * | 2012-12-27 | 2013-04-24 | 中国电子科技集团公司第三十四研究所 | Large dynamic medium-high frequency analog signal digitization conversion circuit |
| CN105549453A (en) * | 2014-11-04 | 2016-05-04 | 西安法拉第电子科技有限公司 | High-precision re-constructible digital delay line and time-delay method thereof |
| CN106559027A (en) * | 2015-09-17 | 2017-04-05 | 北汽福田汽车股份有限公司 | For the data isolation acquisition system and method and vehicle of vehicular electric machine controller |
| CN106230481A (en) * | 2016-08-31 | 2016-12-14 | 国网江西省电力公司电力科学研究院 | A kind of power line interference signal extraction and synchronous playback means |
| CN106595874B (en) * | 2016-11-30 | 2019-08-20 | 中国航空工业集团公司洛阳电光设备研究所 | A kind of high s/n ratio infrared detector ADC sample circuit |
| CN108572272A (en) * | 2017-12-26 | 2018-09-25 | 深圳市鼎阳科技有限公司 | A kind of method and multimeter improving multimeter measurement accuracy |
| CN112242849B (en) * | 2019-07-18 | 2023-09-22 | 纮康科技股份有限公司 | Analog-to-digital converter capable of adjusting operation frequency |
| CN113590515B (en) * | 2021-07-23 | 2022-09-27 | 上海锐星微电子科技有限公司 | Signal transmission loss compensation circuit, integrated circuit and transmission system |
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