CN100424654C

CN100424654C - Access method of matrix data and storage device of the matrix data

Info

Publication number: CN100424654C
Application number: CNB2005100617036A
Authority: CN
Inventors: 严晓浪; 秦兴; 刘大可; 葛海通; 罗晓华
Original assignee: Hangzhou C Sky Microsystems Co Ltd
Current assignee: Hangzhou C Sky Microsystems Co Ltd
Priority date: 2005-11-25
Filing date: 2005-11-25
Publication date: 2008-10-08
Anticipated expiration: 2025-11-25
Also published as: CN1971537A

Abstract

A matrix data access method is disclosed that includes following steps: the data storage space containing the presetting high-dimensional matrix is processed by dimensionality reduction to convert into two-dimensional matrix data storage space, and the two-dimensional matrix data storage space is divided into the separated two-dimensional matrix data storage subspace; the storage type of data in the high-dimensional matrix data storage subspace: the high-dimensional matrix is reduced to low-dimensional matrix, the storage type in every two-dimensional matrix data storage subspace: from left to right, from upper to lower, stored according to the modulus; the two-dimensional sub matrix data storage space is mapped to several physical memories in the data storage model, the data in data block of the two-dimensional sub matrix data storage space is read from the corresponding address of every memory in the several memories according to the matching requirements. The invention also provides a matrix data storage device. The invention is high storage effect and can satisfy the requirements for storing the various types of data.

Description

A kind of access method of matrix data and matrix data memory storage thereof

(1) technical field

The present invention relates to a kind of access method of matrix data and matrix data memory storage thereof.

(2) background technology

Vector processor is used in fields such as multimedia processing and science calculating widely, and the data object of its operation mostly is dimension difference, the different matrix data of data type, so, realize that matrix data access efficiently is very important.

As Chinese invention patent 95103825.7, patent name is that utilizing linear transformation carries out Flame Image Process ground parallel memory device, disclose a kind of use linear transformation and carried out Flame Image Process ground parallel memory device, comprise a plurality of address calculation, a plurality of storage unit and omega network and shift circuit unit, described address calculation is suitable for producing each address corresponding to a module in the memory module according to the memory module number of access mode, reference coordinate and corresponding memory module; Described storage unit is suitable for receiving the address that each corresponding address calculation and read/write signal produces, and carries out storage, input, the output of real data; Described omega network is suitable for receiving the data from its corresponding storage unit, these data are produced suitable path make its actual treatment that produces the memory module consistent order with the required logical order of a processor, and the path output data by this generation, described shift circuit unit is suitable for that indicated input produces suitable path between each omega network and data terminal according to this access mode.This device is that the data by distribution parallel access suitable in a plurality of memory modules have obtained high parallel performance.In fact this class scheme is exactly parallel as the cost realization by the redundancy of address space between the memory module, graphical dots subclass for some accessible certain geometrical shape such as horizontal line, perpendicular line or square frame, in fact in each memory module, all to a memory address space correspondingly arranged, storage efficiency is lower, and exists and can't come access with horizontal line, perpendicular line, two-dimentional square frame mode on the position arbitrarily one.Though this device overcomes this defective by the twice that the memory module number is increased to the number of image points of access simultaneously, yet its cost is the redundance that has increased memory module again, has reduced storage efficiency.

As Chinese invention patent 01139343.2, patent name is to use the method for storer, two-dimensional data access storer and operation processing equipment, a kind of memory-aided method that makes is disclosed, this method comprises the following steps: to include predetermined two dimensional storage space, it is made of predetermined virtual minimum two-dimensional storage space that forms according to two-dimensional way and that longitudinally arrange with horizontal direction, with each address in described virtual minimum two-dimensional storage space allocate in advance in a plurality of physical storages according to the presumptive address in each definite storer of the mode relevant with the size of described virtual minimum two-dimensional storage; During data in reading described two-dimensional storage space, specify in the described virtual minimum two-dimensional storage read the address and, predetermined read direction is specified in the address of reading with reference to appointment, thereby, read the data in the described virtual minimum two-dimensional storage in the corresponding address of mode from each storer of a plurality of physical storages according to the address of appointment and appointment, when reading of data, also specific data reads access mode, crossed over the edge of the existing scope of comparable data as data, then be modified as the address of tentation data of the edge that is positioned at the existing scope of comparable data and reading of data by data read address in the existing scope that will not be included in comparable data.This method becomes whole two dimensional storage spatial division the bidimensional minimized storage space of a series of N * N, and N is less relatively, the indefinite requirement of required storage size during use on discontented on the one hand full border must cause the inconvenience of storage and the redundancy of storage space; The address computing method are limited in the bidimensional minimized storage space in addition, adopt the flat address computing method, the programming personnel need be scaled one dimension with the bidimensional coordinate offset and just be offset, in the practical application, the being seen bidimensional coordinate offset that is generally of user, and can be positive and negative skew, assess the cost, also inconvenient use flexibly so increased.

(3) summary of the invention

Not high for the date storage method storage efficiency that overcomes prior art, as can not to satisfy the requirement of numerous types of data access deficiency the invention provides a kind of storage efficiency height, can satisfy the access method of matrix data and the matrix data memory storage thereof of the requirement of different types of data access.

The technical solution adopted for the present invention to solve the technical problems is:

A kind of access method of matrix data, this method comprises the following steps: to include predetermined higher dimensional matrix data space, it finally can be converted into a plurality of two-dimensional matrix data spaces through multistage dimension-reduction treatment, each two-dimensional matrix data space can resolve into the independently two-dimentional submatrix data space of a series of mutual logic again, described two-dimentional submatrix is m * n matrix, and m, n are natural number;

Data are taked by the mode of higher-dimension to low-dimensional when described higher dimensional matrix data space is deposited, and take by left-to-right order from top to bottom, the mode of depositing according to mould when depositing in each two-dimentional submatrix data space;

The configuration of described two-dimentional submatrix data space by data model storage is mapped in a plurality of physical storages, and the deploy content of described data model storage comprises: base address, data element width, row span, row span and data model storage;

When the data of the described two-dimentional submatrix data space of access, specify line displacement and the line skew of the first address of the data block in the two-dimentional submatrix data space that needs access with respect to the base address of two-dimentional submatrix data space; And,

Need the orientation of the data block in the two-dimentional submatrix data space of access;

The length that needs the data block in the two-dimentional submatrix data space of access;

Thereby data according to the data block in the two-dimentional submatrix data space that reads the needs access in the appropriate address of above condition from each storer of a plurality of physical storages;

When reading of data, the data of reading from physical storage will pass through data replacement as required so that its reading of data of satisfying the demand order;

When depositing data in, data need in sending into physical storage through data replacement so that it satisfies the order of depositing of needs in the physical storage.

Further, data model storage is the row memory module as described, and under the memory module of being expert at, the orientation of the data block of the access of support is arranged for row, and the maximum data block length that at every turn can carry out access is the storage unit sum that is no more than physical storage.

Perhaps, described data model storage is the row memory modules, and under the row memory module, the orientation of the data block of the access of support is arranged for row, and the maximum data block length that at every turn can carry out access is the storage unit sum that is no more than physical storage.

Again or, described data model storage is a ranks stored interleaved pattern, under ranks stored interleaved pattern, the orientation of the data block of the access of support is arranged for row and row are arranged;

Under ranks stored interleaved pattern, when carrying out access, data to interlock staggered comprising the following steps:

(1), the square matrices zone of forming by the data cell of independently interlocking, described square area is meant that the number of the capable span that comprises equals the line number that this zone comprises on line direction, the number of the described capable span that comprises is staggered amount, and it is no more than the number of the capable span that the storage unit sum of physical storage comprised;

(2), the first line data order in the described square area is remained unchanged;

(3), the data element of last row in span of second line data in the described square area transferred in first row span relevant position go, and original shift a capable span successively backward to the data element the capable span of penult from first row span;

(4), the data element in the capable span of penult of the third line data in the described square area is transferred in first row span relevant position and gone, the data element of last row in span transferred in second capable span relevant position and gone, and original data element from first row span to third from the bottom row span shifts two capable spans successively backward;

(5), and the like, whenever proceed to next line, then moving on to the first data element of row from end of line increases by one, finishes up to the last column that proceeds to described square area.

Described interleave method also comprises: each new row that (6), described square area draw after interlocking can carry out permutation and combination, all can be used as the result of this interlace mode through each result of permutation and combination generation.Determine the correction chart mode such as the following table 1 of ranks stored interleaved pattern according to staggered amount and row span:

Table 1

In the last table, M is the amount of interlocking, and X represents row span xstride, and X (M-1) represents to go span X and product (M-1), and X (M-2) represents row span X and product (M-2), and X (M-3) represents to go span X and product (M-3), and the like;

Each the new row that draws after described square area is interlocked can carry out permutation and combination and form new staggered result, and corresponding correction chart 1 also carries out the permutation and combination of each identical row.

Further again, the first address of the data block in the described two-dimentional submatrix data space that needs access is with respect to the line displacement and the line skew of the base address of two-dimentional submatrix data space, and wherein side-play amount is positive number or negative.

Further, under the memory module of being expert at, physical address computation process is: establishing the base address is base, the first address that needs the data block in the two-dimentional submatrix data space of access is respectively x and y with respect to the line displacement and the line skew of the base address of two-dimentional submatrix data space, the row span is xstride, and the row span is ystride;

The physical address z that needs each data corresponding overall situation in physical storage in the data block in the two-dimentional submatrix data space of access _iCalculating formula is (1):

z _i＝base+(x+i)×xstride+y×ystride (1)

Wherein, i is the distances of each data with respect to the first address of this data block, and unit is the row span;

Physical address z with the overall situation _iCarry out obtaining the needed physical address information of each memory cell after the computing divided by N and the mould of getting N, N is meant the modulus of described physical storage.

Under the row memory module, physical address computation process is: establishing the base address is base, the first address that needs the data block in the two-dimentional submatrix data space of access is respectively x and y with respect to the line displacement and the line skew of the base address of two-dimentional submatrix data space, the row span is xstride, and the row span is ystride;

The physical address z that needs each data corresponding overall situation in physical storage in the data block in the two-dimentional submatrix data space of access _iCalculating formula is (2):

z _i＝base+x×xstride+(y+i)×ystride (2)

Under ranks stored interleaved pattern, physical address computation process is: establishing the base address is base, the first address that needs the data block in the two-dimentional submatrix data space of access is respectively x and y with respect to the line displacement and the line skew of the base address of two-dimentional submatrix data space, the row span is xstride, and the row span is ystride;

The staggered amount of ranks stored interleaved pattern is N, needs each data computing method of physical address corresponding in physical storage of the data block in the two-dimentional submatrix data space of access may further comprise the steps:

(1), the global physical address z of each data correspondence in the data block of calculating unmodified _i:

When the orientation of the data block in the two-dimentional submatrix data space that needs access was arranged for row, calculating formula was (1):

z _i＝base+(x+i)×xstride+y×ystride (1)

When the orientation of the data block in the two-dimentional submatrix data space that needs access was arranged for row, calculating formula was (2):

z _i＝base+x×xstride+(y+i)×ystride (2)

Wherein i is the distances of each data with respect to the first address of this data block, and unit is the row span;

(2), the row-coordinate R (z of each data position in the square area of independently carrying out data interlace of while computational data piece _i) and row coordinate C (z _i):

When the orientation of the data block in the two-dimentional submatrix data space that needs access was arranged for row, calculating formula was (3), (4):

R (z_{i}) = \{\begin{matrix} (x + i) % N \times xstride & (x + i &GreaterEqual; 0) \\ (N + (x + i) % N) \times xstride & (x + i < 0) \end{matrix} - - - (3)

C (z_{i}) = \{\begin{matrix} y % N & (y &GreaterEqual; 0) \\ N + y % N & (y < 0) \end{matrix} - - - (4)

In the following formula, % gets surplus compute sign for dividing exactly;

When the orientation of the data block in the two-dimentional submatrix data space that needs access was arranged for row, calculating formula was (5), (6):

R (z_{i}) = \{\begin{matrix} (x % N) \times xstride & (x &GreaterEqual; 0) \\ (N + x % N) \times xstride & (x < 0) \end{matrix} - - - (5)

C (z_{i}) = \{\begin{matrix} (y + i) % N & (y + i &GreaterEqual; 0) \\ N + (y + i) % N & (y + i < 0) \end{matrix} - - - (6)

(3), obtain correction chart according to different interlace modes, according to the R (z that obtains previously _i) and C (z _i) side-play amount that each data of drawing data block move in interleaved processes, utilize this side-play amount to z _iRevise, thereby draw each data in the data block in the two-dimentional submatrix data space that needs access corresponding global physical address in physical storage;

Tabling look-up according to each data residing row-coordinate and row coordinate in the square matrices zone that the data cell of independently interlocking is formed obtains modified value, i.e. the z that obtains at the physical address computing unit _iThe basis on add the correction side-play amount that checks in the table again and just obtained the pairing revised physical address z ' of revised each data _iEach the new row that draws after square area is interlocked as described can carry out permutation and combination and form new staggered result, and then Dui Ying correction chart 1 permutation and combination of also carrying out identical each row gets final product, and its modified value is identical.

(4), with the physical address z of the overall situation _iCarry out obtaining the needed physical address information of each memory cell after the computing divided by N and the mould of getting N, N is meant the modulus of described physical storage.

Described physical storage is that bytes of memory device unit composes in parallel by a plurality of bit wides, and the numerical value of described base address, data element width, row span, row span is unit with the byte-sized.Bit wide also can be double byte or multibyte, as long as the unit of the content of configuration is consistent with bit wide.

A kind of matrix data memory storage that is used to realize described access method of matrix data, the logical memory space of described matrix data memory storage includes predetermined higher dimensional matrix data space, described higher dimensional matrix data space finally can be converted into a plurality of two-dimensional matrix data spaces through multistage dimension-reduction treatment, each two-dimensional matrix data space can resolve into the independently two-dimentional submatrix data space of a series of mutual logic again, described two-dimentional submatrix is m * n matrix, and m, n are natural number;

Described matrix data memory storage comprises:

Configuration register comprises base register, data element byte wide register, row span register, row span register, cyclic access time number register, cyclic access enable register, data model storage register;

The address calculation group, form by the address calculation that quantity is identical with physical memory cells arc, each address calculation has the module No. of setting, described address calculation is used for according to the content of configuration register and module No., data path according to the controller selection, slave controller reads line displacement and the line skew of the first address of the data block in the two-dimentional submatrix data space that needs access with respect to the base address of two-dimentional submatrix data space, generates the pairing physical address of relevant position data of the data block in the two-dimentional submatrix data space that needs access;

Address conversion module is used for each road physical address information that the address calculation group generates is transformed into the address information of each physical memory cells arc, is transported to each physical memory cells arc; Be the pairing physical memory cells arc of first address that physical address information that 0 address calculation produces calculates the data block in the two-dimentional submatrix data space of needs access simultaneously according to module No., and with this information conveyance to the data replacement module;

The data replacement module, be used for when reading of data, the information of the pairing physical memory cells arc of first address of the data block in the two-dimentional submatrix data space that needs access that produces according to address conversion module is replaced one group of data that the physical memory cells arc group produces, so that its reading of data of satisfying the demand order; And when write data, the information of the pairing physical memory cells arc of first address of the data block in the two-dimentional submatrix data space that needs access that produces according to address conversion module is replaced one group of data sending into the physical memory cells arc group so that it satisfies the order of depositing of needs in the physical storage;

The physical memory cells arc group is made up of one group of parallel physical memory cells arc;

Controller, be used for from the program storage reading command, and instruction resolved the configuration information that is converted into configuration register, or the first address of the data block in the two-dimentional submatrix data space that needs access that will parse from instruction is with respect to the line displacement and the line skew of the base address of two-dimentional submatrix data space, need the orientation of the data block in the two-dimentional submatrix data space of access to be transported to the address calculation group, simultaneously the length decision of the data block in the two-dimentional submatrix data space of access enables the quantity of address calculation as required, the data path of address calculation is selected in the orientation of the data block in the two-dimentional submatrix data space of access as required, and these information also are transported to the address calculation group;

Bus connects the data channel of a plurality of physical memory cells arc groups.

Further, described address calculation comprises:

The physical address computing unit, be used for data path and module No. according to the controller selection, and by the first address of the data block in the two-dimentional submatrix data space that needs access of controller input line displacement and line skew with respect to the base address of two-dimentional submatrix data space, generation needs the pairing global physical address of relevant position data of the data block in the two-dimentional submatrix data space of access, described global physical address is expert at and will be directly exported under the memory module, will be input to the address amending unit and revise back output under ranks stored interleaved pattern;

The row-coordinate computing unit, be used under ranks stored interleaved pattern, according to self module No. and the first address of the data block in the two-dimentional submatrix data space of needs access with respect to the line displacement of the base address of two-dimentional submatrix data space, generate the row-coordinate at relevant position data place in the square area of independently carrying out data interlace of the data block in the two-dimentional submatrix data space that needs access;

Row coordinate Calculation unit, be used under ranks stored interleaved pattern, according to self module No. and the first address of the data block in the two-dimentional submatrix data space of needs access with respect to the line skew of the base address of two-dimentional submatrix data space, generate the row coordinate at relevant position data place in the square area of independently carrying out data interlace of the data block in the two-dimentional submatrix data space that needs access;

The address amending unit, be used under ranks stored interleaved pattern, the row coordinate at the row-coordinate at the global physical address that generates according to the physical address computing unit, data place in the square area of independently carrying out data interlace that the row-coordinate computing unit generates, data place in the square area of independently carrying out data interlace of row coordinate Calculation unit generation is revised, and finally generates revised physical address;

Output data selector is used to select the result of OPADD amending unit or the result of calculation of directly exporting the physics address calculation.

Further again, described data replacement module comprises:

DCU data control unit is used to accept the physical memory cells arc module No. from the first byte place of address conversion module, is translated into the selection signal to the data selected cell, flows to the reading of data selected cell or writes data selection unit;

The reading of data selected cell, it is made up of a group selector identical with physical memory cells arc quantity, each selector switch be used for from a plurality of physical memory cells arc select each sense data according to the selection signal of DCU data control unit so that and all data of the data block that reads of line output needs;

Write data selection unit, it is made up of a group selector identical with physical memory cells arc quantity, and each selector switch is used for selecting to write the data of each physical memory cells arc so that all data of the data block that writes to physical memory cells arc group and line output needs according to the selection signal of DCU data control unit.

Further, described physical memory cells arc is single port storer or multiport memory.

Beneficial effect of the present invention mainly shows: 1, unit storage element in the storage space is redefined, satisfy the indefinite requirement of required storage size in the practical application; 2, convenient storage can not cause the redundancy of storage space; 3, can satisfy the requirement of different types of data access; 4, by logical space effectively being distributed the storage efficiency height; 5, carry out unified interleaving mode definition, further improve storage efficiency; 6, the address computation method can adopt positive and negative skew, and is easy to use, flexible.

(4) description of drawings

Fig. 1 is the figure that sets forth matrix stores space and matrix dimension reduction method;

Fig. 2 is the figure that sets forth two-dimentional submatrix data space;

Fig. 3 is the figure that sets forth for two kinds of one 8 * 8 matrix different staggered results;

Fig. 4 is the figure that sets forth for two kinds of one 4 * 4 matrix different staggered results;

Fig. 5 is a more detailed block diagram of setting forth the matrix data memory storage;

Fig. 6 is a more detailed block diagram of setting forth address calculation;

Fig. 7 sets forth brightness signal Y in the video macro block and two carrier chrominance signal U, the V figure at the storage mode in matrix stores space;

Fig. 8 sets forth brightness signal Y in the video macro block and two carrier chrominance signal U, V at the figure through the storage mode of the logical space after the dimension-reduction treatment;

Fig. 9 is the figure that sets forth the storage mode of carrier chrominance signal U in physical storage in the video macro block;

Figure 10 is the figure that sets forth the distribution of data block by rows in logical space and physical space in the two-dimentional submatrix data space that needs access;

Figure 11 sets forth the matrix data memory storage to be expert at and to read the figure of the process of data line under the memory module;

Figure 12 be set forth need in the standard H.264 4 * 4 luminance block predicted with and the figure of the pixel groups on the pixel groups of top and the left side;

Figure 13 is the figure that set forth to need the distribution of pixel groups in logical space and physical space on the pixel groups of top of luminance block of prediction and the left side;

Figure 14 sets forth the matrix data memory storage reads the process of data line under ranks stored interleaved pattern figure;

Figure 15 sets forth the matrix data memory storage reads the process of a column data under ranks stored interleaved pattern figure.

(5) embodiment

Below in conjunction with accompanying drawing the present invention is further described.

Embodiment 1

As shown in Figure 1, a kind of matrix data storage means, include predetermined higher dimensional matrix data space 1, it finally can be converted into a plurality of two-dimensional matrix data spaces 2 through multistage dimension-reduction treatment, and each two-dimensional matrix data space 2 can resolve into the independently two-dimentional submatrix data space 3 of a series of mutual logic again.Data are taked by the mode of higher-dimension to low-dimensional when described higher dimensional matrix data space 1 is deposited, and take by left-to-right order from top to bottom, the mode of depositing according to mould when depositing in each two-dimentional submatrix data space;

The configuration of described two-dimentional submatrix data space 3 by data access pattern is mapped in a plurality of physical storages, and as shown in Figure 2, the content of configuration comprises: base address, data element width, row span, row span and data model storage;

When the data of the described two-dimentional submatrix data space 3 of access, appointment needs line displacement and the line skew of the first address of the data block in the two-dimentional submatrix data space of access with respect to the base address of two-dimentional submatrix data space, the length that needs the orientation of the data block in the two-dimentional submatrix data space of access and need the data block in the two-dimentional submatrix data space of access, thus read the data of the data block in the two-dimentional submatrix data space that needs access in the appropriate address from each storer of a plurality of physical storages; When reading of data, the data of reading from physical storage will pass through data replacement as required so that its reading of data of satisfying the demand order; When write data, data need in sending into physical storage through data replacement so that it satisfies the order of depositing of needs in the physical storage.

Described data model storage comprises row storage, row storage and ranks stored interleaved.

Under the memory module of being expert at, the orientation of the data block of the access of support has only row to arrange, and the maximum data block length that at every turn can carry out access is the storage unit sum that is no more than physical storage.

Under the row memory module, the orientation of the data block of the access of support is arranged for row, and the maximum data block length that at every turn can carry out access is the storage unit sum that is no more than physical storage.

Under ranks stored interleaved pattern, the orientation of the data block of the access of support comprises that row is arranged and row are arranged, and the two can be supported simultaneously.

The square matrices zone of forming by the data cell of independently interlocking, described square area is meant that the number of the capable span that comprises equals the line number that this zone comprises on line direction, the number of the described capable span that comprises claims staggered amount again, the number of the capable span that it can not be comprised above the storage unit sum of physical storage; The first line data order in the described square area is remained unchanged; The data element of last row in span of second line data in the described square area transferred in first row span relevant position go, and original shift a capable span successively backward to the data element the capable span of penult from first row span; Data element in the capable span of penult of the third line data in the described square area transferred in first row span relevant position go, the data element of last row in span transferred in second capable span relevant position and gone, and original data element from first row span to third from the bottom row span shifts two capable spans successively backward; And the like, whenever proceed to next line, then moving on to the first data element of row from end of line increases by one, finishes up to the last column that proceeds to described square area; Each the new row that draws after the above square area is interlocked can carry out permutation and combination, all can be used as the result of this interlace mode through each result of permutation and combination generation.

As shown in Figure 3, described here, as shown in Figure 4, described here for two kinds of one 4 * 4 matrix different staggered results for two kinds of one 8 * 8 matrix different staggered results.

Under the memory module of being expert at, physical address computation process is: establishing the base address is base, the first address that needs the data block in the two-dimentional submatrix data space of access is respectively x and y with respect to the line displacement and the line skew of the base address of two-dimentional submatrix data space, the row span is xstride, and the row span is ystride;

Need each data in the data block in the two-dimentional submatrix data space of access corresponding global physical address z in physical storage _iCalculating formula is (1):

z _i＝base+(x+i)×xstride+y×ystride (1)

Need each data in the data block in the two-dimentional submatrix data space of access corresponding global physical address z in physical storage _iCalculating formula is (2):

z _i＝base+x×xstride+(y+i)×ystride (2)

z _i＝base+(x+i)×xstride+y×ystride (1)

z _i＝base+x×xstride+(y+i)×ystride (2)

R (z_{i}) = \{\begin{matrix} (x + i) % N \times xstride & (x + i &GreaterEqual; 0) \\ (N + (x + i) % N) \times xstride & (x + i < 0) \end{matrix} - - - (3)

C (z_{i}) = \{\begin{matrix} y % N & (y &GreaterEqual; 0) \\ N + y % N & (y < 0) \end{matrix} - - - (4)

R (z_{i}) = \{\begin{matrix} (x % N) \times xstride & (x &GreaterEqual; 0) \\ (N + x % N) \times xstride & (x < 0) \end{matrix} - - - (5)

C (z_{i}) = \{\begin{matrix} (y + i) % N & (y + i &GreaterEqual; 0) \\ N + (y + i) % N & (y + i < 0) \end{matrix} - - - (6)

The first address of the data block in the described two-dimentional submatrix data space that needs access is with respect to the line displacement and the line skew of the base address of two-dimentional submatrix data space, wherein side-play amount can be a positive number, also can be a negative, numerical value be unit with the byte-sized.

Embodiment 2

A matrix data memory storage that composes in parallel by a plurality of physical memory cells arc, the logical memory space of matrix data memory storage includes predetermined higher dimensional matrix data space, described higher dimensional matrix data space finally can be converted into a plurality of two-dimensional matrix data spaces through multistage dimension-reduction treatment, and each two-dimensional matrix data space can resolve into a series of mutual logic two-dimentional submatrix data space independently again.As shown in Figure 5, described matrix data memory storage comprises:

Configuration register comprises base register, data element byte wide register, row span register, row span register, data model storage register, staggered amount register.

The address calculation group, form by the address calculation that quantity is identical with physical memory cells arc, each address calculation has oneself a module No., described address calculation is used for according to the content of configuration register and module No., data path according to the controller selection, slave controller reads line displacement and the line skew of the first address of the data block in the two-dimentional submatrix data space that needs access with respect to the base address of two-dimentional submatrix data space, generates the pairing physical address of relevant position data of the data block in the two-dimentional submatrix data space that needs access.

Address conversion module is used for each road physical address information that the address calculation group generates is transformed into the address information of each physical memory cells arc, is transported to each physical memory cells arc; Be the unit number that physical address information that 0 address calculation produces calculates the pairing physical memory cells arc of first address of the data block in the two-dimentional submatrix data space of needs access simultaneously according to module No., and with this information conveyance to the data replacement module.

The data replacement module, be used for when reading of data, the information of the pairing physical memory cells arc of first address of the data block in the two-dimentional submatrix data space that needs access that produces according to address conversion module is replaced one group of data that the physical memory cells arc group produces, so that its reading of data of satisfying the demand order; And when write data, the information of the pairing physical memory cells arc of first address of the data block in the two-dimentional submatrix data space that needs access that produces according to address conversion module is replaced one group of data sending into the physical memory cells arc group so that it satisfies the order of depositing of needs in the physical storage.

The physical memory cells arc group is made up of one group of parallel physical memory cells arc 50 ~ 57, and the bit wide of each physical memory cells arc is byte.

Controller, reading command from program storage, and instruction resolved the configuration information that is converted into configuration register, or the first address of the data block in the two-dimentional submatrix data space that needs access that will parse from instruction is with respect to the line displacement and the line skew of the base address of two-dimentional submatrix data space, need the orientation of the data block in the two-dimentional submatrix data space of access to be transported to the address calculation group, simultaneously the length decision of the data block in the two-dimentional submatrix data space of access enables the quantity of address calculation as required, the data path of address calculation is selected in the orientation of the data block in the two-dimentional submatrix data space of access as required, and these information also are transported to the address calculation group;

As shown in Figure 6, described address calculation comprises a physical address computing unit, is used for the data path and the module No. i that select according to controller, and described module No. i and each data are identical apart from the i value with respect to the first address of this data block; And by the first address of the data block in the two-dimentional submatrix data space that needs access of controller input line displacement x and line skew y with respect to the base address of two-dimentional submatrix data space, generation needs the pairing global physical address of relevant position data of the data block in the two-dimentional submatrix data space of access, this physical address is expert at and will be directly exported under the memory module, will be input to the address amending unit and revise under ranks stored interleaved pattern; Also comprise a row-coordinate computing unit, be used under ranks stored interleaved pattern, according to self module No. i and the first address of the data block in the two-dimentional submatrix data space of needs access with respect to the line displacement x of the base address of two-dimentional submatrix data space, generate the row-coordinate at relevant position data place in the square area of independently carrying out data interlace of the data block in the two-dimentional submatrix data space that needs access; Also comprise a row coordinate Calculation unit, be used under ranks stored interleaved pattern, according to self module No. i and the first address of the data block in the two-dimentional submatrix data space of needs access with respect to the line skew y of the base address of two-dimentional submatrix data space, generate the row coordinate at relevant position data place in the square area of independently carrying out data interlace of the data block in the two-dimentional submatrix data space that needs access; Also comprise an address amending unit, be used under ranks stored interleaved pattern, the row coordinate at the row-coordinate at the physical address that generates according to the physical address computing unit, data place in the square area of independently carrying out data interlace that the row-coordinate computing unit generates, data place in the square area of independently carrying out data interlace of row coordinate Calculation unit generation is revised, and finally generates revised physical address; Also comprise an output data selector, be used for selecting the result of OPADD amending unit or the result of calculation of direct output physics address calculation.

Described data replacement module comprises a data control module, acceptance is from the physical memory cells arc module No. at the first byte place of address conversion module, be translated into selection signal, flow to the reading of data selected cell or write data selection unit the data selected cell; Also comprise a reading of data selected cell, it is made up of a group selector identical with physical memory cells arc quantity, each selector switch be used for from a plurality of physical memory cells arc select each sense data according to the selection signal of DCU data control unit so that and all data of the data block that reads of line output needs; Comprise that also writes a data selection unit, it is made up of a group selector identical with physical memory cells arc quantity, and each selector switch is used for selecting to write the data of each physical memory cells arc so that all data of the data block that writes to physical memory cells arc group and line output needs according to the selection signal of DCU data control unit.

Embodiment 3

Present embodiment is applied in access method of matrix data during vision signal handles, and usually one-frame video data is divided into several macro blocks, each independently macro block form according to 4: 2: 0 ratio by brightness signal Y and two carrier chrominance signal U and V.Wherein, luminance signal is one 16 * 16 a matrix, and two carrier chrominance signals are respectively 8 * 8 matrix.Utilize matrix stores device of the present invention can effectively realize this macro block data is stored.

Regard each independent macro block as a four-matrix data space, wherein one dimension is the time, as shown in Figure 7, be arranged in order one group of separate matrix data storage space 1 along time t axle, each three-dimensional data space 1 is made up of three separate two-dimensional matrix data spaces 2, each two-dimensional matrix data space 2 is being deposited a kind of information among Y, U, the V, and wherein a plurality of Y data blocks or a plurality of U data block or a plurality of V data block can be formed a two-dimentional submatrix data space.

This four-matrix data space by dimension-reduction treatment, be converted into the total two-dimensional matrix data space that a plurality of two-dimensional matrix data spaces 2 are formed, i.e. plane logical space, as shown in Figure 8, in each two-dimensional matrix data space 2, depositing a kind of information among Y, U, the V.When the size of the space of planning two-dimensional matrix data space 2, can make logical space reach saturated fully by so a kind of method with being used for depositing length and the length of the wide two-dimensional matrix data space that is designed to be used for to deposit U, V and the wide twice of the two-dimensional matrix data space of Y.

When in physical storage, depositing, deposit order in the same two-dimentional submatrix data space of logical space, data with first row from left to right deposit physical storage successively in earlier, forward the high order end of next line then to, deposit successively according to order from left to right again, as shown in Figure 9,8 * 8 data blocks with carrier chrominance signal U are example, earlier all data with the row of first in the U data block of delegation are deposited in physical storage according to the direction of arrow, store all data according to the direction of arrow then with the row of second in the U data block of delegation, and the like, finish up to the storage of 8 line data.

The first, go the data access address computation of the matrix arrangement under the storage pattern

In computings such as the fast fourier transform of signal Processing, discrete cosine transform, the capital runs into the computing of getting data line simultaneously, will get 4 data of delegation to the example in the register simultaneously from storer with one below be expert at using method under the memory module of this matrix arrangement is described.

If the row span is 1, the row span is 16, the data element width is 1, the first address that needs the data block in the two-dimentional submatrix data space of access is respectively 3 and 1 with respect to the line displacement and the line skew of the base address of two-dimentional submatrix data space, need the orientation of the data block in the two-dimentional submatrix data space of access to arrange for row, needing the length of the data block in the two-dimentional submatrix data space of access is 4, then such data block in residing position in the logical space shown in Figure 10 a.

If the physical memory cells arc group is made up of 8 parallel physical memory cells arc 50 ~ 57, establishing the base address is 4, then need data block in the two-dimentional submatrix data space of access in the residing position of physical space shown in Figure 10 b.

The user needed the configuration register of matrix access device is configured before carrying out data access, to be the user be transported to controller by instruction with configuration information to mode, by controller instruction resolved with the configuration information that draws then and finish configuration to each configuration register.The all data access of configuration back before configuration next time all carried out according to this configuration.

Each configuration register value was respectively data model storage for going memory module after configuration was finished in this example, and row span register is 1, and row span register is 16, and the data element width register is 1.

The user just can finish the access of data by instruction then, in this example, controller needing can to obtain the data block in the two-dimentional submatrix data space of access by the parsing to access instruction first address is respectively 4 and 1 with respect to the line displacement and the line skew of the base address of two-dimentional submatrix data space, need the orientation of the data block in the two-dimentional submatrix data space of access to arrange for row only, needing the length of the data block in the two-dimentional submatrix data space of access is 4.Controller carries out the calculating of physical address with above information conveyance to each address calculation, and the data path of calculated address computing unit selects signal to control the carrying out of its calculating simultaneously.

Preceding four address calculation controlled devices in the address calculation group enable, begin to carry out the physical address calculating operation, as shown in Figure 6, the address information sent here of the controlled device of address calculation and data path select signal to finish following computing with reference to formula (1):

The physical address computing unit is carried out:

z ₀＝4+(3+0)×1+1×16＝23

z ₁＝4+(3+1)×1+1×16＝24

z ₂＝4+(3+2)×1+1×16＝25

z ₃＝4+(3+3)×1+1×16＝26

Wherein subscript 0 ~ 4 is represented the module No. of address calculation, and each physical address computing unit is only carried out the computing of own respective modules number.

Because do not have procession staggered, so row-coordinate computing unit and row coordinate Calculation unit do not carry out work here, data selector 6 gating signals are 1, and the result of calculation of physical address computing unit is directly exported.

As shown in figure 11, the result of calculation of address calculation is transported to address conversion module.Address conversion module carries out result of calculation divided by 8 and the processing of mould 8, here 8 be meant that the physical memory cells arc group is made up of 8 parallel physical memory cells arc, obtain following table 2:

	Divided by 8	Mould 8	Meaning
	Divided by 8	Mould 8	Meaning	z ₀＝23	2	7	The address of output physical memory cells arc 7 is 2 data
z ₁＝24	3	0	The address of output physical memory cells arc 0 is 3 data	z ₀＝23	2	7	The address of output physical memory cells arc 7 is 2 data
z ₁＝24	3	0	The address of output physical memory cells arc 0 is 3 data	z ₂＝25	3	1	The address of output physical memory cells arc 1 is 3 data
z ₃＝26	3	2	The address of output physical memory cells arc 2 is 3 data	z ₂＝25	3	1	The address of output physical memory cells arc 1 is 3 data

Table 2

As shown in figure 11, address conversion module is delivered to corresponding physical memory cells arc 50 ~ 57 respectively with transformation result, and physical memory cells arc arrives the address replacement module according to the address information output data.

Meanwhile, address conversion module is with z ₀Pairing physical memory cells arc numbers 7 is transported to the address replacement module, DCU data control unit in the replacement module of address is sent to the reading of data selected cell with the selection signal that physical memory cells arc numbers 7 transforms into the selector switch of reading of data selected cell, the reading of data selected cell selects signal to be changed by the data of physical memory cell input by these, the data of physical memory cells arc 57 are adjusted to first byte of output, as shown in figure 11, then 4 data of the delegation of reading are sent to register with crossing bus.

So far, the operation of current read data is all finished.

The second, the data access address computation of the matrix arrangement under the row memory module

Basic identical under its process and the row memory module, the address computation formula is with reference to (2).

Three, the data access address computation of the matrix arrangement under the ranks stored interleaved pattern

Below with the example that is predicted as of 4 * 4 luminance block in the infra-frame prediction in the standard H.264 the using method of this matrix arrangement under ranks stored interleaved pattern is described.

Figure 12 shown 4 * 4 luminance block 7 that need predict with and the pixel groups 8 of top and the pixel groups 9 on the left side, luminance block 7 that will be predicted can predict by the data in pixel groups 8 and the pixel groups 9, just need here pixel groups 8 that access simultaneously is in same row again access simultaneously be in the pixel groups 9 of same row.Use matrix arrangement of the present invention to quicken to this accessing operation.

If the row span is 1, the row span is 16, the data element width is 1, Figure 12 mid point M is respectively 3 and 1 with respect to the line displacement and the line skew of the base address of two-dimentional submatrix data space, correspondingly, point A is respectively 4 and 1 with respect to the line displacement and the line skew of the base address of two-dimentional submatrix data space, then such data block in residing position in the logical space shown in Figure 13 a.

If the physical memory cells arc group is made up of 8 parallel physical memory cells arc 50 ~ 57, if the base address is 0, then need data block in the two-dimentional submatrix data space of access in the residing position of physical space shown in Figure 13 b, as can be seen from the figure, because under ranks stored interleaved pattern, data are transformed into the physical space and will interlock from logical space, and staggered amount is 8 in this example.Therefore, in Figure 13 b, five pixels of M, I, J, K, L that are in same row in logical space are in staggered distribution in five different row.

Each configuration register value of back is finished in configuration in this example, and to be respectively data model storage be ranks stored interleaved pattern, and row span register is 1, and row span register is 16, and the data element width register is 1, and the amount register that interlocks is 8.

The user just can finish the access of data by instruction then.

The mode that reads for pixel groups 8 at first is described, controller needing can to obtain the data block in the two-dimentional submatrix data space of access by the parsing to access instruction first address is respectively 4 and 0 with respect to the line displacement and the line skew of the base address of two-dimentional submatrix data space, need the orientation of the data block in the two-dimentional submatrix data space of access to arrange for row only, needing the length of the data block in the two-dimentional submatrix data space of access is 8.Controller carries out the calculating of physical address with above information conveyance to each address calculation, and the data path of calculated address computing unit selects signal to control the carrying out of its calculating simultaneously.

Eight equal controlled devices of address calculation in the address calculation group enable, and begin to carry out the physical address calculating operation, and as shown in Figure 6, address information that the controlled device of address calculation is sent here and data path select signal to finish following computing:

The physical address computing unit is carried out with reference to formula (1):

z ₀＝0+(4+0)×1+1×16＝20

z ₁＝0+(4+1)×1+1×16＝21

z ₂＝0+(4+2)×1+1×16＝22

z ₃＝0+(4+3)×1+1×16＝23

z ₄＝0+(4+4)×1+1×16＝24

z ₅＝0+(4+5)×1+1×16＝25

z ₆＝0+(4+6)×1+1×16＝26

z ₇＝0+(4+7)×1+1×16＝27

Wherein subscript 0 ~ 7 is represented the module No. of address calculation, and each physical address computing unit is only carried out the computing of own respective modules number.

The row-coordinate computing unit is carried out with reference to formula (3):

R(z ₀)＝(4+0)％8×1＝4

R(z ₁)＝(4+1)％8×1＝5

R(z ₂)＝(4+2)％8×1＝6

R(z ₃)＝(4+3)％8×1＝7

R(z ₄)＝(4+4)％8×1＝0

R(z ₅)＝(4+5)％8×1＝1

R(z ₆)＝(4+6)％8×1＝2

R(z ₇)＝(4+7)％8×1＝3

Wherein subscript 0 ~ 7 is represented the module No. of address calculation, and each row-coordinate computing unit is only carried out the computing of own respective modules number.

Row coordinate Calculation unit is owing to the orientation of the data block in the two-dimentional submatrix data space that needs access is arranged for row only, so all row coordinate Calculation unit are carried out with reference to formula (4) simultaneously

C(z)＝0％8＝1

The result of physical address computing unit, row-coordinate computing unit, row coordinate Calculation unit is transported to the correction that the address amending unit carries out the address.Table 3 is for being 8 at staggered amount M, and row span X is that the address amending unit carries out correction chart to the physical address of physical address computing unit generation under 1 the situation, and table 3 is specific embodiments of table 1.The correction of address is carried out with reference to table 3:

Table 3

For example comprise the steps: to table look-up according to pixel B residing row-coordinate 5 and row coordinate 1 in the square matrices zone that the data cell of independently interlocking is formed for the correction of pixel B physical address obtain+1, i.e. the z that obtains at the physical address computing unit ₁Add 1 on=21 the basis again and just obtained the pairing physical address 22 of revised pixel B.

After the same method, each address amending unit is transported to corresponding data selector 6 with the physical address of revised pixel A ~ H respectively, and as shown in Figure 6, data selector 6 gating signals are 0, with result's output of address amending unit.

As shown in figure 14, the result of calculation of address calculation is transported to address conversion module.Address conversion module carries out result of calculation divided by 8 and the processing of mould 8, here 8 be meant that the physical memory cells arc group is made up of 8 parallel physical memory cells arc, obtain following table 4:

	Divided by 8	Mould 8	Meaning
	Divided by 8	Mould 8	Meaning	z ₀＝21	2	5	The address of output physical memory cells arc 5 is 2 data
z ₁＝22	2	6	The address of output physical memory cells arc 6 is 2 data	z ₀＝21	2	5	The address of output physical memory cells arc 5 is 2 data
z ₁＝22	2	6	The address of output physical memory cells arc 6 is 2 data	z ₂＝23	2	7	The address of output physical memory cells arc 7 is 2 data
z ₃＝16	2	0	The address of output physical memory cells arc 0 is 2 data	z ₂＝23	2	7	The address of output physical memory cells arc 7 is 2 data
z ₃＝16	2	0	The address of output physical memory cells arc 0 is 2 data	z ₄＝25	3	1	The address of output physical memory cells arc 1 is 3 data
z ₅＝26	3	2	The address of output physical memory cells arc 2 is 3 data	z ₄＝25	3	1	The address of output physical memory cells arc 1 is 3 data
z ₅＝26	3	2	The address of output physical memory cells arc 2 is 3 data	z ₆＝27	3	3	The address of output physical memory cells arc 3 is 3 data
z ₇＝28	3	4	The address of output physical memory cells arc 4 is 3 data	z ₆＝27	3	3	The address of output physical memory cells arc 3 is 3 data

Table 4

As shown in figure 14, address conversion module is delivered to corresponding physical memory cells arc 50 ~ 57 respectively with transformation result, and physical memory cells arc arrives the address replacement module according to the address information output data.

Meanwhile, address conversion module is with z ₀Pairing physical memory cells arc numbers 5 is transported to the address replacement module, DCU data control unit in the replacement module of address is sent to the reading of data selected cell with the selection signal that physical memory cells arc numbers 5 transforms into the selector switch of reading of data selected cell, the reading of data selected cell selects signal to be changed by the data of physical memory cell input by these, the data of physical memory cells arc 55 are adjusted to first byte of output, as shown in figure 14, then 8 data of the delegation of reading are sent to register with crossing bus.

The mode that reads for pixel groups 8 is described again, controller needing can to obtain the data block in the two-dimentional submatrix data space of access by the parsing to access instruction first address is respectively 3 and 1 with respect to the line displacement and the line skew of the base address of two-dimentional submatrix data space, need the orientation of the data block in the two-dimentional submatrix data space of access to arrange for row, needing the length of the data block in the two-dimentional submatrix data space of access is 5.Controller carries out the calculating of physical address with above information conveyance to each address calculation, and the data path of calculated address computing unit selects signal to control the carrying out of its calculating simultaneously.

The equal controlled device of the first five address calculation in the address calculation group enables, and begins to carry out the physical address calculating operation, and as shown in Figure 6, address information that the controlled device of address calculation is sent here and data path select signal to finish following computing:

The physical address computing unit is carried out with reference to formula (2):

z ₀＝0+3×1+(1+0)×16＝19

z ₁＝0+3×1+(1+1)×16＝35

z ₂＝0+3×1+(1+2)×16＝51

z ₃＝0+3×1+(1+3)×16＝67

z ₄＝0+3×1+(1+4)×16＝83

Wherein subscript 0 ~ 5 is represented the module No. of address calculation, and each physical address computing unit is only carried out the computing of own respective modules number.

The row-coordinate computing unit is owing to the orientation of the data block in the two-dimentional submatrix data space that needs access is arranged for row only, so all row-coordinate computing units are carried out with reference to formula (5) simultaneously:

R(z)＝(3％8)×1＝3

Row coordinate Calculation unit is carried out with reference to formula (6):

C(z ₀)＝(1+0)％8＝1

C(z ₁)＝(1+1)％8＝2

C(z ₂)＝(1+2)％8＝3

C(z ₃)＝(1+3)％8＝4

C(z ₄)＝(1+4)％8＝5

The result of physical address computing unit, row-coordinate computing unit, row coordinate Calculation unit is transported to the correction that the address amending unit carries out the address.The address is revised with reference to table 3, for example comprise the steps: to table look-up according to pixel I residing row-coordinate 3 and row coordinate 2 in the square matrices zone that the data cell of independently interlocking is formed for the correction of pixel I physical address obtain+2, i.e. the z that obtains at the physical address computing unit ₁Add 2 on=35 the basis again and just obtained the pairing physical address 37 of revised pixel I.

After the same method, each address amending unit is transported to corresponding data selector 6 with the physical address of revised pixel M, J, K, L respectively, and as shown in Figure 6, data selector 6 gating signals are 0, with result's output of address amending unit.

As shown in figure 15, the result of calculation of address calculation is transported to address conversion module.Address conversion module carries out result of calculation divided by 8 and the processing of mould 8, here 8 be meant that the physical memory cells arc group is made up of 8 parallel physical memory cells arc, obtain following table 5:

	Divided by 8	Mould 8	Meaning
	Divided by 8	Mould 8	Meaning	z ₀＝20	2	4	The address of output physical memory cells arc 4 is 2 data
z ₁＝37	4	5	The address of output physical memory cells arc 5 is 4 data	z ₀＝20	2	4	The address of output physical memory cells arc 4 is 2 data
z ₁＝37	4	5	The address of output physical memory cells arc 5 is 4 data	z ₂＝54	6	6	The address of output physical memory cells arc 6 is 6 data
z ₃＝71	8	7	The address of output physical memory cells arc 7 is 8 data	z ₂＝54	6	6	The address of output physical memory cells arc 6 is 6 data
z ₃＝71	8	7	The address of output physical memory cells arc 7 is 8 data	z ₄＝80	10	0	The address of output physical memory cells arc 0 is 10 data

Table 5

As shown in figure 15, address conversion module is delivered to corresponding physical memory cells arc 50 ~ 57 respectively with transformation result, and physical memory cells arc arrives the address replacement module according to the address information output data.

Meanwhile, address conversion module is with z ₀Pairing physical memory cells arc numbers 4 is transported to the address replacement module, DCU data control unit in the replacement module of address is sent to the reading of data selected cell with the selection signal that physical memory cells arc numbers 4 transforms into the selector switch of reading of data selected cell, the reading of data selected cell selects signal to be changed by the data of physical memory cell input by these, the data of physical memory cells arc 54 are adjusted to first byte of output, as shown in figure 14, then 5 data of the delegation of reading are sent to register with crossing bus.

So far, the operation of current read data is all finished.

Claims

1. access method of matrix data, this method comprises the following steps:

Include predetermined higher dimensional matrix data space, it finally is converted into a plurality of two-dimensional matrix data spaces through multistage dimension-reduction treatment, each two-dimensional matrix data space resolves into the independently two-dimentional submatrix data space of a series of mutual logic again, described two-dimentional submatrix is m * n matrix, and m, n are natural number;

Data are taked by the mode of higher-dimension to low-dimensional when described higher dimensional matrix data space is deposited, take by left-to-right when in each two-dimentional submatrix data space, depositing, order from top to bottom, according to the mode that the result of mould N deposits, N is meant the modulus of physical storage;

Thereby read the data of the data block in the two-dimentional submatrix data space that needs access in the appropriate address from each storer of a plurality of physical storages;

When reading of data, the data of reading from physical storage pass through data replacement as required so that its reading of data of satisfying the demand order;

2. a kind of access method of matrix data as claimed in claim 1, it is characterized in that: described data model storage is the row memory module, under the memory module of being expert at, the orientation of the data block of the access of supporting is arranged for row, and the data block length that at every turn can carry out access is no more than the storage unit sum of physical storage.

3. a kind of access method of matrix data as claimed in claim 1, it is characterized in that: described data model storage is the row memory modules, under the row memory module, the orientation of the data block of the access of supporting is arranged for row, and the data block length that at every turn can carry out access is no more than the storage unit sum of physical storage.

4. a kind of access method of matrix data as claimed in claim 1 is characterized in that: described data model storage is a ranks stored interleaved pattern, and under ranks stored interleaved pattern, the orientation of the data block of the access of support is arranged for row and row are arranged;

Under ranks stored interleaved pattern, when carrying out access, data to interlock, the staggered square matrices zone that comprises the following steps: (1), forms by the data cell of independently interlocking, described square matrices zone is meant that the number of the capable span that comprises equals the line number that this zone comprises on line direction, the number of the described capable span that comprises is staggered amount, and staggered amount is no more than the number of the capable span that the storage unit sum of physical storage comprised;

(2), the first line data order in the described square matrices zone is remained unchanged;

(3), the data element of last row in span of second line data in the described square matrices zone transferred in first row span relevant position go, and original shift a capable span successively backward to the data element the capable span of penult from first row span;

(4), the data element in the capable span of penult of the third line data in the described square matrices zone is transferred in first row span relevant position and gone, the data element of last row in span transferred in second capable span relevant position and gone, and original data element from first row span to third from the bottom row span shifts two capable spans successively backward;

(5), and the like, whenever proceed to next line, then moving on to the first data element of row from end of line increases by one, finishes up to the last column that proceeds to described square matrices zone.

5. a kind of access method of matrix data as claimed in claim 4 is characterized in that: described interleave method also comprises:

(6), each new row of drawing after interlocking of described square matrices zone can carry out permutation and combination, each result who produces through permutation and combination all can be used as the result of this interlace mode.

6. as the described a kind of access method of matrix data of one of claim 1-5, it is characterized in that: the first address of the data block in the described two-dimentional submatrix data space that needs access is positive number or negative with respect to the line displacement of the base address of two-dimentional submatrix data space and the side-play amount of line skew.

7. as claim 4 or 5 described a kind of access method of matrix data, it is characterized in that: correction chart mode such as the following table 1 of determining ranks stored interleaved pattern according to staggered amount and row span:

Table 1

In the table 1, M is the amount of interlocking, and X represents row span xstride, and X (M-1) represents to go span X and product (M-1), and X (M-2) represents row span X and product (M-2), and X (M-3) represents to go span X and product (M-3), and the like;

Table look-up according to each data residing row-coordinate and row coordinate in the square matrices zone that the data cell of independently interlocking is formed and 1 to obtain modified value, on the basis of the uncorrected physical address that the physical address computing unit obtains, add the correction side-play amount that checks in the table then again and just obtained the pairing revised physical address of revised each data, each the new row that draws after the square matrices zone interlocks as described can carry out permutation and combination and form new staggered result, then Dui Ying correction chart 1 permutation and combination of also carrying out identical each row gets final product, and its modified value is identical.

8. a kind of access method of matrix data as claimed in claim 2 is characterized in that:

If the base address is base, the first address that needs the data block in the two-dimentional submatrix data space of access is respectively x and y with respect to the line displacement and the line skew of the base address of two-dimentional submatrix data space, the row span is xstride, and the row span is ystride;

z _i＝base+(x+i)×xstride+y×ystride (1)

With global physical address z _iCarry out simultaneously obtaining the needed physical address information of each memory cell after the computing divided by N and mould N, N is meant the modulus of described physical storage.

9. a kind of access method of matrix data as claimed in claim 3 is characterized in that:

z _i＝base+x×xstride+(y+i)×ystride (2)

Physical address z with the overall situation _iCarry out simultaneously obtaining the needed physical address information of each memory cell after the computing divided by N and mould N, N is meant the modulus of described physical storage.

10. a kind of access method of matrix data as claimed in claim 7 is characterized in that:

1), the global physical address z of each data correspondence in the data block of calculating unmodified _i:

z _i＝base+(x+i)×xstride+y×ystride (1)

z _i＝base+x×xstride+(y+i)×ystride (2)

2), the row-coordinate R (z of each data position in the square area of independently carrying out data interlace of while computational data piece _i) and row coordinate C (z _i):

R (z_{i}) = \{\begin{matrix} (x + i) % N \times xstride & (x + i &GreaterEqual; 0) \\ (N + (x + i) % N) \times xstride & (x + i < 0) \end{matrix} - - - (3)

C (z_{i}) = \{\begin{matrix} y % N & (y &GreaterEqual; 0) \\ N + y % N & (y < 0) \end{matrix} - - - (4)

R (z_{i}) = \{\begin{matrix} (x % N) \times xstride & (x &GreaterEqual; 0) \\ (N + x % N) \times xstride & (x < 0) \end{matrix} - - - (5)

C (z_{i}) = \{\begin{matrix} (y + i) % N & (y + i &GreaterEqual; 0) \\ N + (y + i) % N & (y + i < 0) \end{matrix} - - - (6)

3), obtain correction chart according to different interlace modes, according to the R (z that obtains previously _i) and C (z _i) side-play amount that each data of drawing data block move in interleaved processes, utilize this side-play amount to z _iRevise, thereby draw each data in the data block in the two-dimentional submatrix data space that needs access corresponding global physical address in physical storage;

4), with the physical address z of the overall situation _iCarry out simultaneously obtaining the needed physical address information of each memory cell after the computing divided by N and mould N, N is meant the modulus of described physical storage.

11. a kind of access method of matrix data as claimed in claim 6, it is characterized in that: described physical storage is that bytes of memory device unit composes in parallel by a plurality of bit wides, and the numerical value of described base address, data element width, row span, row span is unit with the byte-sized.

12. a matrix data memory storage that is used to realize access method of matrix data as claimed in claim 1 is characterized in that:

The logical memory space of described matrix data memory storage includes predetermined higher dimensional matrix data space, described higher dimensional matrix data space finally is converted into a plurality of two-dimensional matrix data spaces through multistage dimension-reduction treatment, each two-dimensional matrix data space resolves into the independently two-dimentional submatrix data space of a series of mutual logic again, described two-dimentional submatrix is m * n matrix, and m, n are natural number;

Described matrix data memory storage comprises:

The data replacement module, be used for when reading of data, the information of the pairing physical memory cells arc of first address of the data block in the two-dimentional submatrix data space that needs access that produces according to address conversion module is replaced one group of data that the physical memory cells arc group produces, so that its reading of data of satisfying the demand order; And when write data, the information of the pairing physical memory cells arc of first address of the data block in the two-dimentional submatrix data space that needs access that produces according to address conversioning unit is replaced one group of data sending into the physical memory cells arc group so that it satisfies the order of depositing of needs in the physical storage;

13. matrix data memory storage as claimed in claim 12 is characterized in that: described address calculation comprises:

The row-coordinate computing unit, be used under ranks stored interleaved pattern, according to self module No. and the first address of the data block in the two-dimentional submatrix data space of needs access with respect to the line displacement of the base address of two-dimentional submatrix data space, generate the row-coordinate at relevant position data place in the square matrices zone of independently carrying out data interlace of the data block in the two-dimentional submatrix data space that needs access;

Row coordinate Calculation unit, be used under ranks stored interleaved pattern, according to self module No. and the first address of the data block in the two-dimentional submatrix data space of needs access with respect to the line skew of the base address of two-dimentional submatrix data space, generate the row coordinate at relevant position data place in the square matrices zone of independently carrying out data interlace of the data block in the two-dimentional submatrix data space that needs access;

The address amending unit, be used under ranks stored interleaved pattern, the row coordinate at the row-coordinate at the global physical address that generates according to the physical address computing unit, data place in the square matrices zone of independently carrying out data interlace that the row-coordinate computing unit generates, data place in the square matrices zone of independently carrying out data interlace of row coordinate Calculation unit generation is revised, and finally generates revised physical address;

Output data selector, that be used for selecting under the ranks interleaving mode is the result of OPADD amending unit, and what select under be expert at memory module and the row memory module is the result of calculation of directly exporting the physics address calculation.

14. as claim 12 or 13 described matrix data memory storages, it is characterized in that: described data replacement module comprises: