CA2217589A1 - Digital transmission framing system - Google Patents

Digital transmission framing system

Info

Publication number
CA2217589A1
CA2217589A1 CA002217589A CA2217589A CA2217589A1 CA 2217589 A1 CA2217589 A1 CA 2217589A1 CA 002217589 A CA002217589 A CA 002217589A CA 2217589 A CA2217589 A CA 2217589A CA 2217589 A1 CA2217589 A1 CA 2217589A1
Authority
CA
Canada
Prior art keywords
bit
framing
reference register
pattern
bits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002217589A
Other languages
French (fr)
Other versions
CA2217589C (en
Inventor
Christopher A. Pawlowski
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AG Communication Systems Corp
Original Assignee
AG Communication Systems Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AG Communication Systems Corp filed Critical AG Communication Systems Corp
Publication of CA2217589A1 publication Critical patent/CA2217589A1/en
Application granted granted Critical
Publication of CA2217589C publication Critical patent/CA2217589C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0602—Systems characterised by the synchronising information used
    • H04J3/0605—Special codes used as synchronising signal
    • H04J3/0608—Detectors therefor, e.g. correlators, state machines

Abstract

A digital transmission framing system utilizing an address array containing pointers to a framing pattern reference register. The address array contains an entry for each set of possible framing bits. Pointer values reference the last bit of a consecutive-bit sub-pattern of the reference register that the previously received bits in this frame bit position have matched. As data bits are received, the associated pointer value is incremented by one to point to the next bit of the reference register, and the received data bit is compared to the newly referenced reference register bit. If the received data bit matches the newly referenced reference register bit, the associated pointer is updated with the incremented value and the corresponding frame bit position of the received data bit remains a candidate for the actual framing bit position. This matching operation continues until only one eligible framing bit position is identified in the input data frame. Bit 0 of the framing bit pattern in the transmission stream is then identified and a synchronization signal is generated.
CA002217589A 1996-12-16 1997-10-06 Digital transmission framing system Expired - Fee Related CA2217589C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US767,558 1996-12-16
US08/767,558 US5854794A (en) 1996-12-16 1996-12-16 Digital transmission framing system

Publications (2)

Publication Number Publication Date
CA2217589A1 true CA2217589A1 (en) 1998-06-16
CA2217589C CA2217589C (en) 2003-12-30

Family

ID=25079851

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002217589A Expired - Fee Related CA2217589C (en) 1996-12-16 1997-10-06 Digital transmission framing system

Country Status (2)

Country Link
US (1) US5854794A (en)
CA (1) CA2217589C (en)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6501810B1 (en) * 1998-10-13 2002-12-31 Agere Systems Inc. Fast frame synchronization
GB2320662B (en) * 1996-12-18 2001-06-20 Dsc Telecom Lp Apparatus and method of frame aligning information in a wireless telecommunications system
US5982786A (en) * 1997-11-21 1999-11-09 Cypress Semiconductor Corp. Circuits and methods for framing one or more data streams
FI107673B (en) 1999-09-28 2001-09-14 Nokia Multimedia Network Termi Method and arrangement for synchronizing to a digital signal and for retaining synchronization
US6973101B1 (en) * 2000-03-22 2005-12-06 Cypress Semiconductor Corp. N-way simultaneous framer for bit-interleaved time division multiplexed (TDM) serial bit streams
US20040003266A1 (en) * 2000-09-22 2004-01-01 Patchlink Corporation Non-invasive automatic offsite patch fingerprinting and updating system and method
EP1327191B1 (en) * 2000-09-22 2013-10-23 Lumension Security, Inc. Non-invasive automatic offsite patch fingerprinting and updating system and method
AU2002360844A1 (en) * 2001-12-31 2003-07-24 Citadel Security Software Inc. Automated computer vulnerability resolution system
US7243148B2 (en) 2002-01-15 2007-07-10 Mcafee, Inc. System and method for network vulnerability detection and reporting
US7543056B2 (en) 2002-01-15 2009-06-02 Mcafee, Inc. System and method for network vulnerability detection and reporting
US7257630B2 (en) 2002-01-15 2007-08-14 Mcafee, Inc. System and method for network vulnerability detection and reporting
US7372928B1 (en) * 2002-11-15 2008-05-13 Cypress Semiconductor Corporation Method and system of cycle slip framing in a deserializer
US8091117B2 (en) 2003-02-14 2012-01-03 Preventsys, Inc. System and method for interfacing with heterogeneous network data gathering tools
US7627891B2 (en) 2003-02-14 2009-12-01 Preventsys, Inc. Network audit and policy assurance system
US6879272B1 (en) * 2004-02-24 2005-04-12 Adaptec, Inc. Method and apparatus for controlling data output frequency
US8201257B1 (en) 2004-03-31 2012-06-12 Mcafee, Inc. System and method of managing network security risks
US7519954B1 (en) 2004-04-08 2009-04-14 Mcafee, Inc. System and method of operating system identification
US7439816B1 (en) 2005-09-28 2008-10-21 Cypress Semiconductor Corporation Phase-locked loop fast lock circuit and method
US7728675B1 (en) 2006-03-31 2010-06-01 Cypress Semiconductor Corporation Fast lock circuit for a phase lock loop
US7823053B2 (en) * 2006-12-19 2010-10-26 International Business Machines Corporation System and method for searching error messages
US20100284425A1 (en) * 2009-05-11 2010-11-11 David Hood System and method of using tdm variable frame lengths in a telecommunications network

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0828691B2 (en) * 1988-03-14 1996-03-21 富士通株式会社 Frame synchronization method
JPH05160825A (en) * 1991-12-03 1993-06-25 Fujitsu Ltd Synchronizing circuit
US5331670A (en) * 1992-01-31 1994-07-19 At&T Bell Laboratories Synchronization scheme for a digital communications system
US5557614A (en) * 1993-12-22 1996-09-17 Vlsi Technology, Inc. Method and apparatus for framing data in a digital transmission line
DE4429595C1 (en) * 1994-08-20 1995-06-29 Philips Patentverwaltung Digital data transmission system for ATM cells transporting 34 368 Kbit/s PDH signals

Also Published As

Publication number Publication date
US5854794A (en) 1998-12-29
CA2217589C (en) 2003-12-30

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