CA2012425C

CA2012425C - Packet switching system having arbitrative function for competing packets

Info

Publication number: CA2012425C
Application number: CA002012425A
Authority: CA
Inventors: Atsuo Itoh; Toshio Suzuki
Original assignee: NEC Corp
Current assignee: NEC Corp
Priority date: 1989-03-17
Filing date: 1990-03-16
Publication date: 1996-12-24
Anticipated expiration: 2010-03-16
Also published as: CA2012425A1; US5305310A

Abstract

Disclosed is a packet switching system having, on its input side, m-sorting modules each having sorting circuitry for sorting a plurality of packets entered simultaneously according to the destination address; dropping circuitry for, if there are a plurality of competing packets having the same destination address among the packets sorted by the sorting circuitry, keep-ing one of the competing packets and dropping the rest to in-ferior on sorting module; and routing circuitry for routing each packet passed by the dropping circuitry on the basis of the destination address. The m-sorting modules are so sequentially connected as to make the dropped output of the dropping circuitry of a superior sorting module the input to the sorting circuitry of the immediately inferior sorting module. Buffer modules tem-porarily store the packets entered from the routing circuitry of the m-sorting modules and supply them to output lines of the packet switching system on a first-in first-out basis, each buffer module being connected to an output line corresponding to the destination address. The plurality of packets are entered into the highest-positioned sorting module, non-competing packets are distributed from the highest-positioned sorting module to the buffer modules corresponding to the output lines indicated by the destination addresses, and k-competing packets are entered into the same buffer module with prescribed delays in a sequence from the highest-positioned sorting module to the k-th sorting module.

Description

PACKET SWITCHING SYSTEM HAVING ARBITRATIVE FUNCTION
FOR COMPETING PACKETS

BACKGROUND OF THE INVENTION

Field of the Invention The present invention relates to a self-routing packet switching system.

Description of the Prior Art In a packet switching system of this kind according to the prior art, the address of a packet given from an input line is identified, and the packet is supplied to an output line corresponding to the desired address. When a plurality of packets destined for the same address are simultaneously entered into such a packet switching system, the switching of the competing packets can be achieved in one of the following two methods. By one method, a sorting network and a routing network are combined, and the competing packets, after being dropped and given appropriate delays in a later stage of the routing network, are reentered into the same routing network as taught by Alan Huang et al. in an article entitled "A Wideband Digital Switch"
published in 1984 in the IEEE Global Telecommunications Conference Record. By the other, a switch module having an n-input one-output selecting function is provided corresponding to each output line, and switching is so -201242~
accomplish as to select the packet destination for a given output line out of a bus comprising n-input lines as disclosed by Y.S. Yeh et al. in an article entitled "The Knockout Switch: A Simple, Modular Architecture for High-Performance Packet Switching" published in the Proceedings of IEEE
International Switching Symposium 1987.
The former, however, requires complex processing, such as time stamping, in order to avoid the reversing of the sequence of the competing packets when they are reentered.
The latter, which needs as many n-input one-output (n is the number of input lines) switch modules as the number of output lines, entails a large hardware volume where many input and output lines are involved.

SUMMARY OF THE INVENTION
An object of the present invention, is therefore, to provide a packet switching system capable of supplying, even if a plurality of packets destined for the same address are entered simultaneously, each packet to the desired output line using relatively simple circuitry and processing.
According to a broad aspect, the invention provides a packet switching system comprising: on its input side, m-sorting modules, where m is a positive integer, and 2Cm~
each having sorting means for sorting a plurality of packets entered simultaneously from n-input lines, where n is a positive integer and 2cn, according to the destination address; dropping means for, keeping one of the competing packets and dropping the rest to a sorting module in an inferior position if there are a plurality of competing packets having the same destination address among the packets sorted by the sorting means; and routing means for routing each packet passed the dropping means on the basis of the destination address; said m-sorting modules comprising a first sorting module, a second sorting module, ..., and an m-l-th sorting module and each being in a first superior position, a second superior position, ..., a second inferior position and a first inferior position respectively, and said m-sorting modules being coupled in cascade connection to input a dropped packet outputted from said dropping means of the sorting module in superior position into the sorting means of the sorting module in a next inferior position toward said sorting module; buffer modules for temporarily storing the packets entered from said routing means of said m-sorting modules and supplying them to output lines of the packet switching system on a first-in first-out basis, each buffer module being connected to an output line corresponding to said destination address, whereby said plurality of packets are initially entered into the first sorting module in the first superior position, non-competing packets are distributed from said first sorting module to the buffer modules corresponding to the output lines indicated by said destination address, the k-competing packets, where k is a positive integer, and 2ck_n are entered into the same buffer module with predetermined delays in sequence from the highest-positioned sorting module to the k-th sorting module.
According to a second broad aspect, the invention '.."

-201242~
provides a process for switching packets of data information, each packet including an address defining the destination of the data packet, the process comprising the steps of: (a~
receiving incoming data packets at an input circuit; tb) sorting a plurality of packets having the same address which are simultaneously competing for attention at a sorting module, the packets being sorted as they are received on a basis of the addresses of the received packets; (c) selecting one of said packets sorted at the sorting module according to step (b) and forwarding the selected sorted packet toward its destination; (d) transferring the non-selected ones of said competing packets to another sorting module for again sorting and selecting one of said competing packets according to steps (b) and (c); (e) repeating step ~d) until substantially all of said competing packets have been sorted and forwarded; and (f) buffer time storing said forwarded packets in order to release them in a smooth and orderly form.
According to a third broad aspect, the invention provides a system for switching information packets, wherein each information packet has its own address, said switching system comprising: a plurality of sorting modules, each of said sorting modules comprising in a cascade sequence a sorting circuit, a dropping circuit arranged in a hierarchial order, and a routing circuit, said sorting circuit sorting the information packets entered simultaneously according to the address, said dropping circuit keeping one of the competing packets and dropping the rest, and said routing circuit routing each packet passed the dropping circuit on the basis ~, ,, of the address; means for coupling the dropping circuit in one of said modules to a sorting circuit in the next succeeding one of said modules, thereby creating a cascaded hierarchial order extending from a superior to an inferior sorting module, the superior sorting module being coupled to receive incoming information packets; means for selecting one from a number of packets having the same address which are competing for simultaneous attention and for passing the non-selected remainder of said information packets to the sorting circuit which is next in said hierarchial order, a plurality of switching means associated with said plurality of sorting modules and responsive to said routing circuits for selectively forwarding said information packet according to said packets addresses; and means for buffer time storing said packets in order to smoothly forward them to their destination.

BRIEF DESCRIPTION OF THE DRAWINGS
The above object and features of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a block diagram of a preferred embodiment of the invention;
FIG. 2 illustrates one example of packet construction to be switched by the system according to the invention;
FIG. 3 illustrates in further detail a part of the - 4a -201242~
preferred embodiment shown in FIG. 1;
FIGS. 4 and 5 are flow charts for explaining the operation of the embodiment; and FIGS. 6 to 10 are diagrams for explaining an example of the operation of the embodiment.
In the drawings, the same reference numerals denote the same constituent elements, respectively.

DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG. 1 is a block diagram of a preferred embodiment of the present invention. The packet switching system illustrated in FIG. 1 is composed of n-input lines 101, m-sorting modules 11 to lm, n-output lines 108, and - 4b -_ 5 _ 2012425 n-buffer modules 21 to 2n corresponding to each of the output lines 108.
Each of the sorting modules 11 to lm comprises a sorting circuit 3, a dropping circuit 4 and a routing circuit 5. All of the input lines 101 are connected to the sorting circuit 3 of the first sorting module 11.
The sorting circuit 3 sorts in the sequence of destination addresses all the packets simultaneously entered from the input lines 101, and supplies them to n-data lines 102.
The dropping circuit 4, if two or more packets have the same destination address, keeps one, drops and supplies to n-data lines 105 the other competing packets, and outputs the kept packet and non-competing ones to n-data lines 103. The routing circuit 5 supplies the packets entered from the data lines 103 to the buffer modules corresponding to the output lines of their respective destination addresses via n-data lines 104.
The sorting modules 11 to lm have a multi-line configuration. Among the m-sorting modules 11 to lm, the module 11 is in the highest, and the module lm in the lowest, position. The connection is so arranged that competing packets, dropped by the dropping circuit 4 of a superior module (the sorting module 11, for example), is made the input to the sorting circuit 3 of the immediately inferior module (the sorting module 12, for example).

A packet entered into the sorting module 11, as illustrated in FIG. 2, has as its most significant bit an idle indication bit II indicating the presence of packet information, followed by destination address bits DA indicating the address of the output line and packet information in that order. "0" for the idle indication bit II denotes the validity of the packet information, and "1", the idleness of the packet whose packet information is invalid.
The dropping circuit 4, as shown in FIG. 3, is composed of a competition-arbitrative section 41 comprising n-competition-arbitrative circuits 411 to 41n.
Among the competition-arbitrative circuits 411 to 41n whose function is to determine whether or not a given packet is to be dropped, the circuit 411 is in the highest, and the circuit 41n, in the lowest position. Each of the competition-arbitrative circuits 412 to 41n is connected to an output line 410 for supplying, when a packet has been entered from a data line 102, the same packet; an output line 103 for supplying a packet which does not compete with the immediately superior packet;
and a data line 105 for dropping the packet, if it does compete, and supplying it to the immediately inferior sorting module.
Referring back to FIG. 1, the routing circuit 5 is intended to examine the destination address of the input _ 7 _ 2012425 packet and supplying it to one of the buffer modules 21 to 2n corresponding to the output line 108 to which it is to be sent. Each of its n-output lines 104 is connected to the buffer modules 21 to 2n, respectively. The routing circuit 5 is a non-blocking switch, so that no blocking takes place unless a plurality of packets are to be supplied to the same output line 104.
Here, in the inputting to the sorting circuit 3, when a plurality of packets are simultaneously supplied from a packet synchronizing circuit (not shown) arranged in a preceding stage in the packet switching system, a timing pulse indicating the packet input is supplied to a packet starting position designation line 111. These actions take place cyclically. Each of the circuits 3, 4 and 5, when outputting a packet, informs the next circuit of the arrival of the packet by supplying a timing pulse to packet starting position designation lines 112, 113, 115 and 114.
Each of the n-buffer modules 21 to 2n is provided with an m-input m-output switching circuit 6, a buffer memory 7 having m-FIFO (first-in-first-out) buffers corresponding to m-lines 106, a selector 8 for selecting one out of m-output lines 107 of the buffer memory 7 and connecting it to an output line 108, and a controller 9 for controlling the whole buffer module. As the switching circuit 6 can be used, for instance, an m x m space division switch.

- 8 ~ 2 0 12425 Next will be described the operation of the sorting modules and buffer modules with reference to FIGS. 4 and 5.
Referring to FIG. 4, first, a plurality of packets entered into the packet switching system are inputted to the sorting circuit 3 of the sorting module 11. The sorting circuit 3 sorts all the packets in the ascending order of the binary value through bit-by-bit comparison (Step Sl). In this preferred embodiment, as there is the idle indication bit II as the most significant bit, which is "0" in a valid packet, the order of sorting is mainly determined by the address DA. If the number n of output lines is 64, the address will consist of six bits, so that, if "000000" denotes the No. 0 output line, "000001", the No. 1 output line, ..., and "111111", the No. 63 output line, the packet destined for the No. 0 output line will be sorted into the highest position.
Among packets having the same address DA, the sorting order is determined by the binary value of the packet information section following the address DA. Packets sorted in this manner are supplied to the n-data lines 102 in the ascending order of the power. In this procedure, competing packets having the same address are always outputted together, adjoining one another.
Then, the sorted packets are entered into the competition-arbitrative sections 41 of the dropping circuit 4. In each of the competition-arbitrative circuits 412 to 41n, as a packet whose position is immediately superior in the order of sorting is entered via the data line 410 from the immediately superior competition-arbitrative circuit, its address is compared with that of the packet entered from the data line 102 (Step S2). If the packet is found to have the same address as the packet superior in the sorting order, it will be considered defeated in the competition, or otherwise the packet (the one entered from the data line 102) will survive. Surviving packets, which either are non-competing or have won the competition, are supplied to a routing circuit 5 via a data line 103 (Step S3). At this time, an idle packet whose idle indication bit II has been altered to "1" (with its address DA and packet information unchanged) is supplied to the immediately inferior sorting module 12 via the data line 105 (Step S4).
At Step S2, on the other hand, a packet defeated in the competition is dropped from the first sorting module 11 and entered into the second sorting module 12.
Thus, in that one of the competition-arbitrative circuits 412 to 41n which determined the existence of competition, the packet entered from the data line 102 is supplied as it is to the data line 105, and the idle packet whose idle indication bit II has been altered to "1"
(with its address DA and packet information unchanged) lO- 201242S

is supplied to the routing circuit 5 via the data line 103 (Steps S5 and S6). In the competition-arbitrative section 41, the one packet having the smallest binary value among competing packets is kept, and the rest are handled by inferior sorting modules. Then, n-packets outputted from the competition-arbitrative section 41 are entered into the routing circuit 5 via the data lines 103. The routing circuit 5 identifies the address DA of valid packets, and supplies them via the data lines 104 to the buffer modules 21 to 2n corresponding to the respectively desired ones of the output lines 108 (Step S7). This routing circuit 5 does not output any idle packet that may be entered.
Packets outputted to the data line 105 from the competition-arbitrative section 41 of the dropping circuit 4 are entered into the second sorting module 12.
The sorting modules 12 to lm also operate as charted in FIG. 4. In the sorting modules 12 to lm, both valie packets and invalid packets (the idle packets) are indiscriminately entered into their sorting circuit 3.
Accordingly, each sorting circuit 3 of the modules 12 to lm also separates valid and invalid packets in its output. In the second sorting module 12, again, one packet out of the group of competing packets having the same address survives, and is supplied to the desired one of the buffer modules 21 to 2n. What should be noted - ll- 201242~

here is that the packet entered from the second sorting module 12 to one of the buffer modules 21 to 2n always has a fixed delay from that entered from the first sorting module 11 to that one of the buffer modules 21 to 2n.
Thus, the entery into one of the modules 21 to 2n from the module 12 is delayed by the processing time taken by the second module 12. Therefore, more than one packet is never entered into the same buffer module simultaneously.
Now will be described the operation of the buffer modules 21 to 2n with reference to FIG. 5. Packets having arrived from the sorting modules 11 to lm are entered into the switching circuit 6. The controller 9, upon detection of the arrival of a packet according to the timing pulse 114 (Step S9), so controls the switching circuit 6 as to store the packet into an unoccupied buffer memory 7 (Steps S10 and S11). Thus the number of the FIFO bufers in the buffer memory 7 is equal to the number m of the sorting modules 11 to lm. As packets which were competing when entered into the first sorting module 11 arrive at the same switching circuit 6 in the ascending order of the binary value at intervals each equal to the aforementioned delay, they are stored into the FIFO buffers in a predetermined sequence. Supposing, for instance, that the Nos. 1 to m FIFO buffers are to be used in this order and that the final packet out of the group of competing packets processed according to the preceding timing pulses 114 is stored into the No. (m-2) buffer memory, this group of competing packets to be processed according to the present timing pulses 114 will be cyclically stored, as they arrive, into the FIFO buffers, starting with No.
(m-l) and followed by No. m, No. 1, No. 2 and so forth in this order. The switching circuit 6 performs switching at a timing equivalent to the length of one packet. Thus a path, once established for packet storing, is held until all the packet has been stored into the FIFO buffer. The group of competing packets stored sequentially in this manner await reading.
The controller 9 cyclically reads the packets out of the buffer memory 7 in the same order as in their storing, controls the selector 8 in synchronism with this reading, and sequentially supplies the group of competing packets to the output line 108 (Step S12).
Now will be described the overall operation with reference to a specific example. It is supposed here, for the sake of simplified description, that n = 4, m = 3 and, as shown in FIG. 6, four packets Pl to P4 are simultaneously supplied to the input lines 101. The addresses of the packets Pl to P4 are "1", "2", "1" and "1", respectively, so that the packets Pl, P3 and P4 are competing with one another. These packets are sorted by the sorting circuit 3 of the first sorting module 11.
The packets Pl, P3 and P4 destined for the same address - - 13 ~ 201242S

are rearranged into the ascending order of the binary value of packet information, i.e. P4, P3 and Pl.
Next, refering to FIG. 7, the sorted packets are entered into the competition-arbitrative section 41.
From here, the packet P4 which has won the competition and the non-competing packet P2 are outputted to the routing circuit 5. At this point, the idle packets IP4 and IP2 of the packets P4 and P2, respectively, are supplied to the data lines 105. The packets P3 and Pl, having been defeated in the competition, are dropped from the first sorting module 11 and supplied-to the data lines 105. At this point, the idle packets IP3 and IPl of the packets P3 and Pl, respectively, are supplied to the data lines 103 leading to the routing circuit 5.
As a result, the packets P4 and P2, and the idle packets IP3 and IPl are entered into the routing circuit 5 of the first sorting module 11.
Then in the routing circuit 5, the packet P4 is routed to the buffer module 22 corresponding to the second output line indicated by the address "1" of this packet, and the packet P2, to the buffer module 23 corresponding to the third output line indicated by its address "2". As already stated, neither the idle packet IP3 nor IPl is outputted.
The packets P3 and Pl and the idle packets IP4 and IP2, as illustrated in FIG. 9, are supplied to the second - 14 ~ 2 0 124 2 5 sorting module 12, where they undergo processing similar to what takes place in the first sorting module 11.
Eventually, the packet P3 survives the processing by the second sorting module 12, and is supplied to the buffer module 22. The packet Pl is again dropped by the second sorting module 12, and supplied from the third sorting module 13 to the buffer module 22.
Next will be described, with reference to FIG. 10, the buffer module 22 where the competing packets P4, P3 and Pl successively arrive. Into the switching circuit 6 are entered the packets P4, P3 and Pl in this order. The input delay time D of the packet P3 behind the packet P4 is due to the former's passage of one extra stage of sorting module. Similarly, the packet Pl arrives 2D
behind the packet P4. It is supposed in this case that the final packet of the previous group of competing packets has been stored into the FIFO buffer 71. Therefore, the controller 9 so controls the switching of the switching circuit ~ as to store the current group of competing packets cyc-lically into the FIFO buffers beginning with the FIFO buffer 72. Thus, the packets P4, P3 and Pl are stored into the FIFO buffers 72, 73 and 71, respectively.
After that, the selector 8 supplies these packets to the output line 108 on the first-in first-out basis, so that the competing packets P4, P3 and Pl are smooth supplied to the respectively desired output lines.

- 15 ~ 2012425 Incidentally, if the arrival of the packet Pl at the buffer module 22 is too long delayed to precede that of the first packet among the group of packets to be entered into the sorting module according to the timing pulse 111 next to the packets Pl to P4, the sequence of packets on the same input line may not be preserved. Therefore, in order to maintain the proper order of packets, the maximum delay (m-l)-D between those in the highest and lowest positions among competing packets should be made shorter than one packet length.
Further, since the maximum possible number of competing packets is n, the number m of sorting modules should not be greater than n. However, this number m and the capacities (depths) of individual FIFO buffers are set according to the maximum conceivable ratio of packet discarding in a given packet switching system.

Claims

1. A packet switching system comprising:
on its input side, m-sorting modules, where m is a positive integer, and 2?m, each having sorting means for sorting a plurality of packets entered simultaneously from n-input lines, where n is a positive integer and 2?n, according to the destination address; dropping means for, keeping one of the competing packets and dropping the rest to a sorting module in an inferior position if there are a plurality of competing packets having the same destination address among the packets sorted by the sorting means; and routing means for routing each packet passed the dropping means on the basis of the destination address;
said m-sorting modules comprising a first sorting module, a second sorting module, .3.., and an m-1-th sorting module and each being in a first superior position a second superior position, ..., a second inferior position and a first inferior position respectively, and said m-sorting modules being coupled in cascade connection to input a dropped packet outputted from said dropping means of the sorting module in superior position into the sorting means of the sorting module in a next inferior position toward said sorting module;
buffer modules for temporarily storing the packets entered from said routing means of said m-sorting modules and supplying them to output lines of the packet switching system on a first-in first-out basis, each buffer module being connected to an output line corresponding to said destination address, whereby said plurality of packets are initially entered into the first sorting module in the first superior position, non-competing packets are distributed from said first sorting module to the buffer modules corresponding to the output lines indicated by said destination address, the k-competing packets, where k is a positive integer, and 2?k?n are entered into the same buffer module with predetermined delays in sequence from the highest-positioned sorting module to the k-th sorting module.

2. A packet switching system, as claimed in claim 1, wherein said dropping means has a dropping circuit for keeping the highest-positioned packet in an order of sorting amount competing packets by sequentially judging the destination addresses of packets which follow each other in the order of sorting and for dropping the lower-positioned packet in the order of sorting between the competing packets which have the same destination address.

3. A packet switching system, as claimed in claim 2, wherein said sorting means sorts a plurality of simultaneously entered packets in an ascending order of the binary value of said packets.

4. A packet switching system, as claimed in claim 2, wherein each of said packets has as its most significant bit information indicating validity or invalidity of the packet and said dropping circuit supplies, in place of each packet dropped in the competition, a packet which is the same as the corresponding dropped packet except that said information is placed with information indicating invalidity.

5. A process for switching packets of data information, each packet including an address defining the destination of the data packet, the process comprising the steps of:
(a) receiving incoming data packets at an input circuit;
(b) sorting a plurality of packets having the same address which are simultaneously competing for attention at a sorting module, the packets being sorted as they are received on a basis of the addresses of the received packets;
(c) selecting one of said packets sorted at the sorting module according to step (b) and forwarding the selected sorted packet toward its destination;
(d) transferring the non-selected ones of said competing packets to another sorting module for again sorting and selecting one of said competing packets according to steps (b) and (c);
(e) repeating step (d) until substantially all of said competing packets have been sorted and forwarded; and ~ f) buffer time storing said forwarded packets in order to release them in a smooth and orderly form.

6. The process of claim 5 and the step (b) further comprises the step of (b1) sorting the competing packets on a basis of a ascending order of binary address values.

7. The process of claim 5 and the step (c) further comprising the step of (c1) making said selection on a basis of a highest positioned packet address among the addresses of said competing packets, and dropping packets having a lower positioned packet address.

8. The process of claim 7 further comprises the step of (g) indicating a validity or invalidity of a packet by its most significant information bit.

9. The process of claim 8 further comprises the step of (h) changing said most significant bit from valid to invalid when said packet is dropped.

10. A system for switching information packets, wherein each information packet has its own address, said switching system comprising:
a plurality of sorting modules, each of said sorting modules comprising in a cascade sequence a sorting circuit, a dropping circuit arranged in a hierarchial order, and a routing circuit, said sorting circuit sorting the information packets entered simultaneously according to the address, said dropping circuit keeping one of the competing packets and dropping the rest, and said routing circuit routing each packet passed the dropping circuit on the basis of the address;

means for coupling the dropping circuit in one of said modules to a sorting circuit in the next succeeding one of said modules, thereby creating a cascaded hierarchial order extending from a superior to an inferior sorting module, the superior sorting module being coupled to receive incoming information packets;
means for selecting one from a number of packets having the same address which are competing for simultaneous attention and for passing the non-selected remainder of said information packets to the sorting circuit which is next in said hierarchial order, a plurality of switching means associated with said plurality of sorting modules and responsive to said routing circuits for selectively forwarding said information packets according to said packet addresses; and means for buffer time storing said packets in order to smoothly forward them to their destination.

11. The system of claim 10 wherein said buffer time storing means operates on a first in first out basis.

12. The system of claim 11, further comprises means for identifying some of said packets which reach an inferior sorting module as invalid packets.

13. The system of claim 10 wherein said sorting modules sort the competing packets according to the binary value of said data packet addresses.