CA1333727C - Multiprocessor digital data processing system - Google Patents

Abstract

A multiprocessor digital data processing system comprises a plurality of processing cells arranqed in a hierarchy of rings. The system selectively allocates storage and moves exclusive data copies from cell to cell in response to access requests generated by the cells. Routing elements are employed to selectively broadcast data access requests, updates and transfers on the rings.

Description

1 BACKGROUND OF T~ r. ~-ION

This invention relates to digital data processing systems and, more particularly, to multiprocessing systems with distributed hierarchical memory architectures.
The art provides a number of configurations for coupling the processing units of multiprocessing systems. Among the earlier designs, processing units that shared data stored in system memory banks were coupled to those banks via high-bandwidth shared buses or switching networks. During periods of heavy usage, bottlenecks were likely to develop as multiple processing units simultaneously contended for access to the shared data.
In order to minimize the risk of formation of transmission bottlenecks, distributed memory systems were developed coupling individual processing units with local memory elements to form semi-autonomous processing cells. To achieve the benefits of multiprocessing, some of the more recently designed systems established cell communications through utilization of hierarchical architectures.
The distributed memory systems, however, permit multiple copies of single data items to reside within multiple processing cells; hence, it i8 difficult insure that all processing cells maintain identical copies of like data elements. Conventional efforts to resolve this problem, i.e., to preserve data coherency, rely upon software oriented technigues utilizing comple~ signalling mechanisms.
To avoid processing and signalling overhead associated with these software oriented solutions, Frank et al, United States Patent No. 4,622,631, 13 ~ 3 ~ ~ I

1 discloses a multiprocessing system in which a plurality of processors, each having an associated private memory, or cache, share data contained in a main memory element. Data within that common memory is partitioned into blocks, each of which can be owned by any one of the main memory and the plural processors. The current owner of a data block is said to have the correct data for that block.
A hierarchical approach is disclosed by lo Wilson Jr. et al, United Kingdom Patent Application No. 2,178,205, wherein a multiprocessing system is said to include distributed cache memory elements coupled with one another over a first bus. A second, higher level cache memory, attached to the first bus and to either a still higher level cache or to the main system memory, retains copies of e~ery memory location in the caches below it. The still higher level caches, if any, and system main memory, in turn, retain copies of each memory location of cache below them. The Wilson Jr. et al processors are understood to transmit modified copies of data from their own dedicated caches to associated higher level caches and to the system main memory, while concurrently siqnalling other caches to invalidate their own copies of that newly-modified data.
Notwithstanding the solutions proposed by Frank et al and Wilson Jr. et al proposal, data coherency and bus contention remain significant problems facing both designers and users of multiprocessing systems. With respect to Wilson Jr.
et al, for e~ample, these problems may be attributed, at least in part, to the requirement that data in main memory must always be updated to reflect permanent modifications introduced to the data * Published February 4, 1987 -~3~ 13337~7 1 elements by each of the processors in the system.
Moreover, neither of the proposed designs is capable of supporting more than a limited number of processing units. This restriction in ~scalability~
arises from a reguirement of both the Wilson Jr. et al and Frank et al systems that the size of main memory must increase to accommodate each additional processor.
It is therefore an object of this invention to provide an improved multiprocessing system with improved data coherency, as well as reduced latency and bus contention. A further object is to provide a multiprocessing system with unlimited scalability.
` Other objects of the invention are to provide a physically distributed memory multiprocessing system which requires little or no software overhead to ma inta in data coherency, as well as to provide a multiprocessing system with increased bus bandwidth and improved synchronization.

~ 4 1333727 1 SUMMARY OF TH~ INVENTIOP

The invention attains the aforementioned objects by providing, in one broad aspect, a digital data processing system comprising a plurality of processing cells arranged in a hierarchy of rings.
The system selectively allocates storage and moves exclusive data copies from cell to cell in response to access requests generated by the cells. Routing elements are employed to selectively broadcast data access requests, updates and transfers on the rings.
- A system of the type provided by the invention does not require a main memory element, i.e., a memory element coupled to and shared by the systems many processors. Rather, data maintained by the system is distributed, both on exclusive and shared bases, among the memory elements associated with those processors. Modifications to datum stored esclusively in any one processing cell do not have to be communicated along the bus structure to other storage areas. As a result of this design, only that data which the processors dynamically share, e.g., sharing required by the executing program themselves, must be transmitted along the bus structure. These aspects, along with the systems hierarchical structure, localize siqnal traffic greatly, thereby reducing bus contention and bottlenecks.
With further attention to system structure and element interconnection, the processing cells include central processing units coupled with memory elements, each including a physical data and control signal store, a directory, and a control element.
Groups of cells are interconnected along unidirectional intercellular bus rings, forming units ~ - -5~ 1333727 1 referred to as segments. These segments together form a larger unit referred to as ~information transfer domain(0).~ While cells residing within each segment may communicate directly with one another via the associated intercellular bus, the associated central processing units are not themselves interconnected. Rather, intersegment communications are carried out via the exchange of data and control signals stored in the memory elements. A memory management element facilitates this transfer of information.
Communications between cells of different domain(0) segments are carried out on higher level information transfer domains. These higher level domains are made up of one or more segments, each comprising a plurality of domain routing elements coupled via a unidirectional bus ring. It will be appreciated that the segments of higher level domains differ from those of domain(0) insofar as the former comprise a ring of routing elements, while the latter comprise a ring of processing cells. Each routing element is connected with an associated one of the segments of the ne~t lower information transfer domain. These connected lower segments are referred to as ~descendants.~ Every information transfer domain includes fewer segments than the nest lower domain. Apart from the single segment of the system's highest level domain, signals are transferred between segments of each information transfer domain via segments of the nest higher domain.
An esemplary system having sis domain(0) segments includes two domain(l) segments, the first which transfers data between a first three of the - ~ -6- 1~33727 1 domain(0) segments, and the second of which transfers data between the other three domain(0) segments.
Data is transferred between the two domain(l) segments over a domain(2) segment having two domain routing elements, each connected with a corresponding one of the domain(l) segments.
The system' 8 memory elements each include a directory element that maintains a list of descriptors reflecting the identity and state of each datum stored in the corresponding memory. One portion of each descriptor is derived from the associated datum's system address, while another portion represents an access state governing the manner in which the local central processing unit may utilize the datum. This access state may include any one of an ~ownership~ state, a read-only state, and an invalid state. The first of these states is associated with data which can be modified by the - local central processing unit, i.e., that unit included within the cell in which the datum is stored. The read-only state is associated with data which may be read, but not modified, by the local central processing unit. The invalid state is associated with invalid data copies.
The domain routing elements themselves maintain directories listing all descriptors stored in their descendant domain(0) segment~. Thus, in the above esample, the routing elements of first domain(l) segments maintain directories reflecting the combined content of the cells of their respective domain(0) segment. Moreover, the ~ingle routing element of the domain(2) segment maintains a directory listing all descriptors retained in all of the system's processing cells.

~7~ 1~727 Data access requests generated by a processor are handled by the local memory element whenever possible. More particularly, a controller coupled with each memory monitors the cell's internal bus and responds to local processor requests by comparing the request with descriptors listed in the corresponding directory. If found, matching data is transmitted back along the internal bus to the requesting processor.
lo Data requests that cannot be resolved locally are passed from the processing cell to the memory management system. The management element selectively routes those unresolved data requests to the other processing cells. This routing is accomplished by comparing requested descriptors with directory entries of the domain routing units.
Control elements associated with each of those other cells, in turn, interrogate their own associated directories to find the requested data. Data satisfying a pending request is routed along the domain segment hierarchy from the remote cell to the requesting cell.
Data movement between processing cells is governed by a protocol involving comparative evaluation of each access request with the access state associated with the requested item. The memory management system responds to a request for e~clusive ownership of a datum by moving that datum to the memory element of the re~uesting cell. Concurrently, the memory management element allocates physical storage space for the requested item within the requesting cell's data storage area. The management element also invalidates the descriptor associated with the requested item within the data store of the 5 _ ~ -8- 1~33727 1 remote cell, thereby effecting subsequent deallocation of the physical storage space which had retained the reguested item prior to its transfer to the requesting cell.
While the aforementioned operations result in esclusive storage of the requested datum within the requesting cell, other cells may subsequently gain concurrent access to that datum, for example, on a read-only basis. Particularly, the memory lo management system responds to a request by a first cell for read-only access to datum exclusively owned by a second cell by transmitting a copy of that datum to the first cell while simultaneously designating the original copy of that data, stored in the second cell, as ~nonesclusively owned.~
The system permits an owning cell to disable the copying of its data by providing a further ownership state referred to as the ~atomic~ state.
The memory management system responds to requests for data in that state by transmitting a wait, or ~transient,~ signal to requestors and by broadcasting the requested data over the hierarchy once atomic ownership is relinquished.
A system of the type described above provides improved multiprocessing capability with reduced bus and memory contention. The dynamic allocation of esclusive data copies to.processors reguiring esclusive access, as well as the sharing of data copies required concurrently by multiple proceæsors reduces bus traffic and data access delay8. Utilization of a hardware-enforced access protocol further reduces bus and memory contention, while simultaneously decreasing software overhead required to maintain data coherency. The n 1 interconnection of information transfer domain seqments permits localization of data access, transfer and update requests.
These and other aspects of the invention are evident in the description which follows.

-lO- 13337 27 BRIEF DESCRIPTION OF DRAWING~

A more complete understanding of the invention may be attained by reference to the drawings, in which:
Figure 1 depicts the structure of a preferred multiprocessing system constructed in accord with the invention;
Figures 2A and 2B depict a preferred configuration of processing cells, including illustration of data movement provided within respective memory elements, in a digital data processing system constructed according to a preferred embodiment of the invention;
Figure 3 depicts a preferred interconnect structure of processing cells within a domain(0) segment in a digital data processing system constructed according to a preferred embodiment of the invention;
Figure 4 depicts a construction of an esemplary processing cell in a digital data processing system constructed according to a preferred embodiment of the invention;
Figure 5 depicts a preferred interrelationship between system virtual addresses, descriptors, and cache directories in a digital data processing system constructed according to a preferred embodiment of the invention;
Figures 6A and 6B present state tables depicting handling of processor access requests directed to data stored in local caches in a digital data processing system constructed according to a preferred embodiment of the invention;

1 Figures 7A, 7B, 7C and 7D present state tables depicting handling of memory management data requests directed to data stored in the caches in a digital data processing system constructed accordinq to a preferred embodiment of the invention; and Figure 8 depicts a preferred interrelationship between the LRU_Insert table and the LRU set utilized in a digital data processing system constructed according to a preferred embodiment of the invention.
Figure 9 depicts a construction for a preferred domain routing cell, including a remote interface unit, for a digital data processing system constructed according to a preferred practice of the invention.

~ -12- 1~33727 DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENT

Figure 1 depicts the structure of a preferred multiprocessing system 10 constructed in accord with the invention. The illustrated system 10 includes three information transfer domains:
domain(0), domain(l), and domain(2). Each information transfer domain includes one or more domain segments, characterized by a bus element and a plurality of cell i`nterface elements. Particularly, domain(0) of the illustrated system 10 includes sis segments, designated 12A, 12B, 12C, 12D, 12E and 12F, respectively. Similarly, domain(l) includes segments 14A and 14B, while domain(2) includes segment 16.
Each segment of domain(0), i.e., segments 12A, 12B, ... 12F, comprise a plurality of processing cells. For example, as shown in the illustration, segment 12A includes cells 18A, 18B and 18C; segment 12B includes cells 18D, 18E and 18F; and so forth.
Each of those cells include a central processing unit and a memory element, interconnected along an intracellular processor bus (not shown). In accord with the preferred practice of the invention, the memory element contained in each cells stores all control and data signals used by its associated central processing unit.
As further illustrated, each domain(0) segment may be characterized as having a bus element providing a co~ nication pathway for transferring information-representative signals between the cells of the segment. Thus, illustrated segment 12A i8 characterized by bus 20A, segment 12B by 20B, segment 12C by 20C, ~ cetera. As described in greater detail below, information-representative signals are ~ ~ -13- 1333727 1 passed between the cells 18A, 18B and 18C of exemplary segment 12A by way of the memory elements associated with each of those cells. Specific interfaces between those memory elements and the bus 20A are provided by cell interface units 22A, 22B and 22C, as shown. Similar direct communication pathways are established in segments 12B, 12C and 12D between their respective cells 18D, 18E, ... 18R by cell interface units 22D, 22E, ... 22R, as illustrated.
lo As shown in the illustration and noted above, the remaining information transfer domains, i.e., domain(l) and domain(2), each include one or more corresponding domain segments. The number of segments in each successive segment being less than the number of segments in the prior one. Thus, domain(l)'s two segments 14A and 148 number fewer than domain(O)'s sis 12A, 12B ... 12F, while domain(2), having only segment 16, includes the fewest of all. Each of the segments in domain(l) and domain(2), the ~higher~ domains, include a bus element for transferring information-representative signals within the respective segments. In the illustration, domain(l) segments 14A and 14B include bus elements 24A and 24B, respectively, while domain(2) segment 16 includes bus element 26.
The segment ~uses serve to transfer information between the components elements of each segment, that i8, between the segment's plural domain routing elements. The routing elements themselves provide a mechanism for transferring information between associated seqments of successive domains.
Routing elements 28A, 28B and 28C, for esample, provide a means for transferring information to and from domain(l) segment 14A and each of domain(0) _ -14- 13~3727 1 segments 12A, 12B and 12C, respectively. Similarly, routing elements 28D, 28E and 28F provide a means for transferring information to and from domain(l) segment 14B and each of domain(0) segments 12D, 12E
and 12F, respectively. Further, domain routing elements 30A and 30B provide an information transfer pathway between domain(2) segment 16 and domain(l) segments 14A and 14B, as shown.
The domain routing elements interface their respective segments via interconnections at the bus elements. Thus, domain routing element 28A
interfaces bus elements 20A and 24A at cell interface units 32A and 34A, respectively, while element 28B
interfaces bus elements 20B and 24B at cell interface units 32B and 34B, respectively, and so forth.
Similarly, routing elements 30A and 30B interface their respective buses, i.e., 24A, 24B and 26, at cell interface units 36A, 36B, 38A and 38B, as shown.
Figure 1 illustrates further a preferred mechanism interconnecting remote domains and cells in a digital data processing system constructed in accord with the invention. Cell 18R, which resides at a point physically remote from bus segment 20F, is coupled with that bus and its associated cells (18P
and 180) via a fiber optic transmission line, indicated by a dashed line. A remote interface unit 19 provides a physical interface between the cell interface 22R and the remote cell 18R. ~he remote cell 18R is constructed and operated similarly to thé
other illustrated cells and includes a remote interface unit for coupling the fiber optic link at its remote end.

-15- 13337~7 1 In a like manner, domain segments 12F and 14B are interconnected via a fiber optic link from their parent segments. As indicated, the respecti~e domain routinq units 28F and 30B each comprise two remotely coupled parts. With respect to domain routing unit 28F, for example, a first part is linked directly via a standard bus interconnect with cell interface 34F of segment 14B, while a second part is linked directly with cell interface unit 32F of segment 12F. These two parts, which are identically constructed, are coupled via a fiber optic link, indicated by a dashed line. AS above, a physical interface between the domain routing unit parts and the fiber optic media is provided by a remote interface unit (not shown).
Figure 2A depicts a preferred memory configuration providing data coherence in a multiprocessing system of the type, for esample, described above. The illustrated system includes plural central processing units 40 (A), 40 (B) and 40(C) coupled, respectively, to associated memory elements 42(A), 42(B) and 42(C). Communications between the the processing and memory units of each pair are carried along buses 44A, 44B and 44C, as shown. The illustrated system further includes memory management element 46 for accessing information-representative signals stored in memory elements 44A, 44B and 44C via buses 48(A), 48(B) and 48(C), respectively.
In the illustrated embodiment, the central processing units 40A, 40B and 40C each include access ; request element, labelled SOA, 50B and 50C, respectively. These access request elements generate signals representative of requests for or access to 1 an information stored in the memory elements 42A, 42B
and 42C. Among the types of access request signals generated by elements 50A, 50B and 50C i8 the ownership-reguest signal, representing requests for for priority access to an information-representative signal stored in the memories. In a preferred embodiment, access request elements 50A, 50B and 50C
comprise a subset of an instruction subset implemented on CPU's 40A, 40B and 40C. This instruction subset is described below.
The memory elements 40A, 40B and 40C include control elements 52A, 52B and 52C, respectively.
Each of these control units interfaces a data storage area 54A, 54B and 54C via a corresponding directory element 56A, 56B and 56C, as shown. Stores 54A, 54B
and 54C are utilized by the illustrated system to provide physical storage space for data and instruction signals needed by their respective central processinq units. Thus, store 54A maintains data and control information used by CPU 40A, while stores 54B and 54C maintain such information used by central processing units 40B and 40C, respectively.
The information signals maintained in each of the stores are identified by unique descriptors, corresponding to the signals' system addresses.
Those descriptors are stored in address storage locations of the corresponding directory. While the descriptors are considered unigue, multiple copies of some descriptors may e~ist among the memory elements 42A, 4B and 42C where those copies themselves identify copies of the same data element.
Access request signals generated by the central processing units 40A, 40B and 40C include, along with other control information, an SA request -17- 1~33727 1 portion matching the SA address of the requested information signal. The control elements 52A, 52B
and 52C respond to access-request signals generated their respective central processing units 40A, 40B
and 40C for determining whether the requested information-representative signal is stored in the corresponding storage element 54A, 54B and 54C. If so, that item of information is transferred for use by the requesting processor. If not, the control unit 52A, 52B, 52C transmits the access-request signal to said memory management element along lines 48A, 48B and 48C.
In an effort to satisfy a pending information access request, the memory management element broadcasts an access-request signal received from the requesting central processing unit to the memory elements associated with the other central processing units. By way of a cell interface unit, described below, the memory management element effects comparison of the SA of an access request signal with the descriptors stored in the directories 56A, 56B and 56C of each of the memory elements to determine whether the requested signal is stored in any of those elements. If so, the requested signal, or a copy thereof, is transferred via the memory management element 46 to the memory element associated with the requesting central processing unit. If the reguested information signal is not found amonq the memory elements 42A, 42B and 42C, the operating system can effect a search among the system's peripheral devices (not shown) in a manner described below.
Within the illustrated multiprocessor system, data coherency is maintained through action -1 of the memory management element on memory stores 54A, 54B and 54C and their associated directories 56A, 56B and 56C. More particularly, following generation of an ownership-access request by a first CPU~memory pair (e.g., CPU 40C and its associated memory element 42C), the memory management element 46 effects allocation of space to hold the requested data in the store of the memory element of that pair ~e.g., data store 54C of memory element 42C).
lo Concurrent with the transfer of the requested information-representative signal from the memory element in which it was previously stored (e.g., memory element 42A), the memory management element deallocates that physical storage space which had been previously allocated for storage of thç
requested signal.
The aforementioned actions of the memory management element and, more particularly, the data coherence element are illustrated in Figures 2A and 2B. In the first of those drawings, information signals DATUM(O), DATUM(l) and DATUM(2) are stored in the data store of the memory element 42A partnered with CPU 40A. Descriptors ~foo,~ ~bar~ and ~bas~
which correspond, respectively, to those data signals are stored in directory 56A. Each such descriptor includes a pointer indicating the location of itæ
associated information signal in the store 42A.
In the memory element 42B partnered to CPU
40B, the illustrated æystem ætores information æignals DATUM(3) and DATUM(2). Corresponding to each of those data elementæ are descriptoræ ~car~ and ~bas,~ retained in directory 56B. DATUM(2), and its descriptor ~bas,~ are copied from ætore 42A and, therefore, retain the æame labels.

-l9- 133~727 The system illustrated in Figure 2A does not store any data in the memory element 54C partnered to CPU 40C.
Figure 2B illustrates actions effected by the memory management system 46A following issuance of an ownership-access request by one of the central processing units. In particular, the illustration depicts the movement of information signal DATUM(0) following issuance of an ownership-access request for that signal by CPU 40C. At the outset, in response to the request signal, the memory management element 46 allocates physical storage space in the store 54C
of the memory element partnered with CPU 40C. The memory management element 46 also moves the requested information signal DATUM(0) from store 54A, where it had previously been stored, to the requestor's store 54C, while concurrently deallocating that space in store 54A which had previously held the requested signal. Along with moving the requested information signal, the memory management element 46 also effects invalidation of the descriptor ~foo~ in directory 56A, where it had previously been used to identify DATUM(0) in store 54A, and reallocation of that same descriptor in directory 56C, where it will subsequently be used to identify the siqnal in store 54C.
In the preferred embodiment, the memory management element 46 includes a mechanism for assigning access state information to the data and ~ control signals stored in the memory elements 42A, 42B and 42C. These access states, which include the invalid, read-only, owner and atomic states, govern the manner in which data may be accessed by specific processors. A datum which i8 stored in a memory _ -20- 1 3 3 3~ 27 1 element whose associated CPU maintains priority access over that datum is assigned an ownership state. While, a datum which is stored in a memory element whose associated CPU does not maintain priority access over that datum is assigned a read-only state. Further, a purported datum which associated with ~bad~ data is assiqned the invalid state.
- Figure 3 depicts a preferred configuration for exemplary domain(0) seqment 12A of Figure 1. The segment 12A includes processing cells 18A, 18B and 18C interconnected by cell interconnects 22A, 22B and 22c along bus segment 20A. Domain routing unit 28A
provides an interconnection between the domain(0) segment 12A and if parent, domain(l) segment 14a of Figure 1. This routing unit 28A is coupled along bus 20A by way of cell interconnect 32A, as shown. The structure of illustrated bus segment 20A, as well as its interrelationship with cell interconnects 22A, 22B, 22C and 32A is more fully discussed in copending, commonly assigned, Canadian Patent Application Serial No. 582,550, entitlea ~Interconnection System for Multiprocessing Structure,~ filed on November 8, 1988. Further description of a preferred cell interconnect structure is provided in Appendi~ A, filed herewith.
Figure 4 depicts a preferred structure for processing cells 18A, 18B . . . 18R. The illustrated processing cell 18A includes a central processing unit 58 coupled with e~ternal device interface 60, data subcache 62 and instruction subcache 64 over processor bus 66 and instruction bus 68, respectively. Interface 60, which provides ~' ' l communications with esternal devices, e.q., disk drives, over esternal device bus, is constructed in a manner conventional to the art.
Processor 58 can comprise any one of several commercially available processors, for esample, the Motorola 68000 CPU, adapted to interface subcaches 62 and 64, under control of a subcache co-esecution unit acting through data and address control lines 69A and 69B, in a manner conventional to the art, and further adapted to execute memory instructions as described below. Schematics for a preferred central processing unit are provided in Appendis B, filed herewith. A
description of a preferred processor interface is provided in Appendi~ C, filed herewith.
Processing cell 18A further includes data memory units 72A and 72B coupled, via cache control units 74A and 74B, to cache bus 76. Cache control units 74C and 74D, in turn, provide coupling between cache bus 76 and processing and data buses 66 and 68. As indicated in the drawing, bus 78 provides an interconnection between cache bus 76 and the domain(0) bus segment 20A associated with illustrated cell. A preferred construction for cache control units 74A, 74B, 74C and 74D is provided in Appendis D, filed herewith.
- In a preferred embodiment, data caches 72A
and 72B dynamic random access memory devices, each capable of storing up to 8 Mbytes of data. The subcaches 62 and 64 are static random access memory devices, the former capable of storing up to 512k bytes of data, the latter of up to 256k bytes of instruction information. bs illustrated, cache and processor buses 76 and 64 provide 64-bit transmission pathways, while instruction bus 68 provides a 32-bit * Trade Mark - -- 133372 t l transmission pathway. A preferred construction of cache bus 76 is providea in Appendis E, filea herewith.
Those skilled in the art will understand that illustrated CPU 58 represents a conventional central processing unit and, more generally, any device capable of issuing memory requests, e.g., an i/o controller or other special purpose processing element.

The MemorY Mana~ement System A multiprocessing system lO constructed in accord with a preferred embodiment of the invention permits access to individual data elements stored within processing cells 18A, 18B, . . . 18R by reference to a uni~ue system virtual address (SVA) associated with each datum. Implementation of this capability is provided by the combined actions of the memory management system 46, the subcaches 62, 64 and the caches 72A, 72B. In this regard, it will be appreciated that the memory management system 46 includes cache control units 74A, 74B, 74C and 74D, with their related interface circuitry. It will further be appreciated that the aforementioned elements are collectively referred to as the ~memory system.~
A complete understanding of the structure and operation of the memory system may be attainea through recognition of its architectural features, enumerated below:
Data Storage -- The memory in each cache is divided into pages, each of which may be dynamically assigned to some page of SVA space. The memory system maintains usage and status information about the data in each cache to facilitate efficient migration to and from secondary storage.

1 Data Locality -- The memory system keeps data recently referenced by a processor in the subcache or cache in the same cell of that processor, Data Movement -- The memory system moves data to the cache of the processor referencing it.
Data Sharing -- The memory system keeps copies of SVA data in more than one cache to facilitate efficient data sharing by parallel programs.
Data Coherence -- The memory system lo implements the strongly ordered coherent memory model and the transaction model.
With regard to the last point, those skilled in the art will appreciate that a system is ~sequentially consistent~ if the result of any esecution is the same as if the operations of all the processors were esecuted in some sequential order, and the operations of each individual processor appear in this sequence in the order specified by its program.
Moreover, storage accesses are considered ~strongly ordered~ if accesses to data by any one processor are initiated, issued and performed in program order and; if at the time when a store by processor I is observed by processor K, all accesses to data performed with respect to I before the issuing of the store must be performed with respect to K. By contrast, storage accesses are weakly ordered if accesses to synchronizing variables are strongly ordered and; if no access to synchronizing variable is issued in a processor before all previous data accesses have been performed and; if no access to data is issued by a processor before a previous access to a synchronizing variable has been performed.

_ -24- 1 3 3 3 7 2 ~

1 A coherent system with strong ordering of events is seguentially consistent.
In the illustrated embodiment, the memory system stores data in units of pages and subpages, with each page containing 4k bytes and each subpage containing 64 bytes. The memory system allocates storage in the caches 74A, 74B on a page basis. Each page of SVA space is either entirely represented in the system or not represented at all. The memory system shares data between caches in units of subpages. In the description which follows, the term ~caches~ refers to the cache storage elements 74A, 74B of the respective processing cells.
The organization of SVA space within the illustrated system is a major departure from ordinary virtual memory schemes. Conventional architectures include a software controlled page-level translation mechanism that maps system addresses to physical memory addressor generates missing page esceptions.
In these schemes, the software is responsible for multiplesing the page table(s) among all the segments in use. In the architecture of the illustrated system, there is no software controlled page-level translation mechanism. The memory system can handle a significant portion of the address space management normally performed by software in conventional architectures. These management responsibilities include:
(1) maintaining page usage and status information, (2) reusing old pages, (3) synchronizing and ensuring coherence of shared data access amongst multiple processors, and ~ ~ -25- 1333727 1 (4) migrating data and copies of data on a subpage basis from place to place in the system to keep data nearest to the processors that are using it most frequently.

The illustrated system's processors, e.g., processors 40A, 40B, 40C, communicate with the memory system via two primary logical interfaces. The first is the data access interface, which is implemented by the load and store instructions. In data access mode, the processor presents the memory system with an SVA and access mode information, and the memory system attempts to satisfy that access by finding the subpage containing the data and returning it.
The second logical interface mode is control access, which is implemented by memory system control instructions. In control access, the processor instructs the memory system to perform some side effect or return some information other than the actual data from a page. In addition to the primary interfaces, system software uses control locations in SPA space for configuration, maintenance, fault recovery, and diagnosis.

Cache Structure The caches, e.g., elements 72A, 728 of cell 18A, stores information in units of pages, i.e., 4096 bytes. Each page of SVA space is either entirely present in the caches or not present at all. Each individual cache, e.g., the combination of elements 72A and 72B of cell 18A, allocates space for data on a page by page basiæ. Each cache 8toreæ data on a subpage by subpage basis. Therefore, when a page of SVA space is resident in the system, the following are true:
(1) One or more caches allocates a page of ætorage to the page, each subpage of the page i8 stored on one or more of the caches with space allocated, but (2) Each cache with space allocated for a page may or may not contain a copy of all of the page's subpages.

The associations between cache pages and SVA
pages are recorded by each cache in its cache directory, e.g., element 56A. Each cache directory is made up of descriptors. There is one descriptor for each page of memory in a cache. At a particular time, each descriptor is either valid or invalid. If a descriptor is valid, then the corresponding cache memory page is associated with a page of SVA space, and the descriptor records the associated SVA page address and state information. If a descriptor is invalid, then the corresponding cache memory page is not in use.
Each cache directory 46A acts as a content-addressable memory. This permits a cache to locate a descriptor for a particular page of SVA
space without an iterative search through all of its descriptors. Each cache directory is implemented as a 32 way set-associative memory with 128 setæ. All of the pages of SVA space are divided into 128 eguivalence classes. A descriptor for a page can only be stored in the set of a cache directory that corresponds to the page' 8 eguivalence claæs. The equivalence class is selected by SVAtl8:12]. At any given time, a cache can store no more than 32 pages ~ 27- 1333727 1 with the same value for SVAtl8:121, since that are 32 elements in each set.
The organization of the cache directory is shown in Figure 5. SVAtl8:12~ selects a set. Each of the descriptors in the selected set i8 simultaneously compared against SVAt63:191. If one of the elements of the set is a descriptor for the desired page, the corresponding comparator will indicate a match. The indes in the set of the lo matching descriptor, concatenated with the set number, identifies a page in the cache. If no descriptor in the set matches, the cache signals a missing_page exception. If more than one descriptor matches, the cache siqnals a multiple_descriptor_match exception.
Preferably, SVAtl8:121 is used as a hash function over SVA addresses to select a set. System software assigns SVA addresses so that this hash function qives qood performance in common cases. Two important distribution cases are produced by referencing many pages of a single segment and by referencing the first page of many seqments. The use of SVAtl8:12~ to select a cache set produces qood cache behavior for contiquous groups of pages, since 128 contiquous pages can all reside in a set.
However, this ~ey produces poor hashinq behavior for many paqes with the same value in that field. System software avoids this situation by applyinq a hash function when allocating SVA space to contest seqments.
According to a preferred practice, descriptors contain the following fields, the bit-size of each of which is indicated in parentheses:

---28- 1~ 3 3~ 27 l descriptor.valid (l) A cache sets this bit flag to one to allocate the corresponding page of cache memory to a page of SVA space, and zero otherwise. If descriptor.valid is zero, then none of the other fields are meaninqful.
descriptor.tag (45) Bits t63:19] of an SVA. System software sets this field to identify the particular paqe of SVA space specified by corresponding descriptor.
descriptor.modified (l) A cache sets this bit flag to one when any data is modified in the page. System software sets descriptor.modified to zero to acknowledge the modification of the page.
descriptor.atomic_modified (l) A cache sets this bit flag to one when any subpage of this page undergoes a transition into or out of atomic state. System software sets descriptor.atomic_modified to zero to ac~nowledge the change in atomic state.
descriptor.held (l) Software sets the bit flag to indicate that the descriptor may not be invalidated by the cache even if no subpages are present in the cache.
descriptor.LRU_position (S) The cache maintains this field as the current position of the descriptor in its set from Most Recently Used (0) to Least Recently Used (31).
descriptor.LRU_insert_indes (2) Software sets thiæ field to bias the treatment of the page by the cache's LRU
maintenance.
descriptor.no_write ~l) A flag. Software sets this field to prevent modifications to the page by the local processor. An attempt to modify the page fails, and is signalled back to the processor. The processor siqnals a page_no_write exception.
descriptor.no_atomic (l) A flag. Software sets this field to prevent any cache from acquiring atomic or pending atomic state on any subpage of this page.
An attempt to acquire an atomic state fails, and is signalled back to the processor. The processor signals a page_no_atomic esception.
descriptor.no_owner ~1) Descriptor.no_owner prevents this cache from acquiring ownership of this page. Any attempt to acquire ownership fails, and is signalled back to the processor. The processor signals a page_no_owner exception.
descriptor.owner_limit (2) Descriptor.owner_limit limits ownership to subpages of the page to a particular cache, domain(0), or domainl in the domain hierarchy descriptor.subcache ~l) Set by cache to record that the corresponding subpaqe is subcached in the processor on the cache's cell.
descriptor.subpage_state (3) The subpage state field is set by the cache to record the state of each subpage.
descriptor.summary (2) Summarizes subpage state field corresponding to four consecutive subpages.

If descriptor.no_write is set, write accesses to the page result in a page_no_write esception. System software can trap page reads by keeping a table of pages to be trapped, and refusing to create an SVA page for them. Then, it can translate missing_page esceptions into software generated page_no_read esceptions.

_30_ 1 33 3727 1 Descriptor.no_write can be used to implement an copy-on-access scheme, which in turn can be used as an approsimation of 'copy-on-write.' When a process forks, the pages of the forkinq process's address space are set to take page_no_write esceptions. The child process's address space segments are left sparse. When the child process references a page that has not yet been written by the parent, the page fault is satisfied by making a copy of the corresponding page of the parent process, and the descriptor.no_write is cleared for that page. If the parent writes a page before the child has copied it, the page_no_write handler copies the page into the child address space and then clears descriptor.no_write.
If the descriptor.held is 1 in a descriptor, then the descriptor's cache is prevented from invalidating it. When the first subpage arrives after the subpages of a page with a held descriptor became invalid, all of the field of the descriptor except descriptor.tag, descriptor.held, descriptor.LRU_insert_indes and descriptor.LRU_in-sert_priority are reinitialized as if the descriptor had not esisted when the subpage arrived.
Descriptor.held is not propagated from one cache to another.
Descriptor.owner_limit limits ownership of subpages of the page to a particular cache or domain(0) in the system bus hierarchy. The following list shows the values of descriptor.owner_limit, and the semantics from the point of view of an owning cache responding to reguests from other caches.
~1) Cache_owner_limit - the local cache will not relinquish ownership to any 1 -31- 13~ 3727 other cache. If another cache requests ownership, it receives an error response.
(2) DomainO_owner_limit - the local cache will not relinquish ownership to any cache that is not in the same domain(O).
(3) Domainl_owner_limit - the local cache will not relinquish ownership to any cache that is not in the same domainl.

(4) Default_owner_limit - any cache may be the owner of the subpages of the page.

Descriptor.owner_limit is propagated to other caches as follows: so long as all of the subpages of a descriptor are read-only copies, descriptor.owner_limit is alwayæ
Default_owner_limit. When a new cache becomes the owner of a subpage, it copies the value of descriptor.owner_limit from the old owner.
If descriptor.no_owner is 1 in a descriptor, then the descriptor's cache cannot acquire an ownership state for any subpages of the page described by the descriptor. A cache containing a descriptor with descriptor.no_owner of 1 never responds to requests from other caches escept to indicate that it is holding the copy.
Descriptor.no_owner is not propagated from one cache to another.
If descriptor.no_atomic is 1 in a descriptor, then the descriptors cache cannot acquire atomic or pending atomic ownership states for any subpages of the page described by the descriptor. A
processor attempt to set atomic or pending atomic ownership state failæ, and is signalled bac~ to the 1 processor. The processor signals a paqe_no_atomic exception. Descriptor.no_atomic is propagated from one cache to another.
Descriptor.summary summarizes subpage state field corresponding to four consecutive subpages.
There is one two-bit field for each of the 12 sets of four subpages represented by the descriptor. The following is a list of summary states:
all invalid -- subpage state of all four subpages are invalid.
all exclusive -- subpage state of all four subpages are exclusive owner.
no owner -- subpaqe state of all four subpages are either invalid or read only.

owner -- one or more subpages are either atomic owner, exclusive owner or nonexclusive owner states. If all four subpages are exclusive owner state, all exclusive summary should be used.

The illustrated memory elements, e.g., 42A, 42B, 42C, detect errors, for example, while e~ecuting a synchronous request from its local processor. The element signals the error in its response to the request. The local processor then signals a corresponding exception. When a memory element detects an error while e~ecuting a request from a remote cell, it sends an interrupt to its local processor and responds to the request with an error reply. In the descriptions that follow, the e~pression ~the cache signals an e~ception~ is an abbreviation for this process.
Each memory includes a Cache Activity Descriptor Table (CADT) ~not shown), in which it - _ -33- 1333727 1 maintains the status of ongoing activities. When a memory element detects an error in responding to a reguest from its domain~0) or in e~ecuting an asynchronous control instruction or a remote control instruction, it notes the error in a descriptor in the CADT before sending an interrupt. Software reads the CADT to identify the particular source and type of error. Software resets the CADT to acknowledge receipt of the error.
Subpa~es and Data Sharing When a page is resident in the memory system, each of its subpages is resident in one or more of the caches. When a subpage is resident in a cache, the descriptor in that cache for the page containing that subpage records the presence of that subpage in one of several states. The state of the subpage in a cache determines two things:
1) What operations that cache's local processor may perform on the data present in the subpage; and 2) What responses, if any, that cache makes to requests for that subpage received over the domains from other caches.
The states of subpages in caches change over time as user programs request operations that require particular states. A set of transition rules specify the changes in subpage states that result from processor requests and inter-cache domain communications.
In order for a processor to complete a load or store, two conditions must be satisfied:
1) The subpage containing the data must be present in its local cache.

- _ -34- 1 33 3727 1 2) The local cache must hold the subpage in the appropriate state. The state determines whether the subpage can be modified and how the local cache responds to requests from other caches.
If either of these conditions i8 not satisfied, the processor's local cache communicates over the domains to acquire a copy of the subpage and~or to acquire the necessary state for the subpage. If the cache fails to satisfy the request, it returns an error indication to the processor, which signals an appropriate exception.
The instruction set includes several different forms of loan and store instructions that permit programs to request subpage states appropriate to the espected future data reference pattern of the current thread of control, as well as protocol between different threads of control in a parallel application.
In the test which follows there is first described the states and their transitions in terms of processor instructions and their effect on caches. This is followed by a description of the domain messages that are sent between the caches to implement those state transactions.

Subpage States The subpaqe states and their transition rules provide two general mechanisms to user programs esecuting on the illustrated system:
1) They transparently implement the strongly ordered sequentially consistent model of memory access for ordinary load and store accesses by the processors of the system.
2) They provide a set of transaction primitives that are used by programs to synchronize 1 parallel computations. These primitives can be applied to a variety of traditional and non-traditional synchronization mechanisms.
The states and their transitions are described in three groups. The first group are the basic states and transitions that implement the strongly ordered, sequentially consistent model of memory access. Second are the additional states that implement the transaction primitives. Finally, the transient states, which improve the performance of the memory system, are presented.
The processor subcaching system is divided into two sides: data and instruction. The data subcache 62 is orqanized in 64 bit words, like the cache. The instruction subcache 64 is organized into 32 bit half-words, since there re two 32 bit instructions in each 64 bit memory word. The data subcache stores .5Mbyte, and the instruction subcache .25Mbyte. Since the items in the instruction subcache are half-words, the two subcaches store the same number of items. The two sides of the subcache are similar in structure to the cache.

Subcache Data Units Subcache descriptors do not describe entire pages of SVA space. They describe different unitæ, called bloc~s. The size of a block is different on the two sides of the subcache. On the data side, blocks are the half the size of pages. On the instruction side, they are one guarter as large as pages. On both sides, each block is divided into 32 subblocks. The following table shows the relative sizes of blocks, subblocks and other items in the two subcaches.

_ -36- i3337~7 1 Comparison of Instruction and Data Subcaches total item subblocks bytes subblock size size ~block ~hlock size Data .50Mbyte 64 bits 32 2.OK 64 bytes Instruction .25Mbyte 32 bits 32 l.OK 32 bytes In the same way that the cache allocates a page of memory but copies data one subpage at a time, the subcache allocates pages and copies data one subblock at a time.
Subcache Organizatio~
The subcaches 62, 64 are organized similarly to the caches. Where the caches are 32-way set associative (each set contains 32 descriptors), the subcaches are 4 way set-associative. For the data side, the set number is bits tl6:11] of the SVA, and the tag bits ~63:17]. For the instruction side, the set number is bits tl5:10], and the tag is bits ~63:16]. The data subcaches maintain modification information for each subblock.

Subcache ~lock Replacement The subcaches implement a simple approsimation of the cache LRU scheme. Within a set, each subcache maintains the identity of the most recently referenced descriptor. When a descriptor is needed, one of the three descriptors that is not the most recently referenced descriptor is selected at random for replacement.
Subcache Block Writeback The data subcaches write modified ~ubblocks to their caches as described above in the section entitled 'Updates from the Subcache to the Cache.' 1 Basic States and Transition~
The basic model of data sharing is defined in terms of three classes of subpage states:
invalid, read-only, and owner. These three classes are ordered in strenqth according to the access that they permit; invalid states permit no access, read-only states permit load access, and owner states permit load and store access. Only one cache may hold a particular subpage in an owner state at any lo given time. The cache that holds a subpage in an owner state is called the owner of the subpage.
Ownership of each subpage moves from cache to cache as processors request ownership via store instructions and special load instructions that request ownership. Any number of caches may hold a particular subpage in a read-only state.

Basic States The sections below describe the state classes and how they interact to implement the strongly ordered, sequentially consistent model of memory access.

Invalid States When a subpage is not present in a cache, it is said to be in an invalid state with respect to that cache. If a processor reguests a load or store to a subpage which is in an invalid state in its local cache, then that cache must reguest a copy of the subpage in some other state in order to satisfy the data access. There are two invalid states:
invalid descriptor and invalid. When a particular cache has no descriptor for a particular page, then all of the subpages of that page are said 1 to be in invalid descriptor state in that cache.
Thus, subpageæ in invalid descriptor state are not esplicitly represented. When a particular cache has a descriptor for a particular page, but a particular subpage is not present in that cache, then that subpage is in invalid state. The two invalid states are distinguished because it is much easier for a subpage to undergo a transition to a read-only or owner state from invalid than from lo invalid descriptor. In the former case, a descriptor is already present. In the latter case, a descriptor must be allocated.

Read-Only States There is only one read-only state:
read-only.

Owner States There are two basic owner states:
non-esclusive and e~clusive. When a particular cache holds a particular subpage in non-esclusive state, any number of other caches may simultaneously hold that subpage in read-only state. When a particular cache holds a particular subpage in esclusive state, then no other cache may hold a copy so long as that cache retains esclusive state. When a cache holds a subpage in non-esclusive state, and the data in that subpage are modified, then that cache sends the modified data to all of the caches with read-only copies.

Basic State Transitions The basic state transitions can be illustrated by considering a subpage in esclusive state on a particular cache. The basic mechanism by which data moves from this first cache to other caches is the esecution of load and store instructions by processors other than the local processor of that first cache. The different load and store instructions, as well as the prefetch instructions, permit programs to request that their local cache acguired read-only, non-esclusive, or e~clusive state. If another cache reguests read-only state, then the first cache reduces its state from exclusive to non-esclusive and qrants read-only state to the requestor. If another cache requests non-exclusive state, then the first cache reduces its state to read-only and grants non-exclusive state to the requestor. If another cache requests esclusive state, then the first cache reduces its state to invalid and grants exclusive state to the requestor.
Ownership moves from cache to cache as processors request esclusive and non-esclusive states. When a cache requests non-esclusive ownership, any read-only copies are invalidated (undergo a transition to an invalid state).
When a cache acquires ownership of a subpage in order to satisfy a store instruction, it does not qrant that ownership to another cache until the store instruction is complete. In the case of non-esclusive state, a cache does not grant ownership to another cache until the new data from the store is sent to the caches with read-only copies. This rule provides the strongly ordered nature of the memory system, in that it ensures readers of a memory location to see modifications in the order that they are made.

~40- 1333727 1 When a particular subpage is in invalid state in a particular cache (i.e., a descriptor i8 already allocated, but the particular subpage is not present), and a copy of that subpage is available on the domain interconnection due to a request from some other cache, and at least one other cache in that cache's local domain(0) has copy, that cache will acquire a read-only copy of the subpage. The effect of this mechanism is to accelerate parallel lo computations, since it can remove the latency associated with reguesting a copy of a subpage from another cache.
When a non-esclusive owner modifies a subpage, it must send the modified data over the domains to any read-only copies. This permits very fast propagation of data from a producer to a consumer. However, it consumes domain bandwidth.
Therefore, the memory system includes two mechanisms for avoiding unnecessary non-exclusive owner states.
First, when a non-esclusive owner sends an update out over the domains, it receives a return receipt that includes whether any other caches actually hold read-only copies. If the receipt indicates that there are no read-only copies, then the owner changes the subpage's state from non-esclusive to esclusive, avoiding future updates. Second, when a cache receives an update for a subpage that it holds in read-only state, its action depends on whether that subpage is currently resident in the CPU's subcache.
If the subpage is not subcached, then the cache invalidates it. If the subpage is cached, then the cache removes it from the subcache. The effect of these actions is as follows: So long as a subpage is not modified, read-only copies of it propagate -_ -41- 1333727 1 throughout the memory system. When a subpaqe i8 modified, each read-only copy persists only if that copy is referenced at least as freguently as the subpage is modified.

Basic State Transition Transparency It is important to note that the basic mechanisms provide the strongly ordered memory access model to programs that use simple load and store lo instructions. Programs may use the forms of the load, store, and prefetch instructions that request particular states in order to improve their performance, and it is expected that in many cases compilers will perform the necessary analysis.
However, this analysis is optional.

Synchronization States and Transitions The synchronization states and related transitions implement the KSR transaction model. The transaction model is a primitive synchronization mechanism that can be used to implement a wide variety of synchronization protocols between proqrams. All of these protocols share the purpose of imposing an orderly structure in time on accesses to shared data.
The transaction model is based on two states, atomic and pending atomic, a set of instructions that e~plicitly reguest transitions to and from these states, and forms of the load and store instructions whose semantics are dependent on whether the subpage that they reference is currently in atomic state.

_ -42- 1 33372 7 1 Atomic State and Transaction~
The atomic state i8 the central feature of the transaction model. Atomic state i8 a stronger form of ownership than exclusive state. Subpage only enter and leave atomic state as a result of esplicit requests by programs.
Fundamentally, atomic state can be used to single-thread access to any subpage in SVA space.
When a processor e~ecutes an instruction that requests that a subpage enter atomic state, the instruction will only complete normally if the subpage is not in atomic state already. Thus, atomic state on a subpage can be used as a simple lock. The lock is locked by taking the subpage atomic, and unlocked by releasing it to exclusive.
A program requests that a subpage enter atomic state with one of the forms of the get instruction, and releases it with the rsp instruction. These instructions are described in more detail below.
A sequence of get, manipulate some protected information, and rsp is the simplest form of transaction. The following sections present more comples features of the transaction mechanism that permit the implementation of more sophisticated protocols. These protocols provide high performance for particular parallel programming applications.

Integrating Data and Synchronization In simple transactions, a subpage is used purely as a lock. The data in the subpage is not relevant. Some of the more sophisticated forms of synchronization mechanisms make use of the data in a subpage held in atomic state. The simplest case is ~ _43- 1333727 1 to use atomic state on a subpage as a lock on the data in that subpage. Programs take one or more subpages into atomic state, manipulate their contents, and release them.
Producers and Consumers - Blocking and Non-Blocking Load Instructions In the transactions described above, access to the protected data is strictly single-threaded.
However, there are important applications where one program produces a value and many consume it, and that the consumers need not see a consistent view of more than one full KSR word of data. In such a case, it is undesirable for each of the consumers to serially hold the subpage containing the data in atomic state, one after the other. The consumers must wait for the producer to release atomic state, but they can all read the result simultaneously.
Applications like this can be implemented using the blocking and non-blocking forms of load instructions. Non-blocking load instructions access the data in a subpage regardless of whether or not that subpage is in atomic state. These are used by ordinary programs and by the single-threaded transactions described above. Blocking load instructions only proceed normally if the subpage is nQ~ in atomic state. If the subpage referenced by a blocking load instruction is in atomic state, the instruction blocks until the subpage leaves atomic state. In a producer-consumer relationship, the producer(s) hold the subpage(s) containing the data in atomic state, while the consumers read the data using blocking load instructions.

-_ -44~ 1333727 1 Passive and Active Atomic State Requests - Pending Atomic State The get instructions actively request atomic state over the domains. In some applications, a program may have absolute knowledge that a particular subpage is already in atomic state. In this case, sending a request across the domains is pointless. Instead, the program can use the stop instruction to place the subpage in pending atomic lo state in the local cache, and depend upon another program to espel the subpage using the rspe instruction.
When a subpage is in pending atomic state in a particular cache, this indicates that atomic state is desired in that cache. If a message arrives over the domains in a cache that holds a particular subpage in pending atomic state that indicates that atomic state is available for that subpage, then that cache will take the subpage in atomic state. When a processor executes a stop instruction for a subpage, that subpage is placed in pending atomic state on the local cache. When another processor esecutes an rspe instruction, a message is sent across the domains indicating that atomic state is available for the subpage. When this message reaches a cache with the subpage in pending atomic state, that cache acquires atomic state.
It is important to note that messages of this kind pass all of the caches in the system in a single, well defined order. Thus, a series of caches can use seguences of the form stop, manipulate, rspe,to pass a synchronization token to each of themselves in turn.

1 Transient States and Transitions The transitive states are used automatically by the memory system to improve the performance of accesses to subpages in case of contention. There are three transient states: transient atomic, transient e~clusive, and transient non-esclusive.
These sdtatesd correspond to atomic, esclusive, and non-exclusive states, respectively. A particular subpage enters a transient state in a particular cache when that cache receives a request for the subpage to which it cannot respond immediately. If a subpage is in atomic state and another cache requests that subpage, that subpage enters transient atomic state in the holding cache. When the subpage is later released with an rsp instruction, the transient state forces the subpage to be espelled as if an rspe had been used. If a subpage is in exclusive or non-esclusive state and is subcached, and another cache requests that subpage, that subpaqe enters the corresponding transient state. When an up-to-date copy of the subpage is available for the subcache, the cache expels the subpage, making it available to the other cache(s).
A subpage enters a transient state on a cache due to a request by a single other cache.
However, any number of additional caches may make requests for the same subpage before the holding cache espels it. In this case, the æingle espulsion satisfies all of the requesting caches with a single message over the domains.
Detailed Transitions Between States The following is another list of the states. In this list, the most important conditions -1 for entering and leaving the state are described.
This list provides a more complete listing of the transitions than the introduction above, but the precise specifications of the state transitions are given in the tables provided in below. Some of the transitions are conditioned by LRU information.
invalid A subpage enters invalid descriptor descriptor state in a cache when the descriptor for its page is deallocated. A subpage lo leaves invalid state when a descriptor for its page is allocated in the cache. Unless descriptor.held is 1, a descriptor is automatically invalidated when each of its subpages is implicitly in invalid descriptor state.
invalid A subpage enters invalid state in a cache when another cache acquires exclusive or atomic state. A subpage leaves invalid state in a cache when that cache acquires a copy of the subpage in any state. A cache will acquire a copy of a subpage to satisfy a request from its local processor, in response to a data movement control instruction ~see below) or when a copy is available over the domains due to communication between other caches.
read-only A subpage enters read-only state in a cache from an invalid state when that cache requests a read-only copy, or when a copy is available over the domains due to communication between other caches and at least one other cache in the same domain(0) has a copy of the subpage. A subpage enters read-only state from non-esclusive or esclusive state when another cache requests non-esclusive state. A
subpage leaves read-only state when another cache requests esclusive or atomic state, or when the cache acguires an owner state.

_ ~47~ 1333727 1 When the nonexclusive owner of a subpage modifies that subpage, the owner sends the new data over the domains to update any read-only copies. At the time of such an update, if a cache has a subpage in read-only state and that subpage is in use by the cache' 8 local processor, then the cache updates the copy and replies to the update to indicate that it has a copy.
A subpage is defined to be in use in a processor when it is resident in the processor's subcache. If a cache has a subpage in read-only state and the subpage is not in use, then that cache invalidates the subpage and does not respond to the update.
nonesclusive owner A subpage enters non-exclusive state in a cache when that cache requests ownership and some other cache has a read-only copy. A subpage leaves non-esclusive state as follows: When a cache has a copy in non-esclusive state and another cache requests non-esclusive state, the holding cache responds to the reguest and changes its state to read-only, giving the non-exclusive state to the requesting cache. When a cache has a copy in non-esclusive state and another cache requests esclusive or atomic state, the holding cache responds to the request and invalidates its copy. When a cache holding a subpage in non-esclusive state receives an update from its local processor, it sends the new data to the other caches. If no other cache indicates that it is holding a copy, the holding cache changes the subpage'~
state to esclusive.
e~clusive A subpage enters esclusive state in a owner cache when that cache reguests ownership and no other cache has a read-only copy, or when that cache esplicitly requests esclusive state. A
subpage leaves esclusive state on any request for a copy. The response to 1 requests for different states is as follow~:
read-only - If the page is below BS
High in LRU priority, the holding cache responds granting esclusive state and invalidates its copy. If the page i8 above BS_High in LRU priority, the holding cache responds granting read-only state and changes its copy' 8 state to non-esclusive.
non-esclusi~e - If the subpage i8 subcached, the holding cache responds granting non-esclusive state and changes its copy's state to read-only.
If the subpage is not subcached, the holding cache responds granting exclusive state and invalidates its copy.
esclusive or atomic - The holding cache responds to the request and invalidates its copy.
atomic A subpage enters atomic state in a cache in one of two ways. First, if the local processor esecutes a aet instruction, and the subpage is not in atomic state, then the local cache of the requesting processor will acquire the subpage in atomic state. Second, if a cache holds a subpage in pending atomic state, and the subpage is espelled from another cache holding it in atomic state, then that first cache will acquire atomic state.
A subpage leaves atomic state in a cache only when it is released by esplicit request from the cache's local processor.
pending A subpage enters pending atomic state atomic via the stop instruction.
A subpage leaves pending atomic state in two ways. If a subpage i8 in pending atomic state in a cache, and the local processor esecutes an rsp ~ -49- 1333727 1 instruction, then the subpage leaves pending atomic and becomes invalid. If a subpage is in pending atomic state in a cache, and that subpage is made available in atomic state via an expulsion, then that subpage enters atomic state from pending atomic state.
transient none~clusive owner transient e~clusive owner transient atomic owner If a cache holding a subpage in any owner state is unable to immediately respond, the holding cache marks the subpage transient. For e~ample, when a cache holds a subpage in atomic state and another cache reguests a copy in any state, the holding cache marks the subpage transient atomic, since a response cannot be issued while in atomic state.
Transient state is passed on responses and expulsions. It is cleared only after an expel traverses the domain without being acquired by some other cache.

Data Copying Strategy The interaction among states described above is a tradeoff between time and domain bandwidth spent waiting for a copy from another cache and time and bandwidth spent sending updated copies to other caches. When there are many read-only copies of a subpage in the system, then the changes that a read will find the data already in the local cache are increased. However, if there are any read-only copies in the system, then the owner must send out updates when modifying the subpage.
The following heuristics attempt to dynamically detect on a short term basis multiple read/writer sharing from single read/writer access.

_50_ 133~727 1 Multiple read~writer sharing is multiple read-only copies with high temporal locality and write updates with lower temporal locality. Retaining read-only copies is most efficient since multiple copies are read multiple times between updates. Updates ta~e place in a single domain operation. Single read/writer access is multiple read-only copies read-only copies with low temporal locality and write updates with much higher locality. Retaining lo read-only copies is less efficient since copies are updated multiple times between updates. A single read/write copy (e~clusive owner state) does not require a domain operation for write update.
Applying these two cases independently to all read-only copies allows transition from non-exclusive ownership with multiple read-only copies to esclusive ownership with no read-only copies. The strategy for balancing these considerations is as follows:
a. When a copy of a subpage is sent across the domains to satisfy a request, any cache that has a descriptor for a page but no copy of the subpage picks up a read-only copy from the message. This mechanism accelerates applications with high locality of reference.
b. When a cache sends an update for a subpage, every other cache with a copy of the subpage in read-only state which is not in use invalidates that copy. If a copy is subcached, it is considered ~in use~. When a copy i8 preserved in a processor'~
subcache, it is removed from the subcache.
This slows down the ne~t reference to that subpage from that processor. If it were not removed, the æubpage might remain in subcache indefinitely, compelling the owner to send updates. Since interconnect bandwidth limits total system performance, trading latency on one cache for global throughput improves net system performance.

-Sl- 1333727 1 c. The caches periodically remove read-only copies of subpages when the owner i8 in a different domain(0). This reduces the cost of updates, since intra-domain(0) messages are faster than inter-domain(0) messages.

The Processor Side The tables shown in Figures 6A and 6B
provide the precise specification of the action that a cache takes in response to data access requests from its local processor. There is one row of the table for each processor request to the cache. There is a column for each possible state of the subpage in the cache. The entry in the table states the message, if any, sent over the domains by a cache to satisfy the reguest when the subpage is in the specified state in that cache. The messages are defined below. When an entry includes ~-~state~, the local cache sets the subpage in state state after receiving a successful response to the message.

The Domain Side Caches send messages over the domains to acquire copies of subpages in particular states.
Each message consists of a request type, a descriptor, and the data for a subpage. The tables shown in Figures 7, 7A, 7B, 7C, and 7D provide the precise specification of how each cache responds to messages on the domain. The tables are divided into three sections: read operations, write operations, and response operations. Each section includes the definition of the operations. The tables give the state that results when a cache with a subpage in a specified state receives a particular message. In -l addition to the states, the tables are annotated with the following side effects and modifications:
respond The cache replies to the message with a copy of the subpage.
error The cache signals an exception.
working-set If the LRU priority of the page is lower than BS_High, then the subpage is invalidated in favor of the requestor unless the owner limit prohibits that transition. Otherwise, as shown.
subcached7 If the subpage is not subcached, then it is invalidated in favor of the request, unless the other limit prohibits that transition. Otherwise, as shown.
owner-limit?If the value of descriptor.owner_limit is Cache_owner_limit, then error. If it is DomainO_owner_limit and the source request is in a different domain(0), then reject. Otherwise, as specified.
update- If the subpage is subcached, remove it flush7 from subcache and respond to indicate that the copy exists. If the subpage is not subcached, invalidate it and do not respond at all.
domO-copy? If there are other copies in the local domain(0), then if there is already a copy in the cache, retain a read-only copy. If there is no copy in the cache, ac~uire a copy in read-only state. Otherwise, if there is a copy, invalidate it.
no change No change in state.
If both update-flush? and domO-copy? are specified, then either condition is sufficient to retain a copy.

_ ~53~ 1 3 33~ 27 1 Read Messages With particular reference to Figure 7A, read operations are used to acquire the state necessary for a processor operation. Once the subpage has been 'read' into the local cache, the operation can proceed.
Most of tbe read messages are simply reguests for the subpage in a particular state, and are named after the state. For example, read atomic requests atomic state. There are two read messages that have comples semantics: highest read-only and highest nonesclusive. Highest read-only searches the system in order of increasing domain distance, and takes the stron~est state available in the nearest cache. If there are any copies in the local domain(0), the copy in the strongest state responds and invalidates itself.
Highest nonexclusive has similar semantics, escept that caches with subpages in read-only state do not respond. Read one-time copy reguests a copy of subpage without changing subpage state.

Write Messaaes Referring to Figure 7B, write operations are used to send modified data out to other caches or to force other caches to give up 8tate.
Write Update is sent by the none~clusive owner when the subpage is modified.
Write Invalidate is 8ent by the nonesclusive owner when the nonesclusive owner needs to acquire esclusive state. (To acquire atomic state, a nonesclusive owner use8 write invalidate to get esclusive state, and then internally changed the state to ~54~ 1 333~ 2 l 1 atomic before allowing any other cache to request ownership.) Write Esclusive Recombine is used to e~pel a subpage that is in transient exclusive state or which has been explicitly expelled by a CPU
instruction. It is also sent by a cache with a subpage in exclusive state to find another cache to take responsibility for the subpage on the basis of LRU priority. Once one cache with a descriptor has responded to this message no other cache responds. If the message has not been responded to, and the cache has a descriptor for the page with an LRU_priority of less that WS_Top, the cache sets the state to exclusive owner and responds. This message is used at the end of a transaction to send a subpage to a cache that has re~uested it during the transaction. This message is also used in LRU maintenance.
Write Non-E~clusive Recombine is used to expel a subpage that is in transient non-exclusive state or which has been explicitly espelled by a CPU
instruction. It is also sent by a cache with a subpage in non-exclusive state to find another cache to take responsibility for the subpage on the basis of LRU priority. Once one cache with a descriptor has responded to this message no other cache responds. If the message has not been responded to, and the cache has a descriptor for the page with an LRU_priority of less that WS_Top, the cache sets the state to nonesclusive owner and responds. This message is used to in LRU maintenance.

Both of the recombine messages are limited by descriptor.owner_limit. When descriptor.owner limit iæ DomainO_owner_limit, a recombine message is not delivered outside of the originating domain(0).
When descriptor.owner_limit is Cache_owner_limit, a ~ 55- 1333727 1 recombine message iæ never sent. Note that the indication ~recombine?~ indicates the LRU position comparison described above.

Response Message~
With reference to Figures 7C and 7D, response messages are sent by caches that respond to read messages. The first table shows the action, if any, taken for a response message by a cache that already holds the subpage in the specified state.
The second table shows the action of a cache that is awaiting a response to the specified type of request for the subpage. There are two cases shown in the tables:
1) A response may be detectable as an error. For example, if a cache holds a subpage exclusively and another cache sends an exclusive response, there is an inconsistency, and the holding cache signals an exception.
2) If a cache has a descriptor for the page but no copy of the subpage, it will pick up a copy under some conditions.

Descriptor Movement When a cache receives a copy of a subpage in invalid descriptor state, it initializes its descriptor by copying most of the fields of the descriptor on the source cache. LRS_position, LRU
insert indes, subcache, subpage_state, held and no_ owner are never copied. Owner_limit is handled specifically.

1 Processor Data Accesses and Domain Requests A processor makes data requests to its local cache to satisfy load and store instructions and co-processor operations. A cache makes requests to its local processor to force the processor to invalidate its copy of a subpage in su~cache.

Load and Store Instruction~
A processor passes load and store instructions to its local cache as requests when the subpage containing the referenced address is not present in the subcache in the required state. The different types of load and store instructions pass information to the local cache about the access patterns of the following instructions. For example, if the sequence of the instructions is a load followed by a store, and the subpage containing the data item is not yet resident in the local cache, it is more efficient to acquire ownership for the load than to get a read-only copy for the load instruction and then communicate over the domains a second time to acquire ownership for the store instruction.
The different forms of load and store instructions are described below. Each description 2s begins with a brief summary of the semantics of the instruction, and continues with a detailed description of the cache'æ action.
All of the load instructions described here have two forms: blocking and non-blocking. These forms control the behavior of the load instructions with respect to atomic state. If a processor e~ecutes a blocking load instruction that references a subpage in atomic state, that instruction will wait until the subpage leaves atomic state before -~57~ 1 333727 1 proceeding. If a processor executes a non-blocking load instruction that references a subpage in atomic state, that instruction will acquire atomic state in the local cache and proceed.
load (default) tldd~clddl The program will continue the current access pattern. If the subpage is already present in the cache, the local cache keeps the subpaqe in the same state. If it is not already present, the local cache requests the subpage in read-only state. The ldbd~cldbd forms of these instructions will block if the subpage is in atomic state, and wait for it to be released.
load (esclusive) [lde~clde]
The program will write the subpage in the following instruments, and esclusive state is preferable to non-e~clusive state. A program would use this when the data was expected to have little sharing, or when a series of writes was upcoming, and it was therefore worth extra work to acquire e~clusive state to avoid updating read-only copies.
The local cache requests the subpage in exclusive owner state. This allows the processor to write the subpage without updating read-only copies unless another cache gets a copy of the subpage in read-only state between the load and the store. The ldbe~cldbe forms of these instructions will block if the subpage is in atomic state, and wait for it to be released.
A particular e~ample of the use of load (e~clusive) is per-program data such as stacks. Generally, there will be no read-only copies of æuch data, since the only copy will be the one in use by the program. However, if a program moves from one processor to another, the new processor's local cache will have no copy, and the old processor's _ -58- 13~ 3727 1 local cache will continue to hold the subpage in exclusive state. If the program uses load (default), the local cache acquires the subpage in non-e~clusive state, leaving a read-only copy on the cache of the previous processor, and requiring inefficient updates.
Load (esclusive) instructions always load the data into the subcache in the same state that is acquired in the cache.
lo store (default) [st~cst] The program is unlikely store into this subpaqe in the following few instructions. The local cache maintains the existing state on the subpage.
If the subpage is atomic on some other cache, then the local cache acquires atomic state.
Store (default) instructions always load the data into the subcache in exclusive state.
load subpage (default) tldSPd~cldsPdl loan subpage (esclusive) tldsPe~cldsPe]
Load subpage is used to load a full subpage of data into processor or co-processor general registers. If the subpage is present in the subcache, it is loaded directly from the subcache.
If the subpage is not present in subcache, it is loaded directly from the local cell cache. An option to these instructions specifies whether, in the case that the data are loaded from the cell cache, they are stored in the subcache in addition to the target registers. The ldspbe~cldspbe forms of these instructions will block if the subpage is in atomic ~tate, and wait for it to be released.
The load subpage ~default) and load subpage (esclusive) instructions have corresponding semantics to the load ~59~ 13337~7 1 (default) and load (esclusive) instructions.
load subpage (one time) tldspo~cldspo]
Load subpage (one time) is used when the proqram does not intend to make any further references to the data in the subpage at any time in the near future. This instruction has no effect on the state of the subcache or any of the caches, escept in some cases to set transient state. If the data are available in the subcache, they are loaded from the subcache. If the data are not available in the subcache, but are available in the local cache, they are loaded from the local cache without being stored into the subcache. If the data are not available in the local cell at all, they are copied over the domains without disturbing the esisting state.
store subpage (default) tstsp~cstsp]
store subpage (esclusive) [stspe~cstspe]
Store subpage is used to store a full subpage of data from processor or co-processor general registers. If the subpage is present in the subcache, it is stored directly into the subcache.
If the subpage is not present in subcache, it is stored directly into the local cell cache. An option to these instructions specifies whether, in the case that the data is stored into the cell cache, it is also stored in the subcache.
instruction fetch Instruction fetches always fetch the subpage containing the data in read-only state.

Subpage Atomic State Instructions The subpage atomic instructions are the program interface to the get, stop, and release operations described above. These instructions esist 1 in several forms to permit precise tuning of parallel programs.
release subpage lrsp]
Release subpage is used to remove a subpage from pending atomic or atomic state. If the subpage is in pending atomic state in the local cache, it is set to invalid state. If the subpage is not in pending atomic state in the local cache, it is set to invalid state. If the subpage is not in pending atomic state in the local lo cache, but is in atomic state in some cache in the system, then it is set into esclusive state from atomic state in that cache. If the subpage is in transient atomic state in that cache, it is changed to transient esclusive state and then it is espelled, as per the release and espel subpage instruction below. If the subpage is not in pending atomic state in the local cache and is not in atomic state in any cache, then release subpage has no effect.
release & espel subpage [resp]
Release and expel subpage has the same semantics as release subpage, escept that if the subpage is changed from atomic to esclusive state, it is always espelled as if it were in transient atomic state.
get subpage [gspl get subpage & wait t9SPW]
get subpage, wait & load ~qspwld]
get subpage, wait & load subpage [qwldsp]
Get subpage reguests that a subpage be set into atomic state. For all forms of the get subpage instruction, if the subpage is not in atomic state in any cache, then the local cache acquires it in atomic state.
For the get subpage instruction, if the subpage is already atomic on the local cache, then the instructions signals an e~ception. If the subpage 1 is already atomic on some other cache, then the instruction proceeds.
Programs must use the mcksp instruction after gsp to determine if the attempt to take the subpage into atomic state succeeded.

For the other get subpage instructions, if the subpage is already atomic in any cache, the instruction waits until the subpage is released.
The local cache then acquires the subpage in atomic state.
The two load forms of the get subpage instruction have the same semantics as a gspw followed by the load instruction. The only difference is that the combined instructions are faster.
stop subpage [ssp]
stop subpage & wait tsspw]
stop subpage, wait & load tsspwld]
stop subpage, wait & load subpage [swldsp]
Stop subpage sets the state of a subpage in the local cache to pending atomic.
Stop subpage & wait sets the state of a subpage in the local cache to pending atomic, and then blocks until the subpage state changes from pending atomic to atomic.
Stop subpage, wait, and load is an indivisible combination of stop subpage & wait and load (default).
Stop subpage, wait, and load subpage is an indivisible combination of stop subpage & wait and load subpage (default).

release, espel & stop subpage [ressp]
wait, release, espel & stop subpage [wresspl get subpage, wait, release, espel & ætop subpage lgwressp]
load, release, espel & ~top ~ubpage tldressP]

--62- 1~33727 1 Release, espel and stop subpage is an indivisible combination of release &
e~pel subpage and stop subpage.
Wait, release ~ stop subpage is an indivisible combination of waiting for subpage to be in atomic state in local cache, release ~ e~pel subpage and stop subpage.
Get, wait, release, e~pel & stop subpage is an indivisible combination of get subpage and wait, release &
lo expel subpaqe and stop subpage.
Load, release and stop subpage is an indivisible combination of load (default), release & expel subpage and stop subpage.

Other Subpage Instructions Memcheck Subpage [mckspl Memcheck subpage checks the progress of an asynchronous memory system instruction for a subpages. It returns two values: a binary indication of whether an instruction was in progress and the current subpage state.
Prefetch Subpage ~copy) tpcspc, pdspc, pispc]
Prefetch Subpage ~none~clusive) tPSpcn~ pdspn, pispn]
Prefetch Subpage ~e~clusive) [scspe, pdspe, pispe]
Preetch Subpaqe requests that a copy of a subpage be acquired on the local cache in a specified state. Prefetch subpage specifies whether or not the subpage should be prefetched into the processor's instruction or data subcache. A subseguent load for the subpage blocks until the prefetch subpage has completed.

Pa~e Prefetch Instr~lctio~
Prefetch Cache Page ~copy) tPCPC]
Prefetch Cache Page ~nonesclusive) tPCpn]
Prefetch Cache Page ~esclusive) tPCpe]

~ ~ -63- 1333727 1 Prefetch cache page requests that all subpages of a page be acquired on the local cache in the specified state.

A more detailed description of a preferred memory instruction set, including processor load instructions, processor store instructions, and page manipulation instructions, is provided in Appendis F, filed herewith.

Updates from the Subcache to the Cache When a processor has a copy of a subpage in subcache, and that subpage is owned by that processor's local cache, the processor propagates modifications to the subpage to its local cache as follows:
If the local cache holds the subpage in exclusive state, then the processor propagates modifications to the cache when:

- the subpage is removed from subcache, or - the local cache receives a request for a copy of the subpage. In this case, the local cache esplicitly requests the updated copy.
- the processor is stalled. When the processor is stalled, it updates modified subpages in esclusive state to its local cache.

If a processor's local cache holds the subpage in non-esclusive state then the processor propagates each modification as it is completed.
A processor propagates modified information to its local cache with an Update data request.

~~

1 Forcing Subcache Invalidatio~
A cache forces its local processor to remove a subpage from subcache in order to invalidate the subpage in response to a request from another cache.

Requests from One Cache to Another In parallel to responding to requests from its local processor, each cache responds to messages from other caches deliverea by its local domain(0).
There are three types of messages: read, write, and response. A read message requests some other cache to respond with the data for a subpage. Each read message also requests a particular state, and both the cache that responds with the data and other caches with copies change the state of their copy of the subpage in order to satisfy the state request. a write message either supplies an updated copy of a subpage to caches with read-only copies, or directs other caches to change the state of their copies. A
response message is sent in response to a read message. Caches other than the original requestor take actions on response messages as specified below.
It is important to note that read and write message do not correspond to load and stors instructions. Both load and store instructions result in read messages to acguire a copy of the subpage in the appropriate state. A particular store instruction will not result in an immediate write message unless the subpage iæ held in nonesclusive state.

Cache Page Usaqe and Replacement The caches of a KSR system can be used by system software as part of a multilevel storage _ -65- 1333727 1 system. In such a system, physical memory i8 multiple~ed over a large address space via demand paging. The caches include features that accelerate the implementation of a multi-level storage system in which software moves data between the caches and secondary storage in units of SVA pages.

Caches as Two Storage Levels All of the caches together make up a system's primary storage. However, for some purposes, it is necessary to treat each individual cache as an independent primary store. This is because each cache can only hold a limited number of pages: 4096 pages in each cache, and 32 in any particular set. Since each page can only be stored in one set in each cache, a cache signals an exception when a full set prevents it from allocating a descriptor for a page. When such an esception is signalled, software must take action to make room in the full set.
When a particular set of a particular cache is full, there is no reason for software to assume that the entire memory system is correspondingly full. Thus, it is desirable for software to respond to a full set by moving a page from that set to the corresponding set of another cache. In taking this action, software treats the rest of the memory system as an additional level of storage between a particular cache with a full set and secondary storage, called backing store.

Strategies for ~ackina Store Management Referring to Figure 8, in order to use memory efficiently, software must use some strategy 5 1 for identifyinq an appropriate page to remove from a full set, and a appropriate target cache, if any, for the page. The caches include facilities that accelerate a class of strategies for this page replacement. To accelerate software's selection of a page for replacement within a set, each cache approximately orders the pages from Most Recently Used (MRU) to Least Recently Used (LRU). When a page is referenced, it moves to MRU. As other pages are referenced thereafter, it ages toward LRU. The LRU information accelerates strategies that replace the least recently used page.
To accelerate software's selection of a target cache for replacement between caches, each cache maintains an approximate measurement of the working set of the cache. The working set is a measurement of the number of pages which are in steady use by programs running on a cache's local processor over time, as distinct from pages referenced a few times or infrequently. Software measures the working set of each cache as a point between MRU and ~RU. Pages above the working set point are in the working set, while pages below have left the working set. The working set information accelerates a software strategy that treats the non-working set portion of each cache's memory as system backing store.

Automatic Page Movement and Removal A new page arrives when a cache'~ local proces80r references data in a subpage that is in invalid descriptor state. If the corresponding page is resident elsewhere in the system, the cache will copy its descriptor and the referenced subpage from ~ -67- 1333727 1 another cache. Eventually, this process will fill up cache sets. When data is extensively shared by programs running on multiple processors, this is a very frequent event. Therefore, each cache includes facilities to automatically move and remove pages in parallel with other computation to avoid the need for frequent software intervention required by full sets. These facilities use the LRU and working set information to:
recombine pages To recombine a page is to collect all of its subpages in one cache, and free the descriptors in other caches.
drop pages To drop a page is to remove an lS unmodified pages from all caches.
All of these automatic actions can be tuned or disabled by software, and are inhibited by descriptor.held. The following sections describe the circumstances in which the caches recombine, move, and drop pages.

Recombining Pages Each cache recombines pages from LRU up to the working set point, it is significantly less likely to be referenced again that if it is above the working set point. Therefore, each cache recombines pages when they pass the working set point. A cache uses the write e~clusive recombine or write non-e~clusive recombine message for each subpage to recombine a page. If the recombine messages fail to find another cache to take over the page, the recombining cache retains the data. If the recombine messages fail to find another cache to take over the 1 page, the recombining cache retains the data. In effect, it has found itself as the target of the recombine. Since pages are recombined as soon as possible after they leave the working set, any other cache with copies is likely to have the page in the working set. ~were it not in the working set in some other cache, that cache would have recombined it.) Since pages below the working set point are less likely to be referenced, most of the recombines that actually move data to another cache will be of pages that have recently left the working set. The pages below the working set that get recombined elsewhere will be pages that have been referenced since they left the working set, and so the recombine moves them to the cache that referenced them.

Dropping Pages Caches invalidate subpages and pages to make room for other pages. This is called dropping. A
cache will automatically drop a page which is below the working set point and which has subpages in read-only or invalid state (a read-only page). If a cache has no free descriptors and cannot allocate a descriptor by recombining a page, it will drop a read-only page that is not subcached and is anywhere in the MRU~LRU order. If a cache has no read-only pages, it will drop an unmodified page with subpages in invalid, read-only, or e~clusive state that i8 not subcached and i8 in the lower portion of the working set, as defined by the WS_Low register defined below.

-1 Software Working-Set-Related Action The following sections describe a software strategy that makes use of the cache facilities to implement a multi-level store.
Modified Pages When a modified page crosses the working set point, system software undertakes to write it to disk, so that it will be pure by the time that it reaches LRU. Since only some of the caches will be able to write a given page, by virtue of having a physical connection to the appropriate disk drive, modified pages must be migrated to the cache in a cell with an XIU connected to the secondary storage device for the page. Software moves pages to be written with copy or chng instructions.
Software sometimes has knowledge of the expected reference pattern for some data. If softwarè expects a page to be referenced only one, that page should be put into the LRU order someplace below MRU, to avoid displacing information that is more likely to be used later. In particular, if software is prefetching data that it won't reference for a while, and perhaps not reference it at all, it should not be inserted at ~RU. Software controls the insertion point by setting the appropriate LRU_insert_indes in the prefetch and chng instructions.

Cache Usage and Replacement Facilities Each cache maintains LRU state for all of the resident pages. The LRU data is maintained separately for each of the 128 sets of the descriptor associative memory, and orders the 32 pages in the -~70- 133372~

1 set according to their approximate time of last reference.

Basic LRU Maintenance Each cache maintains an LRU-MRU ordering of the descriptors in each set. The ordering i8 maintained in descriptor.LRU_priority. Each of the descriptors in a set has a value from (MRU) to 31 (LRU) in descriptor.LRU priority. Conceptually, when 10 - a page is referenced it moves to MRU. All of the other pages from MRU down to the referenced page's LRU priority then move down.
When a page is first subcached, descriptor.LRU_priority is set to zero, which inserts it at MRU. When the last subcached subpage of a page is evicted from the subcache, descriptor.LRU priority is set as specified by descriptor.LRU_insert_indes.
The insert indes selects an entry in LRU_insert_table, a per-cache table described below.
descriptor.LRU_priority is set to LRU_insert_table(descriptor.LRU_insert_indes) and the descriptor.LRU_priority is changed for other descriptors as appropriate to accommodate it. Note that if an entry of the LRU_insert_table is set close enough to MRU, then paqes evicted from subcache will be inserted closer to MRU than paqes in subcache.

Working Set Measurement Each cache has an array of 32 working set rate counters, 16 bits. The counters freeze at 216-1. When a page is subcached, the bucket corresponding to its current LRU position is incremented. By periodically reading and clearing the buckets, software can determine the approsimate ~ _ -71- 1333727 1 working set size. Software can attempt to maintain the working set for each schedulable entity, or it can just run a set of entities on a cache and maintain the aggregate working set. The later incurs less cost at scheduling time.
Subcached pages complicate working set measurement. The LRU value of a page can change any time that some other page moves into the cache.
However, the LRU numbers do not consider whether or not a page is subcached. Instead, all the hardware mechanisms which use LRU consider all subcached paqes as one LRU level, and all non-subcached pages at various other LRU levels.

LRU Insert Table The LRU_insert_table maps from four logical points in the LRU~MRU sequence to the 32 actual slots in the set. The four slots are named:
1. WS_High - conventionally set close to or at MRU.
2. WS_Low - a point low in the working set of the cache. When software prefetches low priority data into the cache, it is usually inserted at this point. This allows software to 'over prefetch' without displacing more important data, as inserting it at WS_High would. See the description of prefetch strategy below.
3. BS_High - the boundary between working set and backing store. When software migrates a page into backing store in a cache it inserts it here.
4. BS_Low - an insertion point for low-priority backing store items.

1 Descriptor Allocation Action~
When a new descriptor in a set is needed, the cache proceeds through as many of the following actions needed to find a usable descriptor:
1. Looks for an invalid descriptor. If one exists, it uses it.
2. Drops copies. If ctl$configuration.cde is 1, the cache searches up from LRU, looking for any page which has only read-only subpages. If it finds one that is not held (descriptor.held is 0) and not subcached it invalidates it and uses it. The scan stops at BS_High.
3. Looks for an opportunity to do a recombine. If ctl$configuration.are is 1, the cache scans up from LRU looking for a page that has at least one owned subpage, has descriptor.held of zero, does not have descriptor.owner_limit of Cache_owner_limit, and is not subcached. The scan stops at BS_High.
If the scan finds one, the cache sends a Write REcombine Exclusive or Write Recombine Nonexclusive message as appropriate for each of its subpages which is owned. If all of the subpages are successfully passed off, then the descriptor is invalidated and used.
Software can disable this feature by setting Recombine_high_limit to MRU.
4. Drops pure pages. If ctl$configuration.ade is 1, the cache scans up from LRU looking for pages that are:
not modified have only esclusively owned or read-only subpages not atomic modified not held not subcached.
5. Looks for a pure page (which i8 subcached) to drop.

-73- 133~72 ~

1 6. Signals a no_descriptor_availabl~
exception if it cannot free a descriptor by the means described above.

Backqround Recombine The cache uses otherwise idle time to recombine pages. If Recombine_hiqh_limit is not 31, then the background task scans across the sets looking for pages in each set that can be recombined and recombines them.
Allocation recombines and automatic recombines will generally recombine pages as they leave the working set. There will be few recombinable pages in backing store. If at some time there are not recombinable pages in a cache, new recombinable pages will appear in the form of pages dropping out of the working set. If background and allocation recombines keep up with this rate, the only source of recombinable pages in the backing store will be references by other caches to pages in backing store. The referencing caches' descriptors will probably be in their working sets, and so recombining the pages to them is appropriate.

Software LRU Insertion Bias Software can bias LRU insertion in instructions. Some of the control instructions described below include an LRU_insert_indes field.
When one of these instructions moves the first subpage for a page into subcache, the LRU_insert_indes in the instruction replaces descriptor.LRU_insert_indes for that page. Then, when the page leaves æubcache, it is inserted into the LRU according to the specified entry in the ~ -74- 1333727 1 LRU_insert_table. The chng instruction and the various prefetch instructions ~described below) permit the programmer to specify an LRU_insert_indes. When a cache executes one of these instructions for a subpage of a page which has no valid subpages, the specified LRU_insert_indes becomes descriptor.LRU_insert_indes.
The LRU insert indes specified in control instruction replaces the indes previously stored in the descriptor. Once the indes is set in a cache, it persists in that cache until it is reset or all of the subpages become invalid. In effect, the memory system has a limited memory for LRU bias information. If one program indicates that a page is likely to be referenced again, and shortly thereafter another program indicates that it is unlikely to be referenced again, the second indication persists.
System software can establish a different default behavior. For example, system software might include a background task that changes descriptor.LRU_insert_indes to WS_High for pages below BS_High. This would implement a policy as follows: once a page had aged to backing store, any LRU insert indes information was too old to be valuable, and the ordinary default should apply instead.
Prefetching requires care in the use of LRU
insertion bias. It is desirable for software to be able to 'over prefetch,' to prefetch any data that it may need. To avoid driving higher priority information out of the LRU, the over-prefetched pages should be fetched with an LRU_insert_indes other than WS_High.

. -~75~ 1333727 1 Fiqure 9 depicts an exemplary domain routing unit 28F constructed according to a preferred practice of the invention. The unit 28F includes domain directory section 80 and remote fiber interface section 82 interconnected via cache bus 76. Directory section 80 includes dual routing control units 84A and 84B coupled to memory stores 86A and 868, as illustrated. The stores comprise 8 Mbyte dynamic random access memory elements arranged for storing lists of the descriptors identifying data maintained in the domain segments which descend from the upper level domain segment to which the illustrated routing unit 28F is attached. Routing control units 84A and 84B are constructed and operate similarly to the cache control units 74A, 74B, 74C
and 74D, described above. The units additionally include hash encoding logic for controlling storage and access of descriptors within stores 86A and 86B.
This encoding logic, as well as the descriptor storage and access mechanisms, are conventional in the art.
The remote fiber interface section 82 includes remote interface unit 88, coupled with fiber receiver and decoding section 90 and with fiber encoding and transmitting section 92, in the manner illustrated in Figure 9. The receiver 90 interfaces the incoming fiber optic line 94, while the transmitter 92 interfaces the outgoing line 96. In addition to buffering information signal transmissions, the unit 88 provides CRC encoding and decoding for the fiber optic link. Receiver 90 and transmitter 92 are constructed in accord with technigues conventional in the art.

133372~
1 While the illustrated domain routing unit 28F is specifically configured to interface remote domain segments (see, for example, segments 12F and 14B of Figure 1), it will be appreciated that direct interconnect units (i.e., those domain routing units which provide interconnection between non-remote segments, e.g., segments 14A and 12A of Figure 1) are similarly constructed. In such units, the remote fiber interface section 82 is replaced by a local interface section, which provides buffering for transmissions between respective domain segment buses.

SummarY
It is seen that the aforementioned objects are met by the invention, embodiments of which are described above, which provides a digital data processing system comprising a plurality of processing cells arranged in a hierarchy of rings, which selectively allocates storage and moves esclusive data copies from cell to cell in response to access requests generated by the cells, and which employs routing elements to selectively broadcaset data access requests, updates and transfers on the rings. A multiprocessing system constructed in accord with the invention features improved data coherency, reduced latency and bus contention, as well as unlimited scalability.
It will be appreciated that the embodiments depicted in the drawings and described above are illustrative only and that those skilled in the art may make changes in the illustrated constructions and sequences without departing from the scope of the invention. ~hus, for e~ample, that special purpose processing units capable of generating access _77_ 133~7~7 1 reguests may be substituted for the illustrated central processing units, that remote cells and domains may be coupled by media other than fiber optic lines, and so forth.
Accordingly, what we claim is:

Claims (139)

1. A digital data processing apparatus comprising A. (n) information transfer domains each including one or more segments, where (n) is equal to two, B. said plurality of information transfer domains including a first information transfer domain having a plurality of domain(0) segments, each including i) a plurality of processing cells, each processing cell including a central processing unit connected for information-representative signal transfer with anassociated content-addressable memory element for storing -information-representative signals, each said information-representative signal being identifiable by a corresponding SVA identifier, each said processing cell further including memory management means for accessing information-representative signals stored in that content-addressable memory element, ii) a bus element connected to those plural memory management means for transferring signals between the processing cells of that domain(0) segment, iii) the memory management means of at least a requesting one of said processing cells including means for generating an access-request signal including an identifier component representative of an SVA identifier of an information-representative signal stored in a memory element of any other of said processing cells, said memory management means further including means for transmitting that access-request signal on the bus element of the domain(0) segment with which the requesting processing cell is associated, C. said plurality of information transfer domains further including a second information transfer domain having a domain(1) segment comprising i) a bus element for transferring signals within that domain(1) segment, ii) plural domain routing elements for transferring signals between that domain(1) segment and a respective domain(0) segment, each such routing element being connected for information-representative signal transfer with the respective domain(0) segment bus element and with the domain(1) segment bus element, each said domain routing element including directory means for storing SVA identifier signals corresponding to information-representative signals stored in the plurality of memory elements contained in processing cells of the respective domain(0) segment, and each said domain routing element further including means for receiving an access-request signal transferred along any one of the bus element of the domain(1) segment and the domain(0) segment with which it is connected, for selectively transmitting a copy of that access-request signal along the bus element of the other of those segments based on a comparison of the identifier component of that access-request signal with the SVA identifier signals in said directory element.

2. A digital data processing apparatus comprising A. (n) information transfer domains, each respectively designated as informationtransfer domain(k), wherein (n) is an integer greater than or equal to two, and wherein (k) represents successive integers between (0) and (n-1), inclusive, B. information transfer domain(0) including a plurality of domain(0) segments, each such segment including i) a plurality of processing cells, each processing cell including a central processing unit connected for information-representative signal transfer with anassociated content-addressable memory element for storing information-representative signals, each said information-representative signal being identifiable by a corresponding SVA identifier, each said processing cell further including memory management means for accessing information-representative signals stored in that content-addressable memory element, ii) a bus element connected to those plural memory management means for transferring signals between the processing cells of that domain(0) segment, iii) the memory management means of at least a requesting one of said processing cells including means for generating an access-request signal including an identifier component representative of an SVA identifier of an information-representative signal stored in a memory element of any other of said processing cells, said memory management means further including means for transmitting that access-request signal on the bus element of the domain(0) segment with which the requesting processing cell is associated, C. each information transfer domain(k), wherein (k) represents successive integers between (1) and (n-1), inclusive, including one or more corresponding domain(k) segments, wherein the number of segments in information domain(k) is less than the number of segments in domain(k-1), for each value of (k), and wherein information transfer domain(n-1) includes only one such segment, each domain(k) segment including i) a bus element for transferring signals within that domain(k)segment, ii) plural domain routing elements for transferring signals between that domain(k) segment and a domain(k-1) segment, each such routing element being connected for information-representative signal transfer with the respective domain(k) segment bus element and with the respective domain(k-1) segment bus element, each said domain routing element including directory means for storing SVA identifier signals corresponding to information-representative signals stored in the plurality of memory elements contained in processing cells of domain(j) segmentsassociated with that domain(k) segment, where (j) is an integer between (k-l) and (0), and each said domain routing element further including means for receiving an access-request signal transferred along any one of the bus element of the domain(k) segment with which it is connected and the domain(k- 1) segment with which it isconnected, for selectively transmitting a copy of that access-request signal along the bus element of the other of those segments based on a comparison of the identifier component of that access-request signal with the SVA identifier signals in said directory element.

3. A digital data processing apparatus according to claim 2, wherein one or more said processing cells includes means for receiving an access-request signal transferred along an associated domain(0) bus for selectively generating a signal representative of the requested information-representative signal.

4. A digital data processing apparatus according to claim 3, wherein A. each said bus element comprises a unidirectional information-representative signal flow path, and B. said control means includes means for driving said access-request signal along the flow path defined by the associated bus element.

5. A digital data processing apparatus according to claim 4, wherein said domain routing element includes at least one of A. means for receiving an access-request signal transferred along a bus element associated with a domain(k-l) segment, where (k) is an integer between (1) and (n-1), and for selectively transmitting a copy of that signal along the bus element associated with a corresponding domain(k) segment, and B. means for receiving an access-request signal transferred along a bus element associated with a domain(k) segment, where (k) is an integer between (1) and (n-1), and for selectively transmitting a copy of that signal along the bus element associated with a corresponding domain(k-l) segment.

6. A digital data processing apparatus according to claim 5, wherein A. a domain routing element connected with a domain(k) segment, where (k) is an integer between (1) and (n-1), inclusive, includes directory means for storing SVA identifier signals corresponding to information-representative signals stored in the plurality of memory elements contained in processing cells of domain(j) segments associated with that domain(k) segment, where (j) is an integer between (k-1) and (0), and B. said domain routing element includes interface means coupled with said directory element and with said access request means for comparing an access-request signal with an SVA
identifier signal to determine whether a copy of that domain request signal should be transmitted to the associated domain(k) segment.

7. A digital data processing apparatus according to any one of claims 1-6, wherein A. at least a requesting one of said central processing units includes access request means for generating an access request signal representative of a request for access to an information-representative signal stored in any one of said memory elements, B. the memory management means associated with the requesting central processingunit includes control means responsive to an access-request signal directed to an information-representative signal not stored within the associated memory element for transmitting that signal on the associated domain(0) bus element.

8. A digital data processing apparatus according to claim 7, wherein A. said access request means includes means for generating an ownership-request signal representative of a request for priority access to an information-representative signal, and B. said memory management means includes means responsive to selected ones of said ownership-request signals for allocating, only within the memory element associated with the requesting central processing unit and exclusive of the memory elements associated with the other central processing units, physical storage space for the requested information-representative signal and for storing that signal therein.

9. A digital data processing apparatus according to claim 7, wherein said memorymanagement means comprise deallocation means responsive to selected ones of said ownership-request signal for deallocating physical storage space allocated in a memory element, other than the one associated with the requesting central processing unit, for storage of the requested information-representative signal.

10. A digital data processing apparatus according to claim 7, wherein at least one said memory element includes an associated directory means for storing an SVA identifier signal uniquely identifying at least selected information-representative signals stored in that memory element.

11. A digital data processing apparatus according to claim 10, wherein A. said access request means includes means for generating, along with said access request signal, an SVA request signal identifying the requested information-representative signal, B. said memory management means include interface means coupled with said associated directory means for comparing an SVA request signal with one or more SVA
identifier signals stored in that directory means for determining whether the requested information-representative signal is stored in the memory element associated with that directory means.

12. A digital data processing apparatus according to claim 10, wherein A. each said directory means includes one or more identifier storage locations for storing SVA identifier signals, B. said memory management means include means for storing in one of said associated identifier storage locations an SVA identifier signal associated with an information-representative signal for which physical storage space has been allocated within the associated memory element, and C. said memory management means include means for invalidating an associated SVA identifier signal corresponding to an information-representative signal for which physical storage space has been deallocated within the associated memory element.

13. A digital data processing apparatus according to claim 7, wherein said access request means includes means for generating a read-only request signal representative of a request for secondary access to an information- representative signal, and wherein said memory management means include means selectively responsive to a read-onlysignal generated by a requesting one of said central processing units, said read-only signal being representative of a request for secondary access to an information-representative signal stored in a memory element associated with another of said other central processing units, for transferring a copy of that information-representative signal to the memory element associated with the requesting central processing unit.

14. A digital data processing apparatus according to claim 7, wherein said central processing units includes means for selectively generating an update signal representative of modification of an information-representative signal, said memory management means include means responsive to an update signal generated by an updating one of said central processing units for modifying a corresponding information-representative signal stored in the memory element associated with that central processing unit.

15. A digital data processing apparatus according to claim 14, wherein said memory management means include means responsive to an update signal generated by said updating central processing unit, said update signal being representative of modification of a corresponding information-representative signal stored in a memory element associated with another said central processing unit, for modifying that corresponding information-representative signal.

16. A digital data processing apparatus according to claim 7, wherein A. said access request means includes atomic-ownership means for generating an atomic-request signal representative of a request for exclusive priority access to one or more information-representative signals, B. said memory management means include means selectively responsive to an atomic-request signal generated by a first one of said central processing units for i) allocating, exclusively, in the memory element associated with the first central processing unit physical storage space for said one or more requested information-representative signals and for storing those information-representative signals therein, while ii) preventing access to any of those information-representative signals in response to a first selected access-request signal generated by a second one of said central processing units.

17. A digital data processing apparatus according to claim 16, wherein said memory management means include means for responding to a second selected access request generated by said second central processing unit for effecting exclusive transfer of requested information-representative signals to the memory element associated with that central processing unit and for preventing access to any of those information request signals generated by the first or any other central process unit.

18. A digital data processing apparatus according to claim 16, wherein A. said access request means further includes atomic transaction termination means for generating a release signal representative of termination of said request for priority access to said one or more information-representative signals, and B. said memory management means include means responsive to said transaction-termination signal for re-enabling selective access to those information-representative signals in response to access request signals generated by any of said central processing units.

19. A digital data processing apparatus according to claim 7 wherein A. said plurality of processing cells includes at least a remote processing cellincluding an associated memory element, and B. remote interface means for transferring signals to and from the memory element associated with said remote processing cell.

20. A digital data processing apparatus according to claim 19, wherein said remote interface means includes fiber optic transmission media for carrying signals to and from said remote cell.

21. A digital data processing apparatus according to any one of claims 1-6, characterized in that at least one of said memory elements includes means for storing a data subpage that comprises one or more information-representative signals and that forms part of a data page, said data page comprising plural data subpages, said access request means includes means for generating an access-request signalrepresentative of a request for access to a data subpage stored in one or more of said memory elements, said memory management means includes means responsive to at least selected ones of said access-request signals for i) allocating, only within a memory element associated with the requesting central processing unit means, physical storage space for the data page associated with the requested data subpage, wherein that space is the exclusive physical storage space for the requested data subpage with respect to all of said memory elements, and for ii) storing the requested data subpage in that allocated physical storage space.

22. A digital data processing apparatus according to claim 21, wherein said memory management means includes deallocation means for selectively deallocating physical storage space allocated to selected data pages in one or more of said memory elements.

23. A digital data processing apparatus according to any of the claims 1-6, characterized in that A. at least one of said memory elements includes means for storing a data subpage that comprises one or more information-representative signals and that forms part of a data page, said data page comprising plural data subpages, said access request means includes means for generating an access-request signalrepresentative of a request for access to a data subpage stored in one or more of said memory elements, B. said memory management means includes means responsive to i) selected ones of said access-request signals for allocating, only within a memory element associated with the requesting central processing unit means, physical storage space for the data page associated with the requested data subpage, wherein that space is the exclusive physical storage space for the requested data subpage with respect to all of said memory elements, and for storing the requested data subpage in that allocated physical storage space, ii) selected other ones of said access-request signals for allocating, within a memory element associated with the requesting central processing unit means, physical storage space for the data page associated with the requested data subpage, wherein that space is not exclusive the physical storage space for the requestedinformation-representative signal with respect to all of said memory elements, and for storing the requested data subpage in that allocated physical storage space, C. said memory management means further includes deallocation means for selecting for deallocation a data page for which physical storage space is allocated in at least a first memory element and a second memory element.

24. A digital data processing apparatus according to claim 23, wherein said memory management means includes recombination means for deallocating physical storage space allocated to said selected data page in said first memory element and for transferring, from said first memory element to said second memory element for storage therein, one or more selected subpages of said selected data page in connection with such deallocation.

25. A digital data processing apparatus according to claim 23, wherein said memory management means includes directory means associated with one or more of said memory elements for storing one or more descriptor signals, each identifying a corresponding data page for which physical storage space is allocated within the associated memory element, each said descriptor signal including i) a tag component signal identifying the corresponding data page, ii) at least one field component signal representative of an attribute of one ormore of the subpages which form the corresponding data page.

26. A digital data processing apparatus according to claim 25, wherein said recombination means includes means for transferring one or more of said field component signals from a directory means associated with the first memory element to a directory means associated with the second memory element in conjunction with the transfer of at least selected data subpages therebetween.

27. A digital data processing apparatus according to any one of claims 1-6, characterized in that A. at least one of said memory elements includes means for storing a data subpage that comprises one or more information-representative signals and that forms part of a data page, said data page comprising plural data subpages, said access request means includes means for generating an access-request signalrepresentative of a request for access to a data subpage stored in one or more of said memory elements, B. said memory management means includes means responsive to i) selected ones of said access-request signals for allocating, only within a memory element associated with the requesting central processing unit means, physical storage space for the data page associated with the requested data subpage, wherein that space is the exclusive physical storage space for the requested data subpage with respect to all of said memory elements, and for storing the requested data subpage in that allocated physical storage space, ii) selected other ones of said access-request signals for allocating, within a memory element associated with the requesting central processing unit means, physical storage space for the data page associated with the requested data subpage, wherein that space is not exclusive the physical storage space for the requested data subpage with respect to all of said memory elements, and for storing the requested data subpage in that allocated physical storage space, C. said memory management means further includes deallocation means for selectively deallocating physical storage space allocated to a data page based on a history of access of an information-representative signal in that page by said central processing unit means.

28. A digital data processing apparatus according to claim 27, wherein said deallocation means includes LRU table means for storing one or more access history-representative signals representative of a history of access of respective data pages, or portions thereof, by said central processing unit means.

29. A digital data processing apparatus according to claim 28, comprising A. subcache means, coupled to said central processing unit means and to the associated memory element, for storing one or more information-representative signals of a data subpage in use by that central processing unit means, B. said subcache means including means for transferring information-representative signals to and/or from that subcache means and the associated memory element, and C. said LRU table means includes means coupled to said subcache means for responding to a transfer of one or more information-representative signals of a first data page between that subcache means and its associated memory element for generating an access history-representative signal having a first selected value.

30. A digital data processing apparatus according to claim 29, where said LRU table means includes means for increasing an age-representative value of the access history-representative signal associated with the first data page in response to the transfer of one or more information-representative signals of a second data page between said subcache means and its associated memory element.

31. A digital data processing apparatus according to claim 30, wherein said deallocation means includes means for identifying as a candidate for deallocation a data page having an access history-representative signal greater than a selected value.

32. A digital data processing apparatus according to any one of claims 1-6, characterized in that A. at least one of said memory elements includes means for storing a data subpage that comprises one or more information-representative signals and that forms part of a data page, said data page comprising plural data subpages, said access request means includes means for generating an access-request signalrepresentative of a request for access to a data subpage stored in one or more of said memory elements, B. said memory management means includes means responsive to i) selected ones of said access-request signals for allocating, only within a memory element associated with the requesting central processing unit means, physical storage space for the data page associated with the requested data subpage, wherein that space is the exclusive physical storage space for the requested data subpage with respect to all of said memory elements, and for storing the requested data subpage in that allocated physical storage space, ii) selected other ones of said access-request signals for allocating, within a memory element associated with the requesting central processing unit means, physical storage space for the data page associated with the requested data subpage, wherein that space is not exclusive the physical storage space for the requestedinformation-representative signal with respect to all of said memory elements, and for storing the requested data subpage in that allocated physical storage space, C. said memory management means includes state-defining means coupled with said plural memory elements for associating an access state with the subpages stored therein, and D. said memory management means further includes deallocation means for selectively deallocating physical storage space allocated to a data page based on an access state of one or more subpages thereof.

33. A digital data processing apparatus according to claim 32, wherein A. said state-defining means includes means for associating an invalid state with one or more invalid data subpages, and wherein B. said deallocation means includes means for deallocating physical storage space allocated to a data page for which all associated data subpages are in said invalid state.

34. A digital data processing apparatus according to claim 32, wherein A. said state-defining means includes means for associating a modified state with a data subpage in which one or more information-representative signals have been modified, and B. said deallocation means includes means for deallocating physical storage space allocated to at least a selected data page in which none of the data subpages are associated with said modified state.

35. A digital data processing apparatus according to claim 32, wherein said deallocation means includes means for deallocating physical storage space allocated to a data page in which none of the data subpages are associated with said modified state and in which all of the data subpages are associated with said exclusive owner state, thereby, removing a last copy of that data page from the memory elements of said processing cell.

36. A digital data processing apparatus according to claim 32, wherein said deallocation means includes means for deallocating physical storage space allocated to a data page in which none of the data subpages are associated with said modified state and in which all of the data subpages are associated with said read-only state.

37. A digital data processing apparatus according to claim 32, wherein A. said state-defining means includes means for associating a read-only state with a copy of a data subpage subject to read-only access in a memory element in which physical storage space for that copy is allocated, B. said deallocation means includes means for deallocating physical storage space allocated to a data page for which all associated data subpages are in said read-only state.

38. A digital data processing apparatus according to any one of claims 1-6, characterized in that , 92 A. at least one of said memory elements includes means for storing a data subpage that comprises one or more information-representative signals and that forms part of a data page, said data page comprising plural data subpages, said access request means includes means for generating an access-request signalrepresentative of a request for access to a data subpage stored in one or more of said memory elements, B. said memory management means includes means responsive to selected ones of said access-request signals for allocating, only within a memory element associated with the requesting central processing unit means, physical storage space for the data page associated with the requested data subpage, wherein that space is the exclusive physical storage space for the requested data subpage with respect to all of said memory elements, and for storing the requested data subpage in that allocated physical storage space, C. said memory management means further includes backing store means for transferring information-representative signals forming a selected data page to a secondary storage device.

39. A digital data processing apparatus according to claim 38, comprising A. directory means associated with one or more of said memory elements for storing one or more descriptor signals, each identifying a corresponding data page for which physical storage space is allocated therein, each said descriptor signal including at least one field component signal representative of a status of the corresponding data page, and B. said backing store means includes means for transferring to the secondary storage device, substantially concurrently with the transfer of information-representative signals forming a selected data page, one or more field component signals of the descriptor signal corresponding to that selected data page.

40. A digital data processing apparatus according to claim 39, wherein A. said memory management means including state-defining means coupled with said plural memory elements for associating an access state with one or more information-representative signals stored therein, said access state including an atomic owner access state associable with an data subpage modifiable by a central processing unit means associated with a memory element in which that data subpage is stored, no copy of which data subpage is stored in a memory element associated with another said central processing unit means, neither that information-representative signal, nor a copy thereof, being selectively accessible for transfer to a memory element associated with another said central processing unit means, B. said descriptor signal includes at least one field component signal representative of an atomic-modified state associable with one or more data subpages of the corresponding data page which subpage undergoes a transition into or out of atomic state, C. said backing store means includes means for transferring to the secondary storage device, substantially concurrently with the transfer of information-representative signals forming a selected data page, said atomic-modified state-representative field component signal corresponding to that selected data page.

41. A digital data processing apparatus according to any of claims 1-6, characterized in that said memory management means includes processing means for responding to an access-request signal for accessing the requested information-representative signal asynchronously with respect to the execution of instructions by said requesting central processing unit means.

42. A digital data processing apparatus according to any one of claims 1-6, characterized in that A. said memory management means include state-defining means coupled with said plural memory elements for associating an access state with one or more information-representative signals stored therein, said access state being selected from a group of access states including one or more of i) a read-only access state associable with a copy of an information-representative signal subject to read-only access by a central processing unit associated with a memory element in which that copy is stored, wherein said information-representative signal is stored in a memory element associated with another of said central processing units and is modifiable by that other central processing unit, ii) a nonexclusive owner access state associable with an information-representative signal modifiable by a central processing unit associated with a memory element in which that information-representative signal is stored, a copy of which information-representative signal is stored in a memory element associated with another said central processing unit, iii) an exclusive owner access state associable with an information-representative signal modifiable by a central, processing unit associated with a memory element in which that information-representative signal is stored, no copy of which information-representative signal is stored in a memory element associated with another said central processing unit, that information-representative signal, or a copy thereof, being accessible for transfer to a memory element associated with another said central processing unit, and iv) an atomic owner access state associable with an information-representative signal modifiable by a central processing unit associated with a memory element in which that information-representative signal is stored, no copy of which information-representative signal is stored in a memory element associated with another said central processing unit, neither that information-representative signal, nor a copy thereof, being selectively accessible for transfer to a memory element associated with another said central processing unit.

43. A digital data processing apparatus according to claim 42, the further improvement wherein said state-defining means includes A. means for selectively and exclusively associating any one of i) said atomic owner access state, and ii) said exclusive owner access state with an information-representative signal stored in said plural memory elements, and B. means for selectively and exclusively associating said nonexclusive owner access state with one of (n) copies of an information-representative signal stored in said plural memory elements, where (n) is an integer greater than or equal to one.

44. A digital data processing apparatus according to claim 42, the further improvement wherein said state-defining means includes means for selectively associating any one of i) said read-only access state, and ii) said invalid access state with (n-1) copies of an information-representativesignal stored in said plural memory elements.

45. A digital data processing apparatus according to claim 42, the further improvement wherein said memory management means include means responsive to association of said atomic access state with an information-representative signal stored in a memory element associated with a first central processing unit for preventing access to that information-representative signal in response to a first selected access request signal generated by any other said central processing unit.

46. A digital data processing apparatus according to claim 45, wherein A. said memory management means include means for responding to a second selected access request signal generated by a second central processing unit, and directed to one or more information-representative signals associated with the atomic owner access state, for effecting transfer of those requested signals to the memory element associated with said second central processing unit, and B. said state-defining means includes means for associating the atomic owner state with those transferred signals for allocating, exclusively, in the memory element associated with the second central processing unit physical storage space for said one or more requested information-representative signals.

47. A digital data processing apparatus according to claim 42, wherein A. said state-defining means includes means responsive to an access request signal generated by a requesting central processing unit and directed to an information-representative signal stored in a memory element associated with an owning central processing unit, said information-representative signal being associated with said atomic access state, for associating with that information-representative signal a transient atomic state, B. said owning central processing unit includes means for generating a release signal representative of a release of said requested information-representative signal from said atomic access state, C. said memory management means include means responsive to a release signal generated by said owning central processing unit and directed to said requested information-representative signal for transmitting a copy of that information-representative signal to the memory element associated with the requesting central processing unit.

48. A digital data processing apparatus according to claim 42, the further improvement wherein A. said access request means includes means for generating an exclusive access request signal representative of a request for exclusive access to an information-representative signal, and B. said state-defining means includes means responsive to an exclusive access request signal generated by said requesting central processing unit, said exclusive access request being representative of a request for exclusive access to an information-representative signal stored in a memory element associated with another of said central processing units, wherein that information- representative signal is associated with said read-only access state, for effecting exclusive transfer of that information-representative signal to said requesting central processing unit and for associating the copy of that information-representative signal stored in the memory element associated with that other central processing unit with said invalid access state.

49. A digital data processing apparatus according to claim 42, the further improvement wherein A. said access request means includes means for generating a nonexclusive access-request signal representative of a request for nonexclusive access to an information-representative signal, and B. said state-defining means includes means responsive to a nonexclusive access request signal generated by said requesting central processing unit, said nonexclusive access request signal being representative of a request for nonexclusive access to an information-representative signal stored in a memory element associated with another of said central processing units, wherein that information-representative signal is associated with any one of an exclusive access state and a nonexclusive access state, for effecting exclusive transfer of that information-representative signal to said requesting central processing unit and for associating the information-representative signal stored in the memory element associated with that other central processing unit with said read-only access state.

50. A digital data processing apparatus according to claim 42, the further improvement wherein A. at least a requesting one of said central processing units includes stop request means for generating a stop request signal representative of a pending request for atomic owner access to an information-representative signal, B. said memory management means include means responsive to said stop request signal for effecting exclusive storage of a next available copy of the requested information-representative signal in the memory element associated with a requesting central processing unit, and C. said state-defining means includes means responsive to said stop request signal for assigning said atomic owner access state to said next available copy of the requested information-representative signal stored in the memory element associated with said requesting central processing unit.

51. A digital data processing apparatus according to claim 42, wherein said memory management means include means responsive to a request for priority access to an information-representative signal generated by a first central processing unit for responding to subsequent requests for access to that same information-representative generated by others of said central processing units for generating a transient signal for transmission to said other central processing units, said transient signal being representative of current ownership of said requested information-representative signal by said first central processing unit.

52. A digital data apparatus comprising A. (n) information-representative signal transfer levels, each respectively designated level(k), wherein (n) is an integer greater than or equal to one, and wherein (k) represents successive integers between (0) and (n-1), inclusive, B. each information-representative signal transfer level including a plurality of segments, each comprising bus means for transferring information-representative signals, where the number of segments in each information-representative signal transfer level, except information-representative signal transfer level(0), is less than the number of segments in information-representative signal transfer level(k-1), and where information-representative signal transfer level(n-1) includes only one such segment, C. each segment of information transfer level(0) including one or more processing cells, each said processing cell i) having zero, one or more data, or copies thereof, allocated thereto, each datum or copy thereof corresponding to a unique descriptor by which that datum or copy thereof is referenced, ii) including control means for generating an information-representative signal representative of at least one of a request for access to a datum and a response to a request for access to a datum, said information-representative signal including a descriptor of a datum subject to reference, iii) including routing means coupled to said control means and to the bus means of the associated level(0) segment for selectively transferring information-representative signals therebetween, iv) being referred to as a "first processing group" with respect to that routingmeans, wherein the other processing cells are referred to as a "second processing group"
with respect to that routing means, D. each level(k) segment, for (k) between (1) and (n-1), inclusive, including plural routing means for selectively transferring information-representative signals between that level(k) segment and an associated level(k-l) segment, where each such associated level(k-l) segment, as well as each descendant thereof, if any, is referred to as a descendant of that level(k) segment routing means, where the processing cells associated with descendants of each level(k) segment routing means ate referred to as a "first processing group" with respect to that routing means, and wherein the processing cells other than those associated with descendants of that routing means are referred to as a "second processing group," and E. at least one such routing means includes means for routing an information-representative signal received from a respective one of said first and second processing groups to the respective other of those groups based upon correspondence between the descriptor in that information-representative signal and a datum allocated to, or requested for allocation by, the first processing group.

53. A digital data processing apparatus comprising A. (n) information-representative signal transfer levels, each respectively designated as level(k), wherein (n) is an integer greater than or equal to two, and wherein (k) represents successive integers between (0) and (n-1), inclusive, B. information-representative signal transfer level(0) including a plurality of level(0) segments, each such segment including a plurality of processing cells interconnected by bus means for transferring information-representative signals therebetween, each processing cell including memory means for storing data, each datum being identifiable by a corresponding descriptor, C. at least one of said processing cells further including processing means for at least generating a request for access to a selected datum, D. at least one of said processing cells further including i) control means responsive to a request, received from any of a corresponding processing means and from any other processing cell by way of said associated level(0) segment bus, for selectively accessing said associated memory means to generate a signal representative of the requested datum, and selectively generating an information-representative signal representative of at least one of a request for access to a datum and a response to a request for access to a datum, said information-representative signal including a descriptor of a datum subject to reference, ii) routing means coupled to said control means and to the bus means of the associated level(0) segment for selectively transferring information-representative signals therebetween, iii) being referred to as a "first processing group" with respect to that routing means, wherein the other processing cells are referred to as a "second processing group" with respect to that routing means, D. each information transfer level(k), wherein (k) represents successive integers between (1) and (n-1), inclusive, including one or more corresponding level(k) segments, wherein the number of segments in information level(k) is less than the number of segments in level(k-1), for each value of (k), and wherein information transfer level(n-1) includes only one such segment, each level(k) segment including i) bus means for transferring signals within that level(k) segment, ii) plural level routing means for selectively routing transferring information-representative signals between that level(k) segment bus means and an associated level(k-1) segment bus means, where each such associated level(k-1) segment, as well as each descendant thereof, if any, is referred to as a descendant of that level(k) segment routing means, and where the processing cells associated with descendants of each level(k) segment routing means ate referred to as a "first processing group" with respect to that routing means, and wherein the processing cells other than those associated with descendants of that routing means are referred to as a "second processing group," and E. at least one such routing means includes means for routing an information-representative signal received from a respective one of said first and second processing groups to the respective other of those groups based on a correspondence between an information-representative signal identified in that information-representative signal and a datum requested by, or stored in a memory means of a processing cell of, the respective first processing group..

54. A routing element for digital information-representative signals between a first processing group and a second processing group, each said processing group having one or more processing cells, each processing cell i) having allocated thereto zero, one or more datum or copies thereof, each datum or copy thereof corresponding to a unique descriptor by which that datum or copy thereof is referenced, ii) including means for at least one of generating and receiving an information-representative signal including a descriptor of a datum subject to reference, said routing element comprising routing means for selectively transferring an information-representative signal received from one of said first and second processing groups to the other of those groups based upon correspondence between the descriptor in that information-representative signal and data allocated to said first processing group.

55. A digital data apparatus comprising A. first and second processing groups, each said group including one or more processing cells, each processing cell having allocated thereto zero, one or more datum or copies thereof, each datum or copy thereof corresponding to a unique descriptor by which that datum or copy thereof is referenced, B each processing cell including means for at least one of generating and receiving an information-representative signal including a descriptor of a datum subject to reference, C. routing means coupled to said first and second processing groups for selectively routing an information-representative signal received from one of said processing groups to the other of those processing groups based upon correspondence between the descriptor in that information-representative signal and data allocated to, or requested for allocation by, said first processing group.

56. A digital data apparatus comprising A. first and second processing groups, each said group including one or more processing cells, each processing cell having allocated thereto zero, one or more datum or copies thereof, each datum or copy thereof corresponding to a unique descriptor by which that datum or copy thereof is referenced, B. each processing cell including means for at least one of generating and receiving an information-representative signal including a descriptor of a datum subject to reference, C. routing means coupled to said first and second processing groups for selectively routing an information-representative signal received from one of said processing groups to the other of those processing groups based upon prior routing of the datum referenced in that information-representative signal, or requests therefor, between said first and second processing groups.

57. A digital data apparatus according to claim 55, wherein said second processing group comprises A. a plurality of further processing groups, each including a plurality of processing cells, B. a plurality of further routing means, each associated with a corresponding one of said further processing groups and coupled to the bus means thereof, for selectively transferring information-representative signals therewith, and C. means for transmitting said information-representative signals between said plural routing means.

58. An apparatus according to any one of claims 52 - 57, wherein each said descriptor has a value that is independent of a processing cell in which the corresponding datum is allocated and that is independent of the allocation of that corresponding datum with respect to other data, if any, allocated to that processing cell.

59. An apparatus according to any one of claims 52 - 57, wherein said routing means includes means for selectively passing an information-representative signal received from a respective one of said processing groups on within that same processing group for continued handling thereby.

60. An apparatus according to claim 59, wherein said routing means includes directory means for storing signals representative of at least one of i) data allocated to, or requested for allocation by, said first processing group, and ii) prior routings of said data allocated to, or requested for allocation by, said first processing group.

61. An apparatus according to claim 60, wherein said routing means includes means coupled to said directory means for comparing a descriptor in an information-representative signal received from a processing group with said directory signal to determine whether to route that information-representative signal to the other of said processing groups.

62. An apparatus according to claim 61, wherein A. at least one of said first and second processing groups is disposed physically remotely from the other, and B. said routing means includes remote interface means for selectively transferring an information-representative signals between said remotely disposed processing groups.

63. An apparatus according to claim 62, wherein said remote interface means includes fiber optic transmission media for carrying signals representative of said information-representative signals between said remotely disposed processing groups.

64. An apparatus according to claim 61, wherein said directory means includes means for storing allocation state-defining information for at least selected data, or copies thereof, allocated to said first processing group, said allocation state-defining information including at least one of i) an invalid allocation state for an invalid datum allocated to said first processing group, ii) a read-only allocation state for a COPY of a datum allocated to and subject to read-only access by a processing cell of said first processing group, no copy of which datum is modifiable by a processing cell of said first processing group, iii) a nonexclusive owner allocation state for a datum allocated to and modifiable by a processing cell of said first processing group, one or more read-only copies of which datum are allocated to other processing cells of said first and second processing groups, and iv) an exclusive owner allocation state for a datum exclusively allocated to and modifiable by a processing cell of said first processing group, no copies of which datum are allocated to other processing cells of said first and second processing groups.

65. An apparatus according to claim 61, wherein said directory means includes means for storing pending state-defining information for at least selected data for which requests are pending to at least one of said processing groups.

66. An apparatus according to claim 65, wherein said directory means includes means for storing, as said pending state-defining information, at least an ownership pending state for a datum for which an ownership allocation request is pending.

67. An apparatus according to claim 66, wherein said directory means includes means for storing, as said pending state-defining information, at least one of i) a pending atomic state for a datum for which a request for exclusive allocation is pending from the first processing group to the second processing group, and ii) a transient atomic state for a datum for which a request for exclusive allocation is pending from the second processing group to the first processing group.

68. An apparatus according to claim 61, wherein each of at least selected ones of said processing cells includes A. memory means for storing data allocated to that processing cell, and B. CPU means, coupled to that memory means associated with that processing cell,for at least processing data in that memory means.

69. An apparatus according to claim 68, wherein A. the CPU means of at least a requesting one of said processing cells includes means for generating at least an ownership request-signal representative of a request for ownership access to a datum, and B. at least that requesting processing cell includes routing means selectively responsive to that ownership request-signal for generating an information-representative signal representative of said request for ownership access, and for transferring that information-representative signal to another said processing cell.

70. An apparatus according to claim 69, wherein said other processing cell includes response means selectively for generating an information-representative signal representative of a response to said ownership request, said response information-representative signal including the datum for which ownership access was requested, and means for transferring that response information-representative signal to said requesting processing cell.

71. A digital data apparatus according to claim 56, wherein said second processing group comprises A. a plurality of further processing groups, each including a plurality of processing cells, B. a plurality of further routing means, each associated with a corresponding one of said further processing groups and coupled to the bus means thereof, for selectively transferring information-representative signals therewith, and C. means for transmitting said information-representative signals between said plural routing means.

72. A digital data processing apparatus comprising A. plural processing cells, each including a central processing unit coupled to an associated memory element, B. memory management means coupled to said plural memory elements for accessing one or more of said information-representative signals stored in said plural memory elements, C. at least a requesting one of said central processing units including access request means for generating an access request signal representative of a request for access to an information-representative signal, said access request means including means for generating an ownership-request signal representative of a request for priority access to an information-representative signal, at least the memory element associated with the requesting central processing unit including control means for selectively transmitting said access-request signal to said memory management element, and D. said memory management means including memory coherence means responsive to selected ones of said ownership-request signals for allocating, only within the memory element associated with the requesting central processing unit and exclusive of the memory elements associated with the other central processing units, physical storage space for the requested information-representative signal and for storing that signal therein.

73. A digital data processing apparatus according to claim 72, wherein said memory management means comprises deallocation means responsive to selected ones of said ownership-request signal for deallocating physical storage space allocated in a memory element, other than the one associated with the requesting central processing unit, for storage of the requested information-representative signal, said deallocation being effected substantially concurrently with the allocation of physical storage space for the requested information-representative signal in the memory element associated with the requesting central processing unit.

74. A digital data processing appartus according to claim 73, wherein at least one said memory element includes an associated directory means for storing an SVA identifier signal uniquely identifying at least selected information-representative signals stored in that memory element.

75. A digital data processing apparatus according to claim 74, wherein A. said access request means includes means for generating, along with said access request signal, an SVA request signal identifying the requested information-representative signal, B. said memory management means includes interface means coupled with said directory means for comparing an SVA request signal with one or more SVA identifier signals stored in that directory means for determining whether the requested information-representative signal is stored in the memory element associated with that directory means.

76. A digital data processing apparatus according to claim 74, wherein A. each said directory means includes one or more identifier storage locations for storing SVA identifier signals, B. said memory management element includes means for storing in one of said identifier storage locations an SVA identifier signal associated with an information-representative signal for which physical storage space has been allocated within the associated memory element, and C. said memory management element includes means for invalidating an SVA identifier signal corresponding to an information-representative signal for which physical storage space has been deallocated within the associated memory element.

77. A digital data processing apparatus according to claim 73, wherein said access request means includes means for generating a read-only request signal representative of a request for secondary access to an information-representative signal, and wherein said memory management means includes means selectively responsive to a read-only signal generated by a requesting one of said central processing units, said read-only signal being representative of a request for secondary access to an information-representative signal stored in a memory element associated with another of said other central processing units, for transferring a copy of that information-representative signal to the memory element associated with the requesting central processing unit.

78. A digital data processing apparatus according to claim 73, wherein said central processing units includes means for selectively generating an update signal representative of modification of an information-representative signal, said memory management means includes means responsive to an update signal generated by an updating one of said central processing units for modifying a corresponding information-representative signal stored in the memory element associated with that central processing unit.

79. A digital data processing apparatus according to claim 78, wherein said memory management means includes means responsive to an update signal generated by said updating central processing unit, said update signal being representative of modification of a corresponding information-representative signal stored in a memory element associated with another said central processing unit, for modifying that corresponding information-representative signal.

80. A digital data processing apparatus according to claim 73, wherein A. said access request means includes atomic-ownership means for generating a atomic-request signal representative of a request for exclusive priority access to one or more information-representative signals, B. said memory coherence means includes means selectively responsive to an atomic-request signal generated by a first one of said central processing units for i) allocating, exclusively, in the memory element associated with the first central processing unit physical storage space for said one or more requested information-representative signals and for storing those information-representative signals therein, while ii) preventing access to any of those information-representative signals in response to a first selected access request signal generated by a second one of said central processing units.

81. A digital data processing apparatus according to claim 80, wherein said memory coherence means includes means for responding to a second selected access request generated by said second central processing unit for effecting exclusive transfer of requested information-representative signals to the memory element associated with that central processing unit and for preventing access to any of those information request signals generated by the first or any other central process unit.

82. A digital data processing apparatus according to claim 80, wherein A. said access request means further includes atomic-transaction termination means for generating a release signal representative of termination of said request for priority access to said one or more information-representative signals, and B. said memory coherence means includes means responsive to said transaction-termination signal for re-enabling selective access to those information-representative signals in response to access request signals generated by any of said central processing units.

83. A digital data processing apparatus according to claim 73, wherein A. said plurality of processing cells includes at least a remote processing cell including an associated memory element, and B. remote interface means for transferring information-representative signals to and from the memory element associated with said remote processing cell.

84. A digital data processing apparatus according to claim 83, wherein said remote interface means includes fiber optic transmission media for carrying information-representative signals to and from said remote cell.

85. A digital data processing apparatus according to any one of claims 72-84, characterized in that at least one of said memory elements includes means for storing a data subpage that comprises one or more information-representative signals and that forms part of a data page, said data page comprising plural data subpages, said access request means includes means for generating an access-request signalrepresentative of a request for access to a data subpage stored in one or more of said memory elements, said memory management means includes means responsive to at least selected ones of said access-request signals for i) allocating, only within a memory element associated with the requesting central processing unit means, physical storage space for the data page associated with the requested data subpage, wherein that space is the exclusive physical storage space for the requested data subpage with respect to all of said memory elements, and for ii) storing the requested data subpage in that allocated physical storage space.

86. A digital data processing apparatus according to claim 85, wherein said memory management means includes deallocation means for selectively deallocating physical storage space allocated to selected data pages in one or more of said memory elements.

87. A digital data processing apparatus according to any of the claims 72-84, characterized in that A. at least one of said memory elements includes means for storing a data subpage that comprises one or more information-representative signals and that forms part of a data page, said data page comprising plural data subpages, said access request means includes means for generating an access-request signalrepresentative of a request for access to a data subpage stored in one or more of said memory elements, B. said memory management means includes means responsive to i) selected ones of said access-request signals for allocating, only within a memory element associated with the requesting central processing unit means, physical storage space for the data page associated with the requested data subpage, wherein that space is the exclusive physical storage space for the requested data subpage with respect to all of said memory elements, and for storing the requested data subpage in that allocated physical storage space, ii) selected other ones of said access-request signals for allocating, within a memory element associated with the requesting central processing unit means, physical storage space for the data page associated with the requested data subpage, wherein that space is not exclusive the physical storage space for the requestedinformation-representative signal with respect to all of said memory elements, and for storing the requested data subpage in that allocated physical storage space, C. said memory management means further includes deallocation means for selecting for deallocation a data page for which physical storage space is allocated in at least a first memory element and a second memory element.

88. A digital data processing apparatus according to claim 87, wherein said memory management means includes recombination means for deallocating physical storage space allocated to said selected data page in said first memory element and for transferring, from said first memory element to said second memory element for storage therein, one or more selected subpages of said selected data page in connection with such deallocation.

:`:

89. A digital data processing apparatus according to claim 87, wherein said memory management means includes directory means associated with one or more of said memory elements for storing one or more descriptor signals, each identifying a corresponding data page for which physical storage space is allocated within the associated memory element, each said descriptor signal including i) a tag component signal identifying the corresponding data page, ii) at least one field component signal representative of an attribute of one ormore of the subpages which form the corresponding data page.

90. A digital data processing apparatus according to claim 89, wherein said recombination means includes means for transferring one or more of said field component signals from a directory means associated with the first memory element to a directory means associated with the second memory element in conjunction with the transfer of at least selected data subpages therebetween.

91. A digital data processing apparatus according to any one of claims 72 - 84, characterized in that A. at least one of said memory elements includes means for storing a data subpage that comprises one or more information-representative signals and that forms part of a data page, said data page comprising plural data subpages, said access request means includes means for generating an access-request signalrepresentative of a request for access to a data subpage stored in one or more of said memory elements, B. said memory management means includes means responsive to i) selected ones of said access-request signals for allocating, only within a memory element associated with the requesting central processing unit means, physical storage space for the data page associated with the requested data subpage, wherein that space is the exclusive physical storage space for the requested data subpage with respect to all of said memory elements, and for storing the requested data subpage in that allocated physical storage space, ii) selected other ones of said access-request signals for allocating, within a memory element associated with the requesting central processing unit means, physical storage space for the data page associated with the requested data subpage, wherein that space is not exclusive the physical storage space for the requested data subpage with respect to all of said memory elements, and for storing the requested data subpage in that allocated physical storage space, C. said memory management means further includes deallocation means for selectively deallocating physical storage space allocated to a data page based on a history of access of an information-representative signal in that page by said central processing unit means.

92. A digital data processing apparatus according to claim 91, wherein said deallocation means includes LRU table means for storing one or more access history-representative signals representative of a history of access of respective data pages, or portions thereof, by said central processing unit means.

93. A digital data processing apparatus according to claim 92, comprising A. subcache means, coupled to said central processing unit means and to the associated memory element, for storing one or more information-representative signals of a data subpage in use by that central processing unit means, B. said subcache means including means for transferring information-representative signals to and/or from that subcache means and the associated memory element, and C. said LRU table means includes means coupled to said subcache means for responding to a transfer of one or more information-representative signals of a first data page between that subcache means and its associated memory element for generating an access history-representative signal having a first selected value.

94. A digital data processing apparatus according to claim 93, where said LRU table means includes means for increasing an age-representative value of the access history-representative signal associated with the first data page in response to the transfer of one or more information-representative signals of a second data page between said subcache means and its associated memory element.

95. A digital data processing apparatus according to claim 94, wherein said deallocation means includes means for identifying as a candidate for deallocation a data page having an access history-representative signal greater than a selected value.

96. A digital data processing apparatus according to any one of claims 72-84, characterized in that A. at least one of said memory elements includes means for storing a data subpage that comprises one or more information-representative signals and that forms part of a data page, said data page comprising plural data subpages, said access request means includes means for generating an access-request signalrepresentative of a request for access to a data subpage stored in one or more of said memory elements, B. said memory management means includes means responsive to i) selected ones of said access-request signals for allocating, only within a memory element associated with the requesting central processing unit means, physical storage space for the data page associated with the requested data subpage, wherein that space is the exclusive physical storage space for the requested data subpage with respect to all of said memory elements, and for storing the requested data subpage in that allocated physical storage space, ii) selected other ones of said access-request signals for allocating, within a memory element associated with the requesting central processing unit means, physical storage space for the data page associated with the requested data subpage, wherein that space is not exclusive the physical storage space for the requested data subpage with respect to all of said memory elements, and for storing the requested data subpage in that allocated physical storage space, C. said memory management means includes state-defining means coupled with said plural memory elements for associating an access state with the subpages stored therein, and D. said memory management means further includes deallocation means for selectively deallocating physical storage space allocated to a data page based on an access state of one or more subpages thereof.

97. A digital data processing apparatus according to claim 96, wherein A. said state-defining means includes means for associating an invalid state with one or more invalid data subpages, and wherein B. said deallocation means includes means for deallocating physical storage space allocated to a data page for which all associated data subpages are in said invalid state.

98. A digital data processing apparatus according to claim 96, wherein A. said state-defining means includes means for associating a modified state with a data subpage in which one or more information-representative signals have been modified, and B. said deallocation means includes means for deallocating physical storage space allocated to at least a selected data page in which none of the data subpages are associated with said modified state.

99. A digital data processing apparatus according to claim 96, wherein said deallocation means includes means for deallocating physical storage space allocated to a data page in which none of the data subpages are associated with said modified state and in which all of the data subpages are associated with said exclusive owner state, thereby, removing a last copy of that data page from the memory elements of said processing cells.

100. A digital data processing apparatus according to claim 96, wherein said deallocation means includes means for deallocating physical storage space allocated to a data page in which none of the data subpages are associated with said modified state and in which all of the data subpages are associated with said read-only state.

101. A digital data processing apparatus according to claim 96, wherein A. said state-defining means includes means for associating a read-only state with a copy of a data subpage subject to read-only access in a memory element in which physical storage space for that copy is allocated, B. said deallocation means includes means for deallocating physical storage space allocated to a data page for which all associated data subpages are in said read-only state.

102. A digital data processing apparatus according to any one of claims 72-84, characterized in that A. at least one of said memory elements includes means for storing a data subpage that comprises one or more information-representative signals and that forms part of a data page, said data page comprising plural data subpages, said access request means includes means for generating an access-request signalrepresentative of a request for access to a data subpage stored in one or more of said memory elements, B. said memory management means includes means responsive to selected ones of said access-request signals for allocating, only within a memory element associated with the requesting central processing unit means, physical storage space for the data page associated with the requested data subpage, wherein that space is the exclusive physical storage space for the requested data subpage with respect to all of said memory elements, and for storing the requested data subpage in that allocated physical storage space, C. said memory management means further includes backing store means for transferring information-representative signals forming a selected data page to a secondary storage device.

103. A digital data processing apparatus according to claim 102, comprising A. directory means associated with one or more of said memory elements for storing one or more descriptor signals, each identifying a corresponding data page for which physical storage space is allocated therein, each said descriptor signal including at least one field component signal representative of a status of the corresponding data page, and B. said backing store means includes means for transferring to the secondary storage device, substantially concurrently with the transfer of information-representative signals forming a selected data page, one or more field component signals of the descriptor signal corresponding to that selected data page.

104. A digital data processing apparatus according to claim 103, wherein A. said memory management means including state-defining means coupled with said plural memory elements for associating an access state with one or more information-representative signals stored therein, said access state including an atomic owner access state associable with an data subpage modifiable by a central processing unit means associated with a memory element in which that data subpage is stored, no copy of which data subpage is stored in a memory element associated with another said central processing unit means, neither that information-representative signal, nor a copy thereof, being selectively accessible for transfer to a memory element associated with another said central processing unit means, B. said descriptor signal includes at least one field component signal representative of an atomic-modified state associable with one or more data subpages of the corresponding data page which subpage undergoes a transition into or out of atomic state, C. said backing store means includes means for transferring to the secondary storage device, substantially concurrently with the transfer of information-representative signals forming a selected data page, said atomic-modified state-representative field component signal corresponding to that selected data page.

105. A digital data processing apparatus according to any one of claims 72-84, characterized in that said memory management means includes processing means for responding to an access-request signal for accessing the requested information-representative signal asynchronously with respect to the execution of instructions by said requesting central processing unit.

106. A digital data processing apparatus of the type having plural central processing units, and plural memory elements for storing digital signals representative of information, each memory element being coupled for information transfer with an associated one of said central processing units, characterized in that A. at least a requesting one of said central processing units includes access request means for generating an access request signal representation of a request for access to an information-representative signal, B. said apparatus further including memory management means coupled to said plural memory elements for accessing one or more information-representative signals stored therein, and C. said memory management means including state-defining means coupled with said plural memory elements for associating an access state with one or more information-representative signals stored therein, said access state being selected from a group of access states including one or more of i) a read-only access state associable with a copy of an information-representative signal subject to read-only access by a central processing unit associated with a memory element in which that copy is stored, wherein said information-representative signal is stored in a memory element associated with another of said central processing units and is modifiable by that other central processing unit, ii) a nonexclusive owner access state associable with an information-representative signal modifiable by a central processing unit associated with a memory element in which that information-representative signal is stored, a copy of which information-representative signal is stored in a memory element associated with another said central processing unit, iii) an exclusive owner access state associable with an information-representative signal modifiable by a central processing unit associated with a memory element in which that information-representative signal is stored, no copy of which information-representative signal is stored in a memory element associated with another said central processing unit, that information-representative signal, or a copy thereof, being accessible for transfer to a memory element associated with another said central processing unit, and iv) an atomic owner access state associable with an information-representative signal modifiable by a central processing unit associated with a memory element in which that information-representative signal is stored, no copy of which information-representative signal is stored in a memory element associated with another said central processing unit, neither that information-representative signal, nor a copy thereof, being selectively accessible for transfer to a memory element associated with another said central processing unit.

107. A digital data processing apparatus according to claim 106, the further improvement wherein said state-defining means includes A. means for selectively and exclusively associating any one of i) said atomic owner access state, and ii) said exclusive owner access state with an information-representative signal stored in said plural memory elements, and B. means for selectively and exclusively associating said nonexclusive owner access state with one of (n) copies of an information-representative signal stored in said plural memory elements, where (n) is an integer greater than or equal to one.

108. A digital data processing apparatus according to claim 106, the further improvement wherein said state-defining means includes means for selectively associating any one of i) said read-only access state, and ii) said invalid access state with (n-1) copies of an information-representative signal stored in said plural memory elements.

109. A digital data processing apparatus according to claim 106, the further improvement wherein said memory management means includes means responsive to association of said atomic access state with an information-representative signal stored in a memory element associated with a first central processing unit for preventing access to that information-representative signal in response to a first selected access request signal generated by any other said central processing unit.

110. A digital data processing apparatus according to claim 109, wherein A. said memory management means includes means for responding to a second selected access request signal generated by a second central processing unit, and directed to one or more information-representative signals associated with the atomic owner access state, for effecting transfer of those requested signals to the memory element associated with said second central processing unit, and B. said state-defining means includes means for associating the atomic owner state with those transferred signals for allocating, exclusively, in the memory element associated with the second central processing unit physical storage space for said one or more requested information-representative signals.

111. A digital data processing apparatus according to claim 106, wherein A. said state-defining means includes means responsive to an access request signal generated by a requesting central processing unit and directed to an information-representative signal stored in a memory element associated with an owning central processing unit, said information-representative signal being associated with said atomic access state, for associating with that information-representative signal a transient atomic state, B. said owning central processing unit includes means for generating a release signal representative of a release of said requested information-representative signal from said atomic access state, C. said memory management means includes means responsive to a release signal generated by said owning central processing unit and directed to said requested information-representative signal for transmitting a copy of that information-representative signal to the memory element associated with the requesting central processing unit.

112. A digital data processing apparatus according to claim 106, the further improvement wherein A. said access request means includes means for generating an exclusive access request signal representative of a request for exclusive access to an information-representative signal, and B. said state-defining means includes means responsive to an exclusive access request signal generated by said requesting central processing unit, said exclusive access request being representative of a request for exclusive access to an information-representative signal stored in a memory element associated with another of said central processing units, wherein that information-representative signal is associated with said readonly access state, for effecting exclusive transfer of that information-representative signal to said requesting central processing unit and for associating the copy of that information-representative signal stored in the memory element associated with that other central processing unit with said invalid access state.

113. A digital data processing apparatus according to claim 106, the further improvement wherein A. said access request means includes means for generating a nonexclusive access-request signal representative of a request for nonexclusive access to an information-representative signal, and B. said state-defining means includes means responsive to a nonexclusive access request signal generated by said requesting central processing unit, said nonexclusive access request signal being representative of a request for nonexclusive access to an information-representative signal stored in a memory element associated with another of said central processing units, wherein that information-representative signal is associated with any one of an exclusive access state and a nonexclusive access state, for effecting exclusive transfer of that information-representative signal to said requesting central processing unit and for associating the information-representative signal stored in the memory element associated with that other central processing unit with said read-only access state.

114. A digital data processing apparatus according to claim 106, the further improvement wherein A. the access request means associated with a requesting one of said central processing units includes stop request means for generating a stop request signal representative of a pending request for atomic owner access to an information-representative signal, B. said memory management means includes means responsive to said stop request signal for effecting exclusive storage of a next available copy of the requested information-representative signal in the memory element associated with a requesting central processing unit, and C. said state-defining means includes means responsive to said stop request signal for assigning said atomic owner access state to said next available copy of the requested information-representative signal stored in the memory element associated with said requesting central processing unit.

115. A digital data processing apparatus according to claim 106, wherein said memory management means includes means responsive to a request for priority access to an information-representative signal generated by a first central processing unit for responding to subsequent requests for access to that same information-representative generated by others of said central processing units for generating a transient signal for transmission to said other central processing units, said transient signal being representative of current ownership of said requested information-representative signal by said first central processing unit.

116. A digital data processing apparatus according to any one of claims 72-84, comprising:

a plurality of information transfer domains each including one or more segments, said plurality of information transfer domains including a first information transfer domain having a plurality of domain(O) segments, each including an associated unidirectional bus element coupled in a ring configuration to said memory management means for transferring information-representative signals between a respective plurality of said processing cells.

117. A digital data processing apparatus according to claim 116, comprising:

a domain(1) segment comprising an associated unidirectional bus element and a plurality of routing elements, each said routing element being connected to the bus element associated with the domain(1) segment and to the bus element associated with one of said domain(O) segments for transferring information-representative signals between the domain(l) segment and the associated domain(O) segment, the processing cells associated with each of said domain(O) segments being capable of information-representative signal transfer with the processing cells associated with the remainder of said domain(O) segments only through the domain(1) segment.

118. A digital data processing apparatus according to any one of claims 72-84 comprising:

A. (n) information transfer domains, each respectively designated as information transfer domain(k), wherein (n) is an integer greater than or equal to two, and wherein (k) represents successive integers between (0) and (n-1), inclusive, B. information transfer including a plurality of domain(O) segments, each such segment including a bus element connected to said memory management means for transferring information-representative signals between a plurality of said processing cells, C. each information transfer domain(k), for (k) between (1) and (n-1), inclusive, including one or more corresponding domain(k) segments, wherein the number of segments in information domain(k) is less than the number of segments in domain(k-1), for each value of (k), and wherein information transfer domain(n-1) includes only one such segment.

119. A digital data processing apparatus according to claim 1 18 wherein each said domain(k) segment includes A. a bus element for transferring information-representative signals within that domain(k) segment, B. plural domain routing elements for transferring information-representative signals between that domain(k) segment and a domain(k-1) segment, each such routing element being connected for information-representative signal transfer with the respective domain(k) segment bus element and with the respective domain(k-1) segment bus element.

120. A method of operating a digital data processing apparatus, said apparatus including plural processing cells, each including a central processing unit coupled to an associated memory element, the method comprising the steps of A. generating within a requesting one of said central processing units an ownership-request signal representative of a request for priority access to an information-representative signal, B determining whether the requested information-representative signal is stored within a memory element other than one associated with the requesting central processing unit, and C. responding to a determination that the requested information-representative signal is stored in a memory element other than the one associated with the requesting central processing unit for allocating, only within the memory element associated with the requesting central processing unit and exclusive of the memory elements associated with the other central processing units, physical storage space for the requested information-representative signal and for storing that signal therein.

121. A method of operating a digital data processing system according to claim 120, wherein said responding step includes the further step of deallocating physical storage space, if any, allocated to the requested information-representative signal within the memory elements associated with central processing units other than the requesting one.

122. A method as claimed in claim 121, including the step of storing one or more descriptor signals, each identifying a corresponding data page for which physical storage space is allocated within an associated one of said memory elements, each said descriptor signal including i) a tag component signal identifying the corresponding data page, ii) at least one field component signal representative of a status of one or more of the subpages which form the corresponding data page.

123. A method of operating a digital data processing apparatus according to claim 121, wherein said responding step includes the step of responding to a read-only signal generated by a requesting one of said central processing units, said read-only signal being representative of a request for secondary access to an information-representative signal stored in a memory element associated with another of said other central processing units, for transferring a copy of that information-representative signal to the memory element associated with the requesting central processing unit.

124. A method of operating a digital data processing apparatus according to claim 121, wherein A. said responding step including the step of responding to an atomic-request signal generated by a first one of said central processing units, said being representative of a request for exclusive priority access to one or more information-representative signals, for i) allocating, exclusively, in the memory element associated with the first central processing unit physical storage space for said one or more requested information-representative signals and for storing those information-representative signals therein, while ii) preventing access to any of those information-representative signals in response to a first selected access request signal generated by a second one of said central processing units.

125. A method as claimed in any one of claims 120-124 and 129 characterized in that A. said generating step includes the step of generating a subpage-request signalrepresentative of a request for access to a data subpage stored in one or more of said memory elements, B. said responding step includes the steps of responding to at least selected ones of said subpage-request signals by i) allocating, within the memory element associated with the requesting central processing unit, physical storage space for the data page associated with the requested data subpage, said data subpage comprising one or more information-representative signals and forming at least part of a data page, ii) storing the requested data subpage in that allocated physical storage space,and C. said method of further including the step of deallocating physical storage space allocated to a selected data page in one or more of said memory elements, said deallocating step being effected prior to, or substantially concurrent with, the allocating step.

126. A method as claimed in claim 125, further characterized in that said deallocating step includes the step of selecting for deallocation a data page for which physical storage space is allocated in at least a first memory element and a second memory element.

127 A method as claimed in claim 126, wherein said deallocating step includes the step of storing one or more access history-representative signals representative of a history of access of respective ones of data pages for which physical storage space is allocated within one or more of said memory elements.

128. A method as claimed in any one of claims 120-124 and 129 comprising the steps of A. associating an access state with one or more information-representative signals stored in said plural memory elements, said access state being selected from a group of access states including one or more of i) a read-only access state associable with a copy of an information-representative signal subject to read-only access by a central processing unit associated with a memory element in which that copy is stored, wherein said information-representative signal is stored in a memory element associated with another of said central processing units and is modifiable by that other central processing unit, ii) a nonexclusive owner access state associable with an information-representative signal modifiable by a central processing unit associated with a memory element in which that information-representative signal is stored, a copy of which information-representative signal is stored in a memory element associated with another said central processing unit, iii) an exclusive owner access state associable with an information-representative signal modifiable by a central processing unit associated with a memory element in which that information-representative signal is stored, no copy of which information-representative signal is stored in a memory element associated with another said central processing unit, that information-representative signal, or a copy thereof, being accessible for transfer to a memory element associated with another said central processing unit, and iv) an atomic owner access state associable with an information-representative signal modifiable by a central processing unit associated with a memory .' 129 element in which that information-representative signal is stored, no copy of which information-representative signal is stored in a memory element associated with another said central processing unit, neither that information-representative signal, nor a copy thereof, being selectively accessible for transfer to a memory element associated with another said central processing unit.

129. A method as claimed in claim 121, the further improvement comprising the steps of A. generating, within a requesting one of said central processing units, an exclusive access request signal representative of a request for priority access to an information-representative signal, and B. responding to an exclusive access request signal generated by said requesting central processing unit, said exclusive access request being representative of a request for exclusive access to an information-representative signal stored in a memory element associated another of said central processing units, wherein that information-representative signal is associated with an access state other than said atomic ownership state, for effecting exclusive transfer of that information-representative signal to said requesting central processing unit and for associating the copy of that information-representative signal stored in the memory element associated with that other central processing unit with the invalid access state.

130. A digital data processing apparatus according to any one of claims 72-84, characterized in that A. at least a requesting central processing unit includes execution means for executing a sequence of instructions, a first instruction of which comprises a memory access request instruction for causing the executing central processing unit to generate an access-request signal representative of a request for access to an information-representative signal, said execution means including means for i) responding to said memory access request instruction for generating said access-request signal, and ii) commencing execution of the remaining instructions of said first sequence, at least the memory element associated with the requesting central processing unit including control means for selectively transmitting said access-request signal to said memory management means, and B. said memory management means includes processing means for responding to saidaccess-request signal for accessing the requested information-representative signal asynchronously with respect to the execution of the remaining instructions of said sequence by said requesting central processing unit.

131. A digital data processing apparatus according to claim 130, wherein said processing means includes means for performing at least one of the following functions asynchronously with respect to the execution of the remaining instructions of said sequence:

i) allocating physical storage space for the requested information-representative signal, or a copy thereof, in one or more of said memory elements, ii) deallocating physical storage space associated with requested information-representative signal, or a copy thereof, in one or more of said memory elements, iii) transferring the requested information-representative signal, or a copy thereof, to said requesting central processing unit, and iv) storing said requested information-representative signal in physical storage space allocated in one or more of said memory elements.

132. A digital data processing apparatus according to claim 131, wherein A. said execution means includes means for responding to a selected access request instruction for generating said access-request signal to be representative of a request for access to said requested information-representative signal in a selected access state, B. said memory management means includes means for providing access to said requested information-representative signal in the selected access state asynchronously with respect to the execution of the remaining instructions of said sequence by said requesting central processing unit.

133. A digital data processing apparatus according to claim 132, wherein A. said execution means includes means for responding to a selected access request instruction for generating said access-request signal to be representative of a request for access to said requested information-representative signal in an access state selected from a group of access states including one or more of i) a read-only access state associable with a copy of an information-representative signal subject to read-only access by a central processing unit associated with a memory element in which that copy is stored, ii) a nonexclusive owner access state associable with information-representative signal modifiable by a central processing unit associated with a memory element in which that information-representative signal is stored, a copyof which information-representative signal is stored in a memory element associated with another said central processing unit, iii) an exclusive owner access state associable with information-representative signal modifiable by a central processing unit associated with a memory element in which that information-representative signal is stored, no copy of which information-representative signal is stored in a memory element associated with another said central processing unit, that information-representative signal, or a copy thereof, being accessible for transfer to a memory element associated with another said central processing unit, and iv) an atomic owner access state associable with an information-representative signal modifiable by a central processing unit associated with a memory element in which that information-representative signal is stored, no copy of which information-representative signal is stored in a memory element associated with another said central processing unit, neither that information-representative signal, nor a copy thereof, being selectively accessible for transfer to a memory element associated with another said central processing unit, B. said memory management means includes means for providing access to said requested information-representative signal in the selected access state asynchronously with respect to the execution of the remaining instructions of said sequence by said requesting central processing unit.

134. A digital data processing apparatus according to claims 72-84, characterized in that A. at least a requesting central processing unit includes execution means for executing a sequence of instructions, a first instruction of which comprises a PREFETCH instruction for causing the executing central processing unit to generate a PREFETCH signal representative of a request for transfer of an information-representative signal, or copy thereof, to a memory element associated with the requesting central processing unit, said execution means including means for i) responding to said PREFETCH instruction for generating said PREFETCH
signal, and ii) commencing execution of the remaining instructions of said first sequence, at least the memory element associated with the requesting central processing unit including control means for selectively transmitting said PREFETCH signal to said memory management means, and B. said memory management means includes processing means for responding to saidPREFETCH signal for transferring the requested information-representative signal, or a copy thereof, to a memory element associated with the requesting central processing unit asynchronously with respect to the execution of the remaining instructions of said sequence by said requesting central processing unit.

135. A digital data processing apparatus according to claim 134, wherein said processing means includes means for performing at least one of the following functions asynchronously with respect to the execution of the remaining instructions of said sequence by said requesting central processing unit:

i) allocating physical storage space for the requested information-representative signal, or a copy thereof, in a memory element associated with the requesting central processing unit, ii) deallocating physical storage space associated with requested information-representative signal, or a copy thereof, in one or more of said memory elements, and iii) transferring the requested information-representative signal, or a copy thereof, to the requesting central processing unit.

136. A digital data processing apparatus according to claim 135, wherein A. said execution means includes means for responding to a selected PREFETCH
instruction for generating said PREFETCH signal to be representative of a request for access to said requested information-representative signal in a selected access state, B. said memory management means includes means for providing access to said requested information-representative signal in the selected access state asynchronously with respect to the execution of the remaining instructions of said sequence by said requesting central processing unit.

137. A digital data processing apparatus according to claim 136, wherein A. said execution means includes means for responding to a selected access request instruction for generating said PREFETCH signal to be representative of a request for access to said requested PREFETCH signal in an access state selected from a group of access states including one or more of i) a read-only access state associable with a copy of an information-representative signal subject to read-only access by a central processing unit associated with a memory element in which that copy is stored, ii) a nonexclusive owner access state associable with information-representative signal modifiable by a central processing unit associated with a memory element in which that information-representative signal is stored, a copy of which information-representative signal is stored in a memory element associated with another said central processing unit, iii) an exclusive owner access state associable with information-representative signal modifiable by a central processing unit associated with a memory element in which that information-representative signal is stored, no copy of which information-representative signal is stored in a memory element associated with another said central processing unit, that information-representative signal, or a copy thereof, being accessible for transfer to a memory element associated with another said centralprocessing unit, and iv) an atomic owner access state associable with an information-representative signal modifiable by a central processing unit associated with a memory element in which that information-representative signal is stored, no copy of which information-representative signal is stored in a memory element associated with another said central processing unit, neither that information-representative signal, nor a copy thereof, being selectively accessible for transfer to a memory element associated with another said central processing unit, and B. said memory management means includes means for providing access to said requested information-representative signal in the selected access state asynchronously with respect to the execution of the remaining instructions of said sequence by said requesting central processing unit.

138. A method according to any one of claims 120 - 124 or 129, including the further steps of A. executing, within at least a requesting central processing unit, a sequence of instructions, a first instruction of which comprises a memory access request instruction for causing the executing central processing unit to generate an access-request signal representative of a request for access to an information-representative signal, said executing step including i) responding to said memory access request instruction for generating said access-request signal, and ii) commencing execution of the remaining instructions of said first sequence, and B. transferring selected ones of said access-request signals to a memory management element, and C. responding, within said memory management element, to said access-request signal for accessing the requested information-representative signal asynchronously with respect to the execution of the remaining instructions of said sequence by said requesting central processing unit.

139. A method for operating a digital data processing apparatus according to any one of claims 120-124 or 129, further comprising the steps of A. executing, within at least a requesting central processing unit, a sequence of instructions, a first instruction of which comprises a PREFETCH instmction for causing the executing central processing unit to generate a PREFETCH signal representative of a request for transfer of an information-representative signal, or copy thereof, to a memory element associated with the requesting central processing unit, said executing step including i) responding to said PREFETCH instruction for generating said PREFETCH
signal, and ii) commencing execution of the remaining instructions of said first sequence, selectively transmitting said PREFETCH signal to a memory management element, and C. responding, within said memory management element, to said PREFETCH signal for transferring the requested information-representative signal, or a copy thereof, to a memory element associated with the requesting central processing unit asynchronously with respect to the execution of the remaining instructions of said sequence by said requesting central processing unit.