CA1317683C - Intercommunication network capable of carrying out intercommunication without transmission of a destination number from a transmission source - Google Patents
Intercommunication network capable of carrying out intercommunication without transmission of a destination number from a transmission sourceInfo
- Publication number
- CA1317683C CA1317683C CA000601613A CA601613A CA1317683C CA 1317683 C CA1317683 C CA 1317683C CA 000601613 A CA000601613 A CA 000601613A CA 601613 A CA601613 A CA 601613A CA 1317683 C CA1317683 C CA 1317683C
- Authority
- CA
- Canada
- Prior art keywords
- processor
- zeroth
- transmission
- communicable
- processors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
Abstract
Abstract of the Disclosure In an intercommunication network for use in transmitting a transmission request from a first processor to a second processor, the first processor sends a first processor number preassigned thereto through a system bus to the second processor which holds a communicable processor number corresponding to the first processor number and which detects whether or not the first processor number indicates the first processor by monitoring correspondence between the first processor number and the communicable processor number. A
destination processor number assigned to the second processor may not be transmitted from the first processor because identification is made in the second processor. Thus, no destination processor number is administrated in the first processor. The first and the second processors may belong to a lower rank and an upper rank, respectively, and may be an input/output processor and an execution processor unit, respectively.
destination processor number assigned to the second processor may not be transmitted from the first processor because identification is made in the second processor. Thus, no destination processor number is administrated in the first processor. The first and the second processors may belong to a lower rank and an upper rank, respectively, and may be an input/output processor and an execution processor unit, respectively.
Description
INTERCOMMUNICATION NETWORK CAPABLE OF CARRYING
OUT INTERCOMMUNICATION WITHOUT TRANSMISSION OF
; ; A DESTINATION NUMBER FROM A TRANSMISSION SOURCE
~, :
`,, :~: ~ ~
;~ This invention relates to an intercommunication :! .
:l network for use in carrying out communication among a pIurality of processors, such as execution processor 5:units, input/output processors, and the like, which are connected to one another through a system bus to form a : multiprocessor system.
. : In a conventional intercommunication network of . ~, ;~ ~ the type described, a plurality of processors are 10 classifiable into an upper rank one composed of execution processing units~and a lower rank one composed of input/output processors and the~like. Therefore, the e~ecution processing units and the i~nput/output pro~ce~ssors will be hereinunde~r called upper and lower 5 rank~processors,: respectlvely,~ when they are : *istingu~ished from eaoh other.~
: :. ` : :: : : :
:
:' :::
-~ 1 31 7683 In general, when a transmission or communication request takes place at a first one of the processors used as a transmission end or source to start communication with a second one of the processors that 5 is operable as a reception or destination end, the first processor supplies the bus with a processor number preassigned to the second processor in addition to an intercommunication command. In this connection, such a proces~or number may be referred to as a destination 10 processor number. Each of the processors always monitors the destination processor number on the bus to detect whether or not the destination processor number is destined to each processor. To this end, the destination processor number is compared with a lS preassigned processor number assigned to each processor.
In the above-mentioned example, the second processor alone receives and detects the destination processor num~er to judge that the destination processor number is destined to the second processor~ Thereafter, the 20 second processor supplies an interruption request to a control circuit operahle in accordance with firmware.
As a result, the second processor is put into a communicable state with the first processor.
An intercommunication network of the ~; 25 abDve-mentioned type is very effective to carry out intercommunication between processors, such as execution processor units, hoth of which belong to the same rank and which do not have a master-slave relationship.
..,,, ~ .
:
On the other hand, it often happens that similar intercommunication is carried out between an upper rank processor and a lower rank processor. In this event, a transmission end transmits a destination processor 5 number to a reception end like in the intercommunication between the execution processor units.
More specifically, when the upper rank processor and the lower rank processor act as the transmission and the reception ends, respectively, so as to transfer a 10 communication signal from the upper rank processor to the lower rank one, the upper rank processor supplies the lower rank processor with a destination processor number assigned to the lower rank processor. Thus, each upper rank processor is communicable with all the lower 15 rank processors by specifying the lower rank processors by the destination processor number.
To the contrary, when a communication request takes place at a lower r~nk processor which is operable as the transmission end, so as to transfer a data signal 20 sequence to be processed by the upper rank processors, the lower rank processor produces a destination processor number assigned to a selected one of the upper ~; rank processors to indicate the selected upper rank processor. ~lowever, it is to be noted that the data 25 signal sequence produced from the lower rank processor may be often processed in any one of the upper rank processors, if each of the upper rank processors can carry out processing in similar manners. In this event, ` 131768:~
it is not always desirable to specify a selected one of the upper rank processors by producing the destination processor number preassigned to the selected upper rank processor and to monitor a state of the selected upper 5 rank processor in the lower rank processor.
Specifically, each lower rank processor should always be conscious of a destination processor number communicable with each lower rank processor and must transmit such a destination processor number on transmission of the 10 transmission request. Therefore, each lower rank processor must be formed by the use of complexed hardware and firmware and should bear comparatively heavy load.
Summary of the Invention:
It is an object of this invention to provide an intercommunication network wherein each lower rank processor may be structured by the use of simple har~ware and firmware.
It is another object of this invention to 20 provide an interco~munication network of the type described, which can alleviate load ln each lower rank processor.
It is still another object of this invention to proYide an intercommunication network of the type 25 describedj wherein a transmission source may not be - conscious or a destination processor number.
An intercommunication network to which this invention is applicable i5 for use in carrying out , , , . .
communication among a plurality of processors in a multiprocessor system. The processors are connected to one another through a system bus and comprise first and second processors which have first and second 5 preassigned processor numbers assigned thereto, respectively, and which are operable as a transmission source for transmitting a transmission request and a destination end for receiving the transmission request, respectively. The first processor comprises producing 10 means for producing the first preassigned processor number assigned to the first processor and sending means for sending the first preassigned processor number as a transmission source number on transmission of the ; transmission request to the system bus. The second 15 processor comprises holding means for holding a communicable processor number corresponding to the first preassigned processor number and detecting means coupled to the system bus and the holding means for detecting whether or not the transmission source number indicates 20 the 1rst processor by checking correspondence between the transmission source number and the communicable processor number. The detecting means produces an interruption request signal when both the transmission source number and the communicabl~e processor number :
~ 25 indicate the first processor.
;
, Brief Description of the Drawing:
Fig. 1 is a block diagram of an ; intercommunication network to which this invention is appli cabl e;
Fig. 2 is a block diagram o~ an execution ~; processor unit according to a preferred embodiment of this invention;
Fig. 3 is a block diagram of an input/output processor communicable with the execution processor unit 10 illustrated in Fig~ 2; and Fig. 4 is a block diagram of a portion of the execution processor unit illustrated in Fig. 2.
Description of the Preferred Embodiment:
Referring to Fig. 1, an intercommunication 15 network to which this invention is applicable comprises zeroth through third execution processor units (EPU) 10, 11, 12, and 13, and æeroth through third input/output processors (IOP) 15, 16, 17, and 18 connected through a system bus 20 to one another and to the zeroth through 20 third execution processor units 10 to 13. In addition, a main memory unit 21 is also connected to the system `~ bus 20 to be used in common to the zeroth through third execution~processor units 10 to 13 and the zeroth through third input~output processors 15 to 18. The 25 zeroth through third execution processor units 10 to 13 are operable as upper rank~processors relative to the input/output processors 15 to 18, while the input/output processors 15 to 18, lower rank processors. At any ... .
. ~ .
:
: .- . - - .: .
. ~ - :
~ . ~ . - , .
:~ , :- - ..
~ 1 3 ~ 7683 rate, the execution processor units 10 to 13 and the input/output processors 15 to 18 form a multiprocessor system along with the system bus 20 and the main memory unit 21.
~erein, it is assumed that the zeroth through third execution processor units 10 to 13 of the upper rank are assigned with zeroth throu~h third primary processor numbers represented by binary numbers (0000), (0001), (0010), and (0011), respectively, while the 10 zeroth through third input/output processors 15 to 18 of the lower rank are assigned with zeroth through third :~ subsidiary processor numbers represented by (0100), (0101), ~0110), and (0111), respectively. In addition, each of the zeroth through third execution processor 15 units 10 to 13 is assumed to be similar in structure and operation to one another while each of the zeroth through third inputfoutput processors is assumed to be also similar in structure and operati.on to one another.
In the illustrated intercommunication network, 20 intercommunication is classified into first intercommunication between the execution processor units I0 to 13, second intercommunication from one of the : execution:processor units 10 to 13 to one of the npat/output processors 15 to I8, and third~
: 25 intercommunication from one of the inputjoutput , ~ :
:: processors 15 to 18 to one of the execution processor :: units 10 to 13. The first and the second lntercommunication may be carried out in a conventional ;-- -manner, as will become clear. ~owever, the thirdintercommunication will be carried out in a manner different from the conventional manner, as will later be described in detail. In addition, each of the execution 5 processor units 10 to 13 and the input/output processors 15 to 18 is communicable with the main memory unit 20 through the system bus 20.
Referring to Fig. 2 together with Fig. 1, the zeroth execution processor unit 10 is exemplified as a 10 representative of the zeroth through third execution processor units 10 to 13 and comprises a central processing unit 25 and a bus interface circuit 26 connected to the central processing unit 25 and the system bus 20. The illustrated system bus 20 comprises 15 a command bus 201 and an address/data bus 202 each of which is composed of a plurality of bus lines, although ; each bus is represented only ~y a single line~
In Fig. 2, it is assumed that the first intercommunication is carried out between the execution 20 processor units 10 to 13 and that the illustrated zeroth execution processor unit 10 is operable as a transmission end or a transmission source and communicates with a selected one of the other execution ~' ` ~ ~ processor units that may be called a destination or 25 reception end. The first intercommunication may be .
similar to that of a conventional network. More specifically, the zeroth processor unit 10 at first issues a communication or transmission request to ' '' ` ' identify the destination end or processor. The communication request is specified by a command signal CMD representative of a command and a specific one of the zeroth through third primary processor numbers that 5 is assigned to the destination end and that may be called a destination processor number DEST. In this event, the command indicates the first intercommunica-: tion~ In addition, the communication request also : indicates a source processor number SRC, namely, the 10 zeroth primary processor number (0000~. The commandsignal CMD, the destination processor number DEST, and the source processor number SRC are sent from the `: cen~ral processing unit 25 to a command register 31, a destination number register 32, and a source number 15 register 33 through a first internal line 36 to be kept in the respective registers 31, 32, and 33, respectively. The command signal CMD, the destination processor number DE~T, and the source processor number SRC are delivered from the oommand register 31, the 20 destination numher register 32, and the source number register 33 through a first driver 37 to the command bus 201. Thus, the communication request is sent to all of : the other processors through the command bus 201.
: When the illustrated zeroth execution processor ~, 25 unit 10 is operable as a destination end in the first intercommanication, a command signal CMD, a destination :~ processor number DEST, and a source processor number SRC
~ are received and held through the command bus 201 and a ~, .
lo 1 3 1 7683 first receiver 39 as a received command signal RCMD, a received destination processor number RDEST, and a received source processor number RSRC by a reception command register 41, a reception destination number 5 register 42, and a reception source number register 43, respectively. The received command signal RCMD is sent ~ from the reception command register 41 to a command ; decoder 45 through an internal command line 46.
If the received command signal RCMD is judged to 10 be representative of the first intercommunication, the command decoder 45 sends a logic "1" level signal to the central processing unit 25 through a second internal line 47. On the other hand, the received destination processor number RDEST is sent from the reception 15 destination number register 42 to the central procassing unit 25 through a third internal line 48. Supplied with the logic "1" level signal and the received destination processor number RDEST from the command decoder 45 and the reception destination number register 42, 20 respectively, the central processing unit 25 detects the first intercommunication and compares the received destination processor number RDEST with the zeroth primary processor number (0000) assigned to the zeroth execution processor unit 10. If the received 25 destination processor number RDEST is coincident with the zeroth primary processor number (0000), the central ~: processing unit 25 of the zeroth execution processor : unit 10 judges that the communication request in , , .
,, - .
,~ , " ~
question is destined to the zeroth execution processor unit 10. Such judgement may be made in a usual manner and will not be described any longer.
Thereafter, the first intercommunication is 5 carried out between the execution processor units 10 to 13 in the manner known in the art by transferring a sequence of data signals from one of the execution processor units 10 to 13 to another. On transferring the data signal sequence, the illustrated execution 10 processor unit 10 sets the data signal sequence from the central processing unit 25 to an address/data register 51. Subsequently, the data signal sequence is delivered from the address/data register 51 to the address/data bus 202 through the second driver 52. To the contrary, 15 a reception data signal sequence is sent from the address/data bus 202 to a reception address/data register 53 through a second receiver 54 on receiving the reception data signal sequence and is thereafter delivered to the central processing unit 25. Similar 20 data transfer is carried out in the second and the third intercommunication by the use of the address/data ; register 51 and the reception address/data register 53 also.
The address/data register 51, the second driver 25 52, the reception address/data register 53, and the second receiver 54 are used not only in the first through third intercommunication but also in a data trans~fer operation between each execution processor unit .
: :, '' ' , ~ '' 10 to 13 and the main memory unit 21 (Fig. 1). On such a data transfer operation between each execution processor unit 10 to 13 and the main memory unit 21, each of the address/data register 51 and the reception 5 address/data register 53 is loaded with an address signal and a data signal.
In the second intercommunication from each of the zeroth through third execution processor units 10 to 13 of the upper rank to either one of the zeroth through 10 third input/output processors 15 to 18 of the lower rank, each execution processor unit 10 to 13 supplies .~ :
the command bus 201 with the command signal CMD, the destination processor number DEST, and the source processor number SRC like in the first intercommunica-15 tion mentioned before. In this event, it is to be noted that the command signal CMD is indicative of the second intercommunication while the destination processor number DES~ specifies either one of the 2eroth through ~` third input/output processors 15 to 18.
;`; 20 In Figs. 1 and 2, let the third intercommunica-tion be carried out from either one of the zeroth through third input/output processors 15 to 18 to a selected one of the zeroth through third execution prooessor units 10 to 13 that may be assumed to be the :
'25 zeroth execution processor unit 10 without loss of ` g~nerality.
Temporarily referring to Fig. 3, each input/output processor 15 to 18 is similar in structure ' ::
, .
.
and operation to one another and is therefore exemplified by the zeroth input/output processor 15.
The zeroth input/output processor 15 comprises a subsidiary central processing unit 25' and a subsidiary 5 bus interface unit 26'. The subsidiary central processing unit 25' may be simple in structure and operation in comparison with a conventional one, as will become clear as the description proceeds.
The subsidiary bus interface unit 26' comprises 10 a command register 31', a destination processor number register 32', a source processor number register 33', a reception command register 41', a reception destination processor number register 42', and a reception source processor number register 43' which correspond to those 15 of Fig. 2, respectively. In addition, a command decoder 45' ~s also included in the subsidiary bus interface ~ unit 26' in correspondence to the command decoder 45 ; illustrated in Fig. 2. All of the above-mentioned elements are known in the art and are therefore not 20 shown in Fig. 2.
On carrying out the third intercommunication, the ~eroth input/output processor 15 supplies the command bus 201 with a command signal CMD and a source processor number SRC through a driver 37'. In this 25 case, the command signal CMD specifies the third :: :
` communication wh1le the source processor number SRC
specifies the zeroth subsidiary processor number (0100).
The command signal CMD and the source processor number ., :
SRC are delivered from the command register 31' and the source processor number register 33' through the driver 37' to the command bus 201. Accordingly, the source processor number register 33' is operable to produce the 5 source processor number S~C while the driver 37' is operable to send the source processor number SRC to the system bus 201 Moreover, a dummy number is also sent instead of the destination processor number DEST from the 10 destination processor number register 32 even in the third intercommunication. The dummy number is practically not used as the destination processor number DEST in a destination one of the execution processor units 10 to 13, as will become clear.
; 15 In Figs. 2 and 3, let predetermined relationships be present between the zeroth through third input/output processors 15 to 18 and the zeroth through third execution processor units 10 to 13 on carrying out the third intercommunication. In other 20 words, dependencies of the zeroth through third input/output processors 15 to 18 are predetermined for the zeroth through third execution processor units 10 to 13. For example, the zeroth input/output processor 15 is assumed to be communicable only with the zeroth 25 execution processor unit 10 in the third intercommunica-: tion. Such dependencies of the zeroth through third input~output processors 15 to 18 are monitored by the zeroth through third execution processor units 10 to 13.
. . .
' `
:
As a result, each of the zeroth through third executionprocessor units lO to 13 identifies the input/output processor which is communicable with each execution processor unit 10 to 13 in a manner to be described 5 later.
Now, it is assumed that the communication request is issued from the zeroth input/output processor unit 15 to the zeroth execution processor unit lO to carry out the third intercommunication. In this event, lO the zeroth input/output processor 15 acts as the transmission end or transmission source while the zeroth execution processor unit lO acts as the destination or reception end. The communication request in the third intercommunication is specified by the command signal 15 CMD representative of the third intercommunication and the souxce processor number SRC, namely, (0100) representative of the zeroth input/output processor 15.
The command signal CMD and the source processor number SRC are sent from the command register 31' and the 20 source processor number register 33' of the zeroth input/output processor 15 to the command bus 201. As :
mentioned before, the dummy number is also sent from the : destination processor number register 32' to the command : bus 201.
25 :~ ~; In Fig. 2, the command:signal CMD and the source ~processor number SRC~are delivered from the command bus : 201 to each of the zeroth through third execution processor units lO to 13. In the zeroth execution i ,~ s, .. - . , - - :
, ', processor unit 10, the command signal CMD and the source processor number SRC are kept as the received command signal RCMD and the received source processor number RSRC in the reception command register 41 and the 5 reception source number register 43, respectively. The ~ummy number is also held as the received destination processor number RDEST in the reception destination number register 42.
The received command signal RCMD is sent from lO the reception command register 41 to the command decoder 46. When the command decoder 46 judges that the received command signal RCMD indicates the third intercommunication, the command decoder 46 produces an indication signal of the logic "1" level representative 15 of the third intercommunication.
Referring to Fig. 4 together with Fig. 2, the indication signal is sent from the command decoder 45 through a fourth internal line 64 to a request judgement ;clrcuit 65. The request judgement circuit 65 is 20 supplied with the received source processor number RSRC
from the reception source number register 43 through a fifth internal line 68. Furthermore, the illustrated bus interface circuit 26 c~omprises an input/output processor number (IOPN) register 71 connected to the 25 central processing unit 25 through a sixth internal line .
~72.~ The IOPN register 71 is loaded~under control of the :~: central processing unit 25 wi~h a communicable processor number which corresponds to one of the input/output '~; :
. .
.
, :.:
~ 1 31 7683 processors 15 to 18 that is communicable with the zeroth execution processor unit 10 and that is determined by the above-mentioned dependencies. ~herefore, the IOPN
register 71 is operable to hold the communicable 5 processor number and may be called a holding register for holding the communicable processor number.
The communicable processor number specifies each input/output processor by a bit position of the logic "1" level assigned to each of the input/output 10 processors 15 to 18. In the example being illustrated, ~he communicable processor number is represented by four bits arranged from a zeroth or most significant bit to a third or least significant bit. The zeroth through third bits are determined for the zeroth through third 15 input/output processors 15 to 18, respectively. As mentioned before, the zeroth execution processor unit 10 is communicable with the zeroth input/output processor lS and the communicable processor number must therefore specify the æeroth input/output processor 15. Under the ~; 20 circumstances, the communicable processor number in the zeroth execution processor unit 10 is represented by (1000) having the zeroth bit of the logic "1" level.
.
`~ ~ In Fig. 4, the IOPN register 71 is composed of zeroth through third bit registers 710 to 713 loaded ~;~ 25 with~the zeroth through third bits tl000) of the ;~ communicable processor number, respectively. Likewise, ~ the reception source processor number register 43 is -~ composed of zeroth through third reception registers 430 . , :
:
:: :
.
18 ~317683 to 433 which are loaded with the received source processor number RSRC represented by the binary eode of ~0100), respectively. Under the circumstances, the request judgement circuit 65 judges or checks whether 5 the received source processor number RSRC indicates the zeroth input/output processor 15 specified by the communicable processor number (1000) of the zeroth exeeution processor unit 10. The request judgement : cireuit 65 produces an interruption request signal INT
10 when the received source processor number RSRC indieates the zeroth input/output processor 15. The interruption request signal INT is held in an interruption tINT) register 75 and is thereafter sent to the central proeessing unit 25 through a seventh internal line 77, 15 as shown in Fig. 2.
In this eonneetion, a eombination of the reeeption souree proeessor number register 43 and the request judgement eircuit 65 may be called a detection eireuit for deteeting whether or not the reeeived source 20 processor number RSRC indicates the zeroth input/output : processor 15 communieable with the zeroth execution processor unit 10.
More particularly, the request judgement circuit 65 il:lustrated in Fig. 4 comprises zeroth through third 25 AND gates 80 to 83 eonneeted to the zeroth through third bit registers 710 to 713, respeetively, an OR gate 84 : : eonneeted to the zeroth through third AND gates 80 to 83, and an output AND gate 85 connected to the OR gate ,', 19 ~ 31 7683 84 and the command decoder 45 through the fourth internal line 64. On the other hand, the zeroth reception register 430 of the reception source processor number register 43 is connected to the output AND gate 5 85 through a first inverter 86 while the first reception register 431 is connected direct to the output AND gate 85. In addition, the second reception register 432 is connected to the second and the third AND gates 82 and 83 directly and also to the zeroth and the first AND
10 gate~ 80 and 81 through a second inverter 87. The third ; reception register 433 is connected to the first and the third A~D gates 81 and 83 directly and also to the zeroth and the second AND gates 80 and 82 through a third inverter 88.
With this structure, let the communicable processor number and the received source processor number RSRC be loaded with (1000) and (0100), ~ respectively. In this case, the zeroth AND gate 80 - alone is opened to supply the logic "1" level signal to 20 the output AND gate 85 through the OR gate 84. Thus, the received source processor number RSRC is checked by the~zeroth through third AND gates 80 to 83 and the second and the third lnverters 87 and 88, all of which may be called a checking circuit.
:: 25 ~ Inasmuch as the output AND gate 85 is supplied with the indication signal of the loglc "1" level from : ` :
the command decoder 45 and with the logic "1" levels :from the zeroth reception register 430 through the first , ~ :
,;, inverter 86 and from the first reception register 431, the output AND gate 85 is opened to produce the interruption request signal INT. The interruption request signal INT is sent to the central processing 5 unit 25 through khe interruption register 75.
Responsive to the interruption request signal INT, the central processing unit 25 recognizes that the communication request in question is sent from the zeroth input/output processor 15 determined for the 10 zeroth execution processor unit 10 by the above-mentioned dependencies.
; ~Thereafter, the zeroth input/output processor 15 transfers a sequence of data signals through the address/data but 202 to the zeroth execution processor 15 unit 10. The data signal sequence is received by the central processing unit 25 of the zeroth execution `~ processor unit 10 through the second receiver 54 and the reception address/data register 53.
In Fi~. 4, the communlcable processor number of 20 ~1000) may be changed to another under control of the central processing unit 25 to communicate with another one of the input/output processors when the input/output processors increase or decreasë in number. For example, ,:
~ when the communicable processor number is changed to -~ ~ 25;(0100~, the interruption request signal INT of the logic "1" leveI is produced from the output AND gate 85 on reception of the received source processor number RSRC
represented by (0101~. This shows that the illustrated , ~, .
~: .
.
~` 1317683 execution processor unit 10 is communicable with the first input~output processor 16 (Fig. lj. Likewise, when the communicable processor number and the received source processor number RSRC be equal to (0010) and 5 (01103, respectively, the second AND gate 82 is opened to produce the interruption request signal INT through the output AND gate 85. In addition, the request judgement circuit 65 illustrated in Fig. 3 can produce the interruption request signal INT when the 10 communicable processor number and the received source processor number RSRC are equal to (0001) and (0111), respectively.
With this structure, no destination processor ; number DEST may be produced from each input/output 15 processor 15 to 18 on the third communication, although description has been made on the assumption that the destination processor number is sent from each input/output processor as a dummy number. Accordingly, it is unnecessary to monitor or administrate the primary 20 processor numbers of the execution processor units.
; This means that each input/output processor may not be aware or conscious of the primary processor numbers.
This enables alleviation of a burden imposed on hardware or ~irmware of each input/output processor.
While this invention has thus far been described . .
in conjunction with a preferred embodiment thereof, it ill readily be possible for those skilled in the art to ~ .
~ ~ put this invention into practice in various other ~ I
, ,~, ~.1. . . ' . ;
22 1 ~1 7683 manners. For example, the upper and the lower rank processors may not be restricted to the execution processor units and the input/output processors. In addition, this invention may be applied to inter-S communication between processors of the same rank. Nodu~ny number may be sent ~rom the transmission source to the reception end.
;' .
~'~
~i :
;
'
OUT INTERCOMMUNICATION WITHOUT TRANSMISSION OF
; ; A DESTINATION NUMBER FROM A TRANSMISSION SOURCE
~, :
`,, :~: ~ ~
;~ This invention relates to an intercommunication :! .
:l network for use in carrying out communication among a pIurality of processors, such as execution processor 5:units, input/output processors, and the like, which are connected to one another through a system bus to form a : multiprocessor system.
. : In a conventional intercommunication network of . ~, ;~ ~ the type described, a plurality of processors are 10 classifiable into an upper rank one composed of execution processing units~and a lower rank one composed of input/output processors and the~like. Therefore, the e~ecution processing units and the i~nput/output pro~ce~ssors will be hereinunde~r called upper and lower 5 rank~processors,: respectlvely,~ when they are : *istingu~ished from eaoh other.~
: :. ` : :: : : :
:
:' :::
-~ 1 31 7683 In general, when a transmission or communication request takes place at a first one of the processors used as a transmission end or source to start communication with a second one of the processors that 5 is operable as a reception or destination end, the first processor supplies the bus with a processor number preassigned to the second processor in addition to an intercommunication command. In this connection, such a proces~or number may be referred to as a destination 10 processor number. Each of the processors always monitors the destination processor number on the bus to detect whether or not the destination processor number is destined to each processor. To this end, the destination processor number is compared with a lS preassigned processor number assigned to each processor.
In the above-mentioned example, the second processor alone receives and detects the destination processor num~er to judge that the destination processor number is destined to the second processor~ Thereafter, the 20 second processor supplies an interruption request to a control circuit operahle in accordance with firmware.
As a result, the second processor is put into a communicable state with the first processor.
An intercommunication network of the ~; 25 abDve-mentioned type is very effective to carry out intercommunication between processors, such as execution processor units, hoth of which belong to the same rank and which do not have a master-slave relationship.
..,,, ~ .
:
On the other hand, it often happens that similar intercommunication is carried out between an upper rank processor and a lower rank processor. In this event, a transmission end transmits a destination processor 5 number to a reception end like in the intercommunication between the execution processor units.
More specifically, when the upper rank processor and the lower rank processor act as the transmission and the reception ends, respectively, so as to transfer a 10 communication signal from the upper rank processor to the lower rank one, the upper rank processor supplies the lower rank processor with a destination processor number assigned to the lower rank processor. Thus, each upper rank processor is communicable with all the lower 15 rank processors by specifying the lower rank processors by the destination processor number.
To the contrary, when a communication request takes place at a lower r~nk processor which is operable as the transmission end, so as to transfer a data signal 20 sequence to be processed by the upper rank processors, the lower rank processor produces a destination processor number assigned to a selected one of the upper ~; rank processors to indicate the selected upper rank processor. ~lowever, it is to be noted that the data 25 signal sequence produced from the lower rank processor may be often processed in any one of the upper rank processors, if each of the upper rank processors can carry out processing in similar manners. In this event, ` 131768:~
it is not always desirable to specify a selected one of the upper rank processors by producing the destination processor number preassigned to the selected upper rank processor and to monitor a state of the selected upper 5 rank processor in the lower rank processor.
Specifically, each lower rank processor should always be conscious of a destination processor number communicable with each lower rank processor and must transmit such a destination processor number on transmission of the 10 transmission request. Therefore, each lower rank processor must be formed by the use of complexed hardware and firmware and should bear comparatively heavy load.
Summary of the Invention:
It is an object of this invention to provide an intercommunication network wherein each lower rank processor may be structured by the use of simple har~ware and firmware.
It is another object of this invention to 20 provide an interco~munication network of the type described, which can alleviate load ln each lower rank processor.
It is still another object of this invention to proYide an intercommunication network of the type 25 describedj wherein a transmission source may not be - conscious or a destination processor number.
An intercommunication network to which this invention is applicable i5 for use in carrying out , , , . .
communication among a plurality of processors in a multiprocessor system. The processors are connected to one another through a system bus and comprise first and second processors which have first and second 5 preassigned processor numbers assigned thereto, respectively, and which are operable as a transmission source for transmitting a transmission request and a destination end for receiving the transmission request, respectively. The first processor comprises producing 10 means for producing the first preassigned processor number assigned to the first processor and sending means for sending the first preassigned processor number as a transmission source number on transmission of the ; transmission request to the system bus. The second 15 processor comprises holding means for holding a communicable processor number corresponding to the first preassigned processor number and detecting means coupled to the system bus and the holding means for detecting whether or not the transmission source number indicates 20 the 1rst processor by checking correspondence between the transmission source number and the communicable processor number. The detecting means produces an interruption request signal when both the transmission source number and the communicabl~e processor number :
~ 25 indicate the first processor.
;
, Brief Description of the Drawing:
Fig. 1 is a block diagram of an ; intercommunication network to which this invention is appli cabl e;
Fig. 2 is a block diagram o~ an execution ~; processor unit according to a preferred embodiment of this invention;
Fig. 3 is a block diagram of an input/output processor communicable with the execution processor unit 10 illustrated in Fig~ 2; and Fig. 4 is a block diagram of a portion of the execution processor unit illustrated in Fig. 2.
Description of the Preferred Embodiment:
Referring to Fig. 1, an intercommunication 15 network to which this invention is applicable comprises zeroth through third execution processor units (EPU) 10, 11, 12, and 13, and æeroth through third input/output processors (IOP) 15, 16, 17, and 18 connected through a system bus 20 to one another and to the zeroth through 20 third execution processor units 10 to 13. In addition, a main memory unit 21 is also connected to the system `~ bus 20 to be used in common to the zeroth through third execution~processor units 10 to 13 and the zeroth through third input~output processors 15 to 18. The 25 zeroth through third execution processor units 10 to 13 are operable as upper rank~processors relative to the input/output processors 15 to 18, while the input/output processors 15 to 18, lower rank processors. At any ... .
. ~ .
:
: .- . - - .: .
. ~ - :
~ . ~ . - , .
:~ , :- - ..
~ 1 3 ~ 7683 rate, the execution processor units 10 to 13 and the input/output processors 15 to 18 form a multiprocessor system along with the system bus 20 and the main memory unit 21.
~erein, it is assumed that the zeroth through third execution processor units 10 to 13 of the upper rank are assigned with zeroth throu~h third primary processor numbers represented by binary numbers (0000), (0001), (0010), and (0011), respectively, while the 10 zeroth through third input/output processors 15 to 18 of the lower rank are assigned with zeroth through third :~ subsidiary processor numbers represented by (0100), (0101), ~0110), and (0111), respectively. In addition, each of the zeroth through third execution processor 15 units 10 to 13 is assumed to be similar in structure and operation to one another while each of the zeroth through third inputfoutput processors is assumed to be also similar in structure and operati.on to one another.
In the illustrated intercommunication network, 20 intercommunication is classified into first intercommunication between the execution processor units I0 to 13, second intercommunication from one of the : execution:processor units 10 to 13 to one of the npat/output processors 15 to I8, and third~
: 25 intercommunication from one of the inputjoutput , ~ :
:: processors 15 to 18 to one of the execution processor :: units 10 to 13. The first and the second lntercommunication may be carried out in a conventional ;-- -manner, as will become clear. ~owever, the thirdintercommunication will be carried out in a manner different from the conventional manner, as will later be described in detail. In addition, each of the execution 5 processor units 10 to 13 and the input/output processors 15 to 18 is communicable with the main memory unit 20 through the system bus 20.
Referring to Fig. 2 together with Fig. 1, the zeroth execution processor unit 10 is exemplified as a 10 representative of the zeroth through third execution processor units 10 to 13 and comprises a central processing unit 25 and a bus interface circuit 26 connected to the central processing unit 25 and the system bus 20. The illustrated system bus 20 comprises 15 a command bus 201 and an address/data bus 202 each of which is composed of a plurality of bus lines, although ; each bus is represented only ~y a single line~
In Fig. 2, it is assumed that the first intercommunication is carried out between the execution 20 processor units 10 to 13 and that the illustrated zeroth execution processor unit 10 is operable as a transmission end or a transmission source and communicates with a selected one of the other execution ~' ` ~ ~ processor units that may be called a destination or 25 reception end. The first intercommunication may be .
similar to that of a conventional network. More specifically, the zeroth processor unit 10 at first issues a communication or transmission request to ' '' ` ' identify the destination end or processor. The communication request is specified by a command signal CMD representative of a command and a specific one of the zeroth through third primary processor numbers that 5 is assigned to the destination end and that may be called a destination processor number DEST. In this event, the command indicates the first intercommunica-: tion~ In addition, the communication request also : indicates a source processor number SRC, namely, the 10 zeroth primary processor number (0000~. The commandsignal CMD, the destination processor number DEST, and the source processor number SRC are sent from the `: cen~ral processing unit 25 to a command register 31, a destination number register 32, and a source number 15 register 33 through a first internal line 36 to be kept in the respective registers 31, 32, and 33, respectively. The command signal CMD, the destination processor number DE~T, and the source processor number SRC are delivered from the oommand register 31, the 20 destination numher register 32, and the source number register 33 through a first driver 37 to the command bus 201. Thus, the communication request is sent to all of : the other processors through the command bus 201.
: When the illustrated zeroth execution processor ~, 25 unit 10 is operable as a destination end in the first intercommanication, a command signal CMD, a destination :~ processor number DEST, and a source processor number SRC
~ are received and held through the command bus 201 and a ~, .
lo 1 3 1 7683 first receiver 39 as a received command signal RCMD, a received destination processor number RDEST, and a received source processor number RSRC by a reception command register 41, a reception destination number 5 register 42, and a reception source number register 43, respectively. The received command signal RCMD is sent ~ from the reception command register 41 to a command ; decoder 45 through an internal command line 46.
If the received command signal RCMD is judged to 10 be representative of the first intercommunication, the command decoder 45 sends a logic "1" level signal to the central processing unit 25 through a second internal line 47. On the other hand, the received destination processor number RDEST is sent from the reception 15 destination number register 42 to the central procassing unit 25 through a third internal line 48. Supplied with the logic "1" level signal and the received destination processor number RDEST from the command decoder 45 and the reception destination number register 42, 20 respectively, the central processing unit 25 detects the first intercommunication and compares the received destination processor number RDEST with the zeroth primary processor number (0000) assigned to the zeroth execution processor unit 10. If the received 25 destination processor number RDEST is coincident with the zeroth primary processor number (0000), the central ~: processing unit 25 of the zeroth execution processor : unit 10 judges that the communication request in , , .
,, - .
,~ , " ~
question is destined to the zeroth execution processor unit 10. Such judgement may be made in a usual manner and will not be described any longer.
Thereafter, the first intercommunication is 5 carried out between the execution processor units 10 to 13 in the manner known in the art by transferring a sequence of data signals from one of the execution processor units 10 to 13 to another. On transferring the data signal sequence, the illustrated execution 10 processor unit 10 sets the data signal sequence from the central processing unit 25 to an address/data register 51. Subsequently, the data signal sequence is delivered from the address/data register 51 to the address/data bus 202 through the second driver 52. To the contrary, 15 a reception data signal sequence is sent from the address/data bus 202 to a reception address/data register 53 through a second receiver 54 on receiving the reception data signal sequence and is thereafter delivered to the central processing unit 25. Similar 20 data transfer is carried out in the second and the third intercommunication by the use of the address/data ; register 51 and the reception address/data register 53 also.
The address/data register 51, the second driver 25 52, the reception address/data register 53, and the second receiver 54 are used not only in the first through third intercommunication but also in a data trans~fer operation between each execution processor unit .
: :, '' ' , ~ '' 10 to 13 and the main memory unit 21 (Fig. 1). On such a data transfer operation between each execution processor unit 10 to 13 and the main memory unit 21, each of the address/data register 51 and the reception 5 address/data register 53 is loaded with an address signal and a data signal.
In the second intercommunication from each of the zeroth through third execution processor units 10 to 13 of the upper rank to either one of the zeroth through 10 third input/output processors 15 to 18 of the lower rank, each execution processor unit 10 to 13 supplies .~ :
the command bus 201 with the command signal CMD, the destination processor number DEST, and the source processor number SRC like in the first intercommunica-15 tion mentioned before. In this event, it is to be noted that the command signal CMD is indicative of the second intercommunication while the destination processor number DES~ specifies either one of the 2eroth through ~` third input/output processors 15 to 18.
;`; 20 In Figs. 1 and 2, let the third intercommunica-tion be carried out from either one of the zeroth through third input/output processors 15 to 18 to a selected one of the zeroth through third execution prooessor units 10 to 13 that may be assumed to be the :
'25 zeroth execution processor unit 10 without loss of ` g~nerality.
Temporarily referring to Fig. 3, each input/output processor 15 to 18 is similar in structure ' ::
, .
.
and operation to one another and is therefore exemplified by the zeroth input/output processor 15.
The zeroth input/output processor 15 comprises a subsidiary central processing unit 25' and a subsidiary 5 bus interface unit 26'. The subsidiary central processing unit 25' may be simple in structure and operation in comparison with a conventional one, as will become clear as the description proceeds.
The subsidiary bus interface unit 26' comprises 10 a command register 31', a destination processor number register 32', a source processor number register 33', a reception command register 41', a reception destination processor number register 42', and a reception source processor number register 43' which correspond to those 15 of Fig. 2, respectively. In addition, a command decoder 45' ~s also included in the subsidiary bus interface ~ unit 26' in correspondence to the command decoder 45 ; illustrated in Fig. 2. All of the above-mentioned elements are known in the art and are therefore not 20 shown in Fig. 2.
On carrying out the third intercommunication, the ~eroth input/output processor 15 supplies the command bus 201 with a command signal CMD and a source processor number SRC through a driver 37'. In this 25 case, the command signal CMD specifies the third :: :
` communication wh1le the source processor number SRC
specifies the zeroth subsidiary processor number (0100).
The command signal CMD and the source processor number ., :
SRC are delivered from the command register 31' and the source processor number register 33' through the driver 37' to the command bus 201. Accordingly, the source processor number register 33' is operable to produce the 5 source processor number S~C while the driver 37' is operable to send the source processor number SRC to the system bus 201 Moreover, a dummy number is also sent instead of the destination processor number DEST from the 10 destination processor number register 32 even in the third intercommunication. The dummy number is practically not used as the destination processor number DEST in a destination one of the execution processor units 10 to 13, as will become clear.
; 15 In Figs. 2 and 3, let predetermined relationships be present between the zeroth through third input/output processors 15 to 18 and the zeroth through third execution processor units 10 to 13 on carrying out the third intercommunication. In other 20 words, dependencies of the zeroth through third input/output processors 15 to 18 are predetermined for the zeroth through third execution processor units 10 to 13. For example, the zeroth input/output processor 15 is assumed to be communicable only with the zeroth 25 execution processor unit 10 in the third intercommunica-: tion. Such dependencies of the zeroth through third input~output processors 15 to 18 are monitored by the zeroth through third execution processor units 10 to 13.
. . .
' `
:
As a result, each of the zeroth through third executionprocessor units lO to 13 identifies the input/output processor which is communicable with each execution processor unit 10 to 13 in a manner to be described 5 later.
Now, it is assumed that the communication request is issued from the zeroth input/output processor unit 15 to the zeroth execution processor unit lO to carry out the third intercommunication. In this event, lO the zeroth input/output processor 15 acts as the transmission end or transmission source while the zeroth execution processor unit lO acts as the destination or reception end. The communication request in the third intercommunication is specified by the command signal 15 CMD representative of the third intercommunication and the souxce processor number SRC, namely, (0100) representative of the zeroth input/output processor 15.
The command signal CMD and the source processor number SRC are sent from the command register 31' and the 20 source processor number register 33' of the zeroth input/output processor 15 to the command bus 201. As :
mentioned before, the dummy number is also sent from the : destination processor number register 32' to the command : bus 201.
25 :~ ~; In Fig. 2, the command:signal CMD and the source ~processor number SRC~are delivered from the command bus : 201 to each of the zeroth through third execution processor units lO to 13. In the zeroth execution i ,~ s, .. - . , - - :
, ', processor unit 10, the command signal CMD and the source processor number SRC are kept as the received command signal RCMD and the received source processor number RSRC in the reception command register 41 and the 5 reception source number register 43, respectively. The ~ummy number is also held as the received destination processor number RDEST in the reception destination number register 42.
The received command signal RCMD is sent from lO the reception command register 41 to the command decoder 46. When the command decoder 46 judges that the received command signal RCMD indicates the third intercommunication, the command decoder 46 produces an indication signal of the logic "1" level representative 15 of the third intercommunication.
Referring to Fig. 4 together with Fig. 2, the indication signal is sent from the command decoder 45 through a fourth internal line 64 to a request judgement ;clrcuit 65. The request judgement circuit 65 is 20 supplied with the received source processor number RSRC
from the reception source number register 43 through a fifth internal line 68. Furthermore, the illustrated bus interface circuit 26 c~omprises an input/output processor number (IOPN) register 71 connected to the 25 central processing unit 25 through a sixth internal line .
~72.~ The IOPN register 71 is loaded~under control of the :~: central processing unit 25 wi~h a communicable processor number which corresponds to one of the input/output '~; :
. .
.
, :.:
~ 1 31 7683 processors 15 to 18 that is communicable with the zeroth execution processor unit 10 and that is determined by the above-mentioned dependencies. ~herefore, the IOPN
register 71 is operable to hold the communicable 5 processor number and may be called a holding register for holding the communicable processor number.
The communicable processor number specifies each input/output processor by a bit position of the logic "1" level assigned to each of the input/output 10 processors 15 to 18. In the example being illustrated, ~he communicable processor number is represented by four bits arranged from a zeroth or most significant bit to a third or least significant bit. The zeroth through third bits are determined for the zeroth through third 15 input/output processors 15 to 18, respectively. As mentioned before, the zeroth execution processor unit 10 is communicable with the zeroth input/output processor lS and the communicable processor number must therefore specify the æeroth input/output processor 15. Under the ~; 20 circumstances, the communicable processor number in the zeroth execution processor unit 10 is represented by (1000) having the zeroth bit of the logic "1" level.
.
`~ ~ In Fig. 4, the IOPN register 71 is composed of zeroth through third bit registers 710 to 713 loaded ~;~ 25 with~the zeroth through third bits tl000) of the ;~ communicable processor number, respectively. Likewise, ~ the reception source processor number register 43 is -~ composed of zeroth through third reception registers 430 . , :
:
:: :
.
18 ~317683 to 433 which are loaded with the received source processor number RSRC represented by the binary eode of ~0100), respectively. Under the circumstances, the request judgement circuit 65 judges or checks whether 5 the received source processor number RSRC indicates the zeroth input/output processor 15 specified by the communicable processor number (1000) of the zeroth exeeution processor unit 10. The request judgement : cireuit 65 produces an interruption request signal INT
10 when the received source processor number RSRC indieates the zeroth input/output processor 15. The interruption request signal INT is held in an interruption tINT) register 75 and is thereafter sent to the central proeessing unit 25 through a seventh internal line 77, 15 as shown in Fig. 2.
In this eonneetion, a eombination of the reeeption souree proeessor number register 43 and the request judgement eircuit 65 may be called a detection eireuit for deteeting whether or not the reeeived source 20 processor number RSRC indicates the zeroth input/output : processor 15 communieable with the zeroth execution processor unit 10.
More particularly, the request judgement circuit 65 il:lustrated in Fig. 4 comprises zeroth through third 25 AND gates 80 to 83 eonneeted to the zeroth through third bit registers 710 to 713, respeetively, an OR gate 84 : : eonneeted to the zeroth through third AND gates 80 to 83, and an output AND gate 85 connected to the OR gate ,', 19 ~ 31 7683 84 and the command decoder 45 through the fourth internal line 64. On the other hand, the zeroth reception register 430 of the reception source processor number register 43 is connected to the output AND gate 5 85 through a first inverter 86 while the first reception register 431 is connected direct to the output AND gate 85. In addition, the second reception register 432 is connected to the second and the third AND gates 82 and 83 directly and also to the zeroth and the first AND
10 gate~ 80 and 81 through a second inverter 87. The third ; reception register 433 is connected to the first and the third A~D gates 81 and 83 directly and also to the zeroth and the second AND gates 80 and 82 through a third inverter 88.
With this structure, let the communicable processor number and the received source processor number RSRC be loaded with (1000) and (0100), ~ respectively. In this case, the zeroth AND gate 80 - alone is opened to supply the logic "1" level signal to 20 the output AND gate 85 through the OR gate 84. Thus, the received source processor number RSRC is checked by the~zeroth through third AND gates 80 to 83 and the second and the third lnverters 87 and 88, all of which may be called a checking circuit.
:: 25 ~ Inasmuch as the output AND gate 85 is supplied with the indication signal of the loglc "1" level from : ` :
the command decoder 45 and with the logic "1" levels :from the zeroth reception register 430 through the first , ~ :
,;, inverter 86 and from the first reception register 431, the output AND gate 85 is opened to produce the interruption request signal INT. The interruption request signal INT is sent to the central processing 5 unit 25 through khe interruption register 75.
Responsive to the interruption request signal INT, the central processing unit 25 recognizes that the communication request in question is sent from the zeroth input/output processor 15 determined for the 10 zeroth execution processor unit 10 by the above-mentioned dependencies.
; ~Thereafter, the zeroth input/output processor 15 transfers a sequence of data signals through the address/data but 202 to the zeroth execution processor 15 unit 10. The data signal sequence is received by the central processing unit 25 of the zeroth execution `~ processor unit 10 through the second receiver 54 and the reception address/data register 53.
In Fi~. 4, the communlcable processor number of 20 ~1000) may be changed to another under control of the central processing unit 25 to communicate with another one of the input/output processors when the input/output processors increase or decreasë in number. For example, ,:
~ when the communicable processor number is changed to -~ ~ 25;(0100~, the interruption request signal INT of the logic "1" leveI is produced from the output AND gate 85 on reception of the received source processor number RSRC
represented by (0101~. This shows that the illustrated , ~, .
~: .
.
~` 1317683 execution processor unit 10 is communicable with the first input~output processor 16 (Fig. lj. Likewise, when the communicable processor number and the received source processor number RSRC be equal to (0010) and 5 (01103, respectively, the second AND gate 82 is opened to produce the interruption request signal INT through the output AND gate 85. In addition, the request judgement circuit 65 illustrated in Fig. 3 can produce the interruption request signal INT when the 10 communicable processor number and the received source processor number RSRC are equal to (0001) and (0111), respectively.
With this structure, no destination processor ; number DEST may be produced from each input/output 15 processor 15 to 18 on the third communication, although description has been made on the assumption that the destination processor number is sent from each input/output processor as a dummy number. Accordingly, it is unnecessary to monitor or administrate the primary 20 processor numbers of the execution processor units.
; This means that each input/output processor may not be aware or conscious of the primary processor numbers.
This enables alleviation of a burden imposed on hardware or ~irmware of each input/output processor.
While this invention has thus far been described . .
in conjunction with a preferred embodiment thereof, it ill readily be possible for those skilled in the art to ~ .
~ ~ put this invention into practice in various other ~ I
, ,~, ~.1. . . ' . ;
22 1 ~1 7683 manners. For example, the upper and the lower rank processors may not be restricted to the execution processor units and the input/output processors. In addition, this invention may be applied to inter-S communication between processors of the same rank. Nodu~ny number may be sent ~rom the transmission source to the reception end.
;' .
~'~
~i :
;
'
Claims (4)
1. An intercommunication network for use in carrying out communication among a plurality of processors, said processors being connected to one another through a system bus and comprising first and second processors which have first and second preassigned processor numbers, respectively, and which are operable as a transmission source on transmission of a transmission request and as a destination end for receiving said transmission request, respectively, wherein said first processor comprises:
producing means for producing said first preassigned processor number assigned to said first processor; and sending means coupled to said producing means for sending said first preassigned processor number as a transmission source number to said transmission bus on transmission of said transmission request;
said second processor comprising:
holding means for holding a communicable processor number corresponding to said first preassigned processor number; and detecting means coupled to said system bus and said holding means for detecting whether or not said transmission source number indicates said first processor by checking correspondence between said transmission source number and said communicable (Claim 1 continued) processor number, said detecting means producing an interruption request signal when both said transmission source number and said communicable processor number indicate said first processor.
producing means for producing said first preassigned processor number assigned to said first processor; and sending means coupled to said producing means for sending said first preassigned processor number as a transmission source number to said transmission bus on transmission of said transmission request;
said second processor comprising:
holding means for holding a communicable processor number corresponding to said first preassigned processor number; and detecting means coupled to said system bus and said holding means for detecting whether or not said transmission source number indicates said first processor by checking correspondence between said transmission source number and said communicable (Claim 1 continued) processor number, said detecting means producing an interruption request signal when both said transmission source number and said communicable processor number indicate said first processor.
2. An intercommunication network as claimed in Claim 1, wherein said first and said second processors are an input/output processor and an execution processor unit, respectively.
3. An intercommunication network as claimed in Claim 1, wherein said transmission source number is represented by a binary code of a predetermined number of bits while said communicable processor number has a logic "1" level at a bit position preassigned to said first processor and is different from said binary code.
4. An intercommunication network as claimed in Claim 3, wherein said holding means holds said communicable processor number having the logic "1" level at said bit position preassigned to said first processor;
said detecting means comprises:
register means for retaining said binary code representative of said transmission source number;
checking means coupled to said holding means and said register means for checking whether or not both the communicable processor number and said binary code of the transmission source number specify said first processor; and (Claim 4 continued) signal producing means coupled to said checking means for producing said interruption request signal when said first processor is specified by both said communicable processor number and said binary code of the transmission source number.
said detecting means comprises:
register means for retaining said binary code representative of said transmission source number;
checking means coupled to said holding means and said register means for checking whether or not both the communicable processor number and said binary code of the transmission source number specify said first processor; and (Claim 4 continued) signal producing means coupled to said checking means for producing said interruption request signal when said first processor is specified by both said communicable processor number and said binary code of the transmission source number.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP135725/1988 | 1988-06-03 | ||
| JP63135725A JPH0731666B2 (en) | 1988-06-03 | 1988-06-03 | Inter-processor communication method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1317683C true CA1317683C (en) | 1993-05-11 |
Family
ID=15158423
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000601613A Expired - Fee Related CA1317683C (en) | 1988-06-03 | 1989-06-02 | Intercommunication network capable of carrying out intercommunication without transmission of a destination number from a transmission source |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US5113495A (en) |
| JP (1) | JPH0731666B2 (en) |
| CA (1) | CA1317683C (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2837877B2 (en) * | 1989-07-04 | 1998-12-16 | キヤノン株式会社 | Communication device and communication method |
| FR2661024B1 (en) * | 1990-04-17 | 1994-02-04 | Somfy | INSTALLATION COMPRISING SEVERAL RECEIVING POINTS AND SEVERAL TRANSMITTING POINTS. |
| US5392399A (en) * | 1992-05-18 | 1995-02-21 | 3Com Corporation | Bridge system for selectively routing frame with ordering parameter identifying ordering of identifiers only based upon its source identifier |
| CN1047906C (en) * | 1993-01-29 | 1999-12-29 | 波音公司 | Call completion system and method |
| US5526489A (en) * | 1993-03-19 | 1996-06-11 | 3Com Corporation | System for reverse address resolution for remote network device independent of its physical address |
| US5875306A (en) * | 1996-10-01 | 1999-02-23 | International Business Machines Corporation | Reconfiguring computer resources in a distributed computer enterprise environment |
| JP2000341302A (en) * | 1999-05-27 | 2000-12-08 | Sony Corp | Electronic device |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6041786B2 (en) * | 1977-12-05 | 1985-09-18 | 日本電気株式会社 | interrupt control system |
| US4296466A (en) * | 1978-01-23 | 1981-10-20 | Data General Corporation | Data processing system including a separate input/output processor with micro-interrupt request apparatus |
| CH632365A5 (en) * | 1978-01-30 | 1982-09-30 | Patelhold Patentverwertung | DATA EXCHANGE PROCESS BETWEEN MULTIPLE PARTNERS. |
| US4223380A (en) * | 1978-04-06 | 1980-09-16 | Ncr Corporation | Distributed multiprocessor communication system |
| US4667287A (en) * | 1982-10-28 | 1987-05-19 | Tandem Computers Incorporated | Multiprocessor multisystem communications network |
| SE435975B (en) * | 1983-03-18 | 1984-10-29 | Ellemtel Utvecklings Ab | DEVICE IN A COMPUTER-CONTROLLED TELECOMMUNICATION SYSTEM FOR TRANSFERING DATA INFORMATION BETWEEN A REGIONAL PROCESSOR AND A CENTRAL PROCESSOR BY A COST SYSTEM |
| US4660141A (en) * | 1983-12-06 | 1987-04-21 | Tri Sigma Corporation | Self configuring computer network with automatic bus exchange of module identification numbers and processor assigned module numbers |
| JPH0670787B2 (en) * | 1984-06-29 | 1994-09-07 | 富士通株式会社 | Command transfer control system between processors |
| GB2169174B (en) * | 1984-11-28 | 1989-06-01 | Canon Kk | Data communication apparatus |
| US4912627A (en) * | 1985-08-14 | 1990-03-27 | Apple Computer, Inc. | Method for storing a second number as a command address of a first peripheral device and a third number as a command address of a second peripheral device |
| US4730251A (en) * | 1985-10-28 | 1988-03-08 | International Business Machines Corporation | Automatic I/O address assignment |
| JPH06103481B2 (en) * | 1985-11-15 | 1994-12-14 | 株式会社日立製作所 | Program loading method |
| US4953072A (en) * | 1987-05-01 | 1990-08-28 | Digital Equipment Corporation | Node for servicing interrupt request messages on a pended bus |
| US4876664A (en) * | 1987-08-26 | 1989-10-24 | Allen-Bradley Company, Inc. | Programmable controller with a dual intermodule message system |
| US4860003A (en) * | 1988-05-27 | 1989-08-22 | Motorola, Inc. | Communication system having a packet structure field |
| US4894826A (en) * | 1989-01-30 | 1990-01-16 | Honeywell, Inc. | Message generating communication apparatus having a message preamble format allowing parts of certain messages to be ignored |
-
1988
- 1988-06-03 JP JP63135725A patent/JPH0731666B2/en not_active Expired - Lifetime
-
1989
- 1989-06-02 CA CA000601613A patent/CA1317683C/en not_active Expired - Fee Related
- 1989-06-05 US US07/361,559 patent/US5113495A/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0731666B2 (en) | 1995-04-10 |
| JPH01305460A (en) | 1989-12-08 |
| US5113495A (en) | 1992-05-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5129089A (en) | Distributed interlock apparatus and distributed interlock management method | |
| US5025369A (en) | Computer system | |
| EP0063334B1 (en) | Data processing apparatus for a multiprocessor system | |
| US5497501A (en) | DMA controller using a predetermined number of transfers per request | |
| US4999768A (en) | Data transfer control units each of which comprises processors and dual-part memory | |
| KR920001552B1 (en) | Local area network system with a multi-computer system coupled method and method for controlling the same | |
| CA1221173A (en) | Microcomputer system with bus control means for peripheral processing devices | |
| GB1518565A (en) | Data processing system | |
| CA1317683C (en) | Intercommunication network capable of carrying out intercommunication without transmission of a destination number from a transmission source | |
| CA1244118A (en) | Distributed control type electronic switching system | |
| US5140691A (en) | Adapter-bus switch for improving the availability of a control unit | |
| US4958271A (en) | Transfer control equipment | |
| US4977499A (en) | Method and apparatus for commanding operations on a computer network | |
| EP0370780B1 (en) | A communication command control system between CPUs | |
| US4802087A (en) | Multiprocessor level change synchronization apparatus | |
| EP0180299B1 (en) | Error detection system for a data processing apparatus | |
| US6938078B1 (en) | Data processing apparatus and data processing method | |
| JP2003140704A (en) | Process controller | |
| JP3086245B2 (en) | Other system access designation device | |
| JPS6055752A (en) | Packet processing system | |
| JPS61249162A (en) | Input device | |
| JPH05300161A (en) | Fddi connection time monitor system | |
| JPS6174052A (en) | Data processing device | |
| JP2573790B2 (en) | Transfer control device | |
| JPS5842491B2 (en) | Fault recognition method in multiprocessor system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKLA | Lapsed |