CA1292808C - Apparatus and method for interprocessor communication - Google Patents
Apparatus and method for interprocessor communicationInfo
- Publication number
- CA1292808C CA1292808C CA000538417A CA538417A CA1292808C CA 1292808 C CA1292808 C CA 1292808C CA 000538417 A CA000538417 A CA 000538417A CA 538417 A CA538417 A CA 538417A CA 1292808 C CA1292808 C CA 1292808C
- Authority
- CA
- Canada
- Prior art keywords
- processor
- signal group
- command
- processing unit
- execution apparatus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
Abstract
ABSTRACT
In order to provide communication between two processors in a data processing unit, a target processor includes apparatus that can store data signal groups from a source processor. Having stored a data signal group from the source processor, the target processor notifies the source processor of the receipt of the data signal group. In response to the presence of the stored data signal group, the target processor executes a command identified by the transferred data signal group. The source processor at a preselected time, executes an instruction to determine if the command designated by the data signal group stored in the target processor has been executed. The commands specified by the transferred data signal groups can be executed under hardware control by the target processor in a relatively short time immediately following completion of the instruction in execution in the target processor at the time of the transfer of the data signal group.
The interprocessor communication has only a minor impact on the performance of the source processor and the target processor because of the command implementation by apparatus.
In order to provide communication between two processors in a data processing unit, a target processor includes apparatus that can store data signal groups from a source processor. Having stored a data signal group from the source processor, the target processor notifies the source processor of the receipt of the data signal group. In response to the presence of the stored data signal group, the target processor executes a command identified by the transferred data signal group. The source processor at a preselected time, executes an instruction to determine if the command designated by the data signal group stored in the target processor has been executed. The commands specified by the transferred data signal groups can be executed under hardware control by the target processor in a relatively short time immediately following completion of the instruction in execution in the target processor at the time of the transfer of the data signal group.
The interprocessor communication has only a minor impact on the performance of the source processor and the target processor because of the command implementation by apparatus.
Description
l~,<.'j~O~
BACKGROUND OF THE_I~VE~TIO~
1. Field of the Invention This invention relates generally to data processing systems and, more particularly, to the communication between componencs of the data processing svstem, the components each having signal processing capahility.
BACKGROUND OF THE_I~VE~TIO~
1. Field of the Invention This invention relates generally to data processing systems and, more particularly, to the communication between componencs of the data processing svstem, the components each having signal processing capahility.
2. Discussion of the Related Art As the complexity of the modern data processing systems has increased, the problems involved with the communication between processing components has similarly increased. ~owever, the need for ehis interprocessor communication has expanded. In the multiprocessor and muLtiprogrammed data processing environment, the exchange of information or the sharin8 of processing activity among system components is frequently required and the coordlnation of these activities results in the requirement for a protocol to provide the information between the processors. For example, a processor can have a content addressable memory associated therewith to facilitate address translation. In the multiprocessor system, the contents of the content addressable memory associated with each processor 0~
cannot be inconsistent. Inconsistencies can result in data processing system errors. When a first (source) processor performs a process that results in the change or invalidation of the contents of the content addressable memory associated with the first processor, then the contents of a content addressable memory of the second (target) processor equivalent to the changed or invalidated memory contents of the ~irst processor must be similarly changed or invalidated.
rn order to provide this communication, the related art provides a potential tar8et processor with storage apparatus, wherein a source processor can store signals indicative o the requirement for communication with the target processor by the source processor. The source proceqsor stores signals representin~ the communication desired between the two processors in a predetermined location in main memory, typically referred to as the processor mallbox, and transfers signals to the storage apparatus in the tar8et processor. The target processor, according to a prearranged protocol, reviews the storage apparatus, and when a signal is found in the storage apparatus, the target processor retrieves the contents of a location in its mailbox.
The contents of the mailbox identify the activity that the source processor is requesting the target processor to perform.
This procedure for interprocessor communication may have a significant impact on the performance. The tar8et processor must first identify the presence of a a communication request, must stop the current processing activity and call upon a software procedure to retrieve the contents of the mai.lbox, interpret the contents of the stored request and perform the activity indicated bv the mailbox flle contents. In addition, the source processor may suspend other activity in order to determine whether che activity requested by the source processor has been performed.
A need has therefore been felt for apparatus and method that would provide for ineerprocessor communication by min:imizin~ the impact on system performance, Obiects of the Invention It is therefore an object of the present invention to provide an improved data processing system, It is yet another object of the present invention to provide apparatus and method for communication between processing components of the data processing system.
It is still another object of the present invention to permit execution of a command generated ~ 2801!3 I
in a first processor by a second processor without intervention of a software program in the second processor.
It is a still further object of the present invention to provide for interprocessor communication in a data processing system that reduces the impact of the communication on the performance of the data processing system.
Summarv of the Invention The aforementioned and other objects are accomplished, according to the present invention, by providing apparatus in a target processor that can receive and store a command transmitted by a source proces~sor via a system bus. The source processor lS receive~ a si~naL from the target processor when the COItlmalltl i'9 store(i ln the ~s~orage apparatus. ~When the command i-. seore(l in the ~-lppat.ltus of the target proc:essor, a stdtus signal is genérated in the target processor. When the tar8et processor completes execution of the current instruction, the status signal causes ;he command stored in the target processor to be executed. ~fter execution of the command. the target processor continues the instruction sequence in progress at the time that the command was entered in the target processor apparatus. The transferred command, in the preferred embodiment, can result in two types of activity in 2~0~3 the tarqet processor. The first type of activity is a modification of ~on~rol da~a stored in the target pro~essor, i.e.
modification of data relating to address translation. The second type of activity is the performance of a function requested by the source processor, i.e. execution of the request stored in the target processor mailbox. The source processor can examine the main memory location, altered as a result of the data command transmitted to the target processor, to ascertain that the command has been executed. These and other features of the present lnventlon wlll become apparent upon readlng of the discussion herein along wlth the drawings.
In accordance wlth the present lnventlon, there ls provided a processor for use ln a data processlng system of the type ln whlch a plurallty of processors are coupled to a system bues for lnterprocessor communlcatlon of eslgnal groups along sald bus; sald processor characterlzed by comprlsing- lnstructlon executlon apparatus for proce~ssing of data slgnal groups ln sald procesesor ln reesponse to lnstructlon Esignal groupsJ an lnterface unit for recelving and storlng eslgnal yroups from esald bus whlch slgnal groups lnclude the bu~s addres~s of sald processor and a command slgnal groups and command executlon apparatus coupled to a portlon of sald instructlon executlon apparatus and responslve to sald command signal group stored by sald lnterface unit for performlng an operatlon on sald coupled portlon of said lnstruction execution apparatus, said operation being determined by said command slgnal group.
In accordance wlth another aspect of the invention there is provided a method for permitting a second central processing 1~92~0B
5a 72434-48 unit of a data processing system to control the operation of a first central processing unit, said method comprising the steps of: identifying each of a plurality of preestablished conditions in said second central processing unit; generating a command signal group in said second central processing unit in response to each one of said preestablished conditions, said command slgnal group determined by said one pre-established conditlon; applying said command signal group and an associated address slgnal group to a system bus, said address signal group identifying said first central processing unit; retrievlng said command slgnal group form said system bus by said first central processlng unit in response to said address slgnal group; storing said command signal group in a first central processing unit register; suspendlng operation of said first central processing unlt ln response to storage of sald selected signal group in said register; and performing a predetermined operatlon on a selected portion of said first central proce~sing unlt in response to said command slgnal group by apparatus coupled between said first processing unlt register and said selected portions of said first central processing unit, said predetermined operatlon being determined by sald command signal group.
Brief Descrlption of the Drawinqs Figure 1 is a block diagram of a data processing system capable of utilizing the present invention.
Figure 2 is a block diagram of a processor of a data processing system illustrating components used in the implementation of the present invention according to the preferred embodlment.
1292~01!3 5b 72434-48 Figure 3 is a flow diagram illustrating the communication between processors according to the present invention.
Figure 4 is a dlagram illustrating the format of the data signal groups assoclated with the transferred command that are transferred between the l~Z~)8 source processor and the target processor on the address lines of the system bus.
Figure 5a, 5b and 5c illustrate the format of data signal groups associated ~ith the transferred command that are transferred on the data lines of the system bus.
Figure 6 illustrates the organization of main memory locations associated with each processor that supports the operation of the present invention.
10Figure 7 is a diagram illustrating the execution of the transferred command in relation to other data processing system activity.
Description of the Preferred Embodiment l. Detailed Description of the FiRures 15~eferring now to ~ig. 1, a dar.a processing system capable of advanta~eou~Ly u~ in~ (:he present invencion is show1l. rhe dat.l pr()cessir1g system includes at least two processors (i11ustrated hy processor 10 and processor 1l, a main memory unit 15, at least one peripheral interface units (illustrated by peripheral unit 12 and peripheral unit 13) and a system bus 19. In the data processing system illustrated in Figure l, the main memory unit stores the data signal groups to be manipulated bv the processors. During initialization of the system, The storage space on the main memory unit 15 is divided into a multiplicity of regions, each storing 1292~308 preidentified logic signals. In addition, the main memory unit has certain regions reserved for control data, the control data being accessible to the processors. The use of a common main memory unit for a plurality of processors is described as a "tightly coupled" system.
Referring next to gigure 2, components of the processors relevant to the present invention are shown. The processor includes a system bus interface 1~ unit '1 that senses all the data (logic) signal groups applied to the system bus. The logic signals applied to the system bus include information designating the target component to which an associated data signal group is to be applied within the tar8et processor. The system bus interfsce unit 21 includes the apparatus tor identifying when signals applied to the system bus 19 are to be transmit~ed to the processor with which the interface unit is associated. The system bus interface unit 21 aLso includes apparatus Eor applying a signal, communicating to the source processor that the target processor has received the logic signals, on line 29 to the system bus 19. This signal is generally referred to as the "acknowledge" signal. The data signals from the source processor are stored in a storage apparatus 22. Associated with the storage apparatus 22 is a storage cell 24, such as a register ~2~2~;08 cell, that causes a signal to be applied within the target processor indicating that a data signal group is stored in the storage apparatus 22. The applied signal further indicates to the target processor that signal group stored in the register 22 is a command.
The signals in the storage apparatus 22 are applied to decode logic 24. The signal from storage cell 23 is applied to switch 27. The output signals from switch 27 are applied to the decode logic 24 and to the processor instruction register 25. Output signals from the decode logic 24 are applied to a content addressable memory 26 and to interrupt apparatus 28. The interrupt apparatus 28 applies signals to the system bus interface unit 21 and the lS decode logic Z4 applies signals to the system interface unit 21.
Referrin8 once a8~in to ~igure 2, the processor i9 shown as havillg a content addressable memory included therein. In the preferred embodiment, each processor includes two content addressable memories, one content addressable memory associated with data segments and one content addressable memory associated with data pages. The content addressable memories are used to translate a symbolic address used by a program executing in a processor to a physical address designating a location in the main memory unit. An appropriate 12~21~08 command in storage apparatus 22 can invalidate a selected location or all the locations in a content addressable memory.
Referring next to Fig. 3, a flow diagram illustrating communication between two processors is shown. After the source processor identifies the requirement to communicate with the target processor in step 301, a software lock is set in the operatin~
system to prevent simul~aneous communication b~ two processors in step 302. The source processor, for selected interprocessor communication sequences, prepares and stores data ~iles in a predetermined main memorv unit location, i.e. the tar8et processor mailbox, in step 303. rn step 304, the source processor executes the interprocessor instruction, the instruction then transfers the command to the tar8et processor in seep 305. ln step 305, the tar8et processor 9cknowledges the receipt of the command after the transfer has taken place. If the acknowledge signal is noe recelved, in step 307 the source processor once again attempts to transfer the data signal group to the target processor via step 305. When the transfer of the data signal group is successful, then the source processor continues with the curren~ instruction sequence execution. This instruction sequence execution continues until a preselected activity and then performs the testing of 1~92~10~
the indicia in step 310. The target processor, after completion of the execution of the current instruction or instruction sequence, executes the command in step 308 identified by the transferred data signal group. In step 309, the target processor establishes an indicia available to the source processor indicating completion of the activitv, i.e.
execution of the transferred command. .~t a later period of time, the source processor tests, in step 310, the indicia set by the target processor to determine iE the command designated by the transferred data signal group has been executed.
Reterring ne.Yt to Fig. 4, the format ot ~he portion of the command transferred from the source processor to the targe~: processor on the a(ldress lines of the system bus is shown. The logic signal group is 16 bits in length. Bits 0 through 9 specify the identification number of the target processor.
Bits 10 through 15 specify the function to be performed by the target processor. These functions include (0) flush the se8ment content addressable memory, (I) flush an entry in the segment content addressable memory, (2) flush the page content addressable memory, (3) set activity flag and place an entry in rhe interrupt queue and (4) flush an entry in the page content addressable memory.
Referring to Figure 5a, 5b, and 5c, 12~2~308 portions of the transferred command transferred over the data llnes of the system bus is shown. For functions 0 and 2, wherein the entire contents of a content addressable memory are invalidated, no additional Information is needed. 1~hen the function reques~ed by the source processor is (1) or (4), i.e.
flush an entry in the segment or page content addressable memory, then the format o~ the second data Sl~nal group is shown in Fig 5a and 5c respecti-e1~.. In Fi.g. 5a, data signal group, the bits in positions 2 through 11 specifv the particu:lar entry in the segment content addressable memory to be flushed. I`he data slgna1s trans~erred in FiR. 5a and 5c are ava~lab1e to the source processor in so~tware visibLe registers. In Fig. 5c, the designation of the particuLar page descriptor requires ~wo signal groups, the page descripcor identified by positions 4 through 15 in the first si~nal group and positions 16 through 22 in the second data group. As shown in Fig~ 5b, when the function code (3) is transferred, in the associated signal group transferred over the da~a lines of the system bus, bits 0 through 9 identify the source processor while bits 10 through 15 designate the interrupt level. The interface uni~
includes apparatus to interpret the function code to determine if the data lines have logic signals applied thereto that are relevant to the process 2~0~3 identified by the function code.
Referring next to Fig. 6, an organization of the memory locations in main memory associated with each processor supporting the present invention is shown. At the time of initialization of the system, the operaring svstem allocates a group of memory locations 61 to a selected processor. The memory locations associated with each processor has allocated therein particular memory locations reserved ~or specified tvpe data. ~n particular, a plurality ot locations 62 are reserved for activity flags. Simi~arly, a plurality of locations in the group of main memorv locations associated with each processor are reserved as the mail box and store messages and requests from other processors.
Referring to Fig. 7, a diagram illustrating the opera~ion o~ the present invention is shown. The targee processor executes a series of instructions 71, i.e. by loading the instruction register. At some point, the source processor executes the interprocessor instruction and transfers command 72 to the tar8et processor. The completion of the command transfer will typically occur during the execution of a current instruction. After the current instruction has been executed, the target processor will execute the command 73 stored in storage apparatus 22. The target processor will then 1~2~10~3 execute the next instruction in the sequence.
2. Operation of the Preferred Embodiment In the present invention, interprocessor commands that can be executed by apparatus (hardware) are chosen. In addition, the interprocessor commands are chosen so that if the apparatus for non-software execurion is not available, the apparatus can be added without excessive additional design comple.~it~
and without unacceptable additionaL appararus~ The content addressable memory location invalidation and a portion of an interrupt command are two interprocessor commands implemented in the pre~erred embodiment, however other commands can be si~nilarly processed by the present invention.
The present invention permits a greater independerlce of opera~ion between ~he processors.
This independence is achieved by selecting certain activity for use with the present invention. In particular, the preferred embodiment involves two types of interprocessor communication. In the first type of communication, the source processor informs the target processor that a certain address identified by the contents of a content addressable memory is no longer valid. The command transferred to the target processor then invalidates the address(es) designated by the source processor in the content addressable memory.
Z~08 -14~
In the second type of communication, the source processor requires that the target processor gain access to data signal groups in the processor mailbox, for example, to execute a routine or program under the control of the source processor. In this communication, the source processor transfers the request to the target processor mailbox for use by the target processor. The command transferred to the target processor in this second type ot`
communication indicates the type of activity, i.e.
the data groups in the main memory to be used by the target processor, and the priority level of the activity requested by the source processor. Ti)e designation of the priority level provides for an orderly e.YeCUtiolt of activity by the tar8et processor and eliminates inappropriate~ interruption of activity by a lower level process.
In either type of comnlunication, apparatus has been added to the processors so the transferred command can be executed by the tar8et processor without software intervention. The presence of a signal in the storage cell 23 prevents the instruction register from executing the next instruction until the command stored in storage apparatus 22 has been executed. appropriate decoding apparatus has been added to the processors so that a content addressable memory can have either a selected 1~2~() !3 or the entire contents invalidated. With respect to the command related to the request stored in the processor mail box, the interrupt apparatus 28 tests the priority of the currently executing program S against the priorl;y of the request in the mailbox while simultaneous loading appropriate activitv flags and prioritv designation in the main memory location group associated with the target processor. When the request prioritv is higher than the currentl-executinx pro~rum, then a tu11 interrupt is e~ecutedby the processor and the request in the mailbox will be executed ne~t by the processor If the priority of the request is lower tharl the priority of the currently e~ecuting program, then the currently executin~r~ program will continue in execution.
When ~the source processor origin.1l~y transfers the data signal group, the rteceipt of the "acknowledge" signal permits the source processor to execute other inseructions. According to the prior art, the operation of the source processor would be interrupted until confirmation that the requested operation was completed. In the current invention, the source processor is free to execute other instructions after the identification of the "acknowledge" signal. The source processor does examine the contents of selected locations in the main memory to insure that the requested operation ~2 ~0 has in fact taken place. But this examination can take place after other processing by the source processor, permitting more intdependent operation.
After execution of the invalidation of the contents of a location or locations in a content addressable memory, the command provides that an appropriate activity flag be set in a predefined location in main memory in order that the source processor can insure that the command has been e.Yecuted. ~'ith respect to the command related to the processor interrupt, the command requires that activLtv flags, processor identification numbers and priority levels be stored in selected predefined main memory locations. The source processor can interrogate those locations to determine in the command has been executed, so no indepenclent ~ignal neetd be set in che main memory to i.ndit.ate completion of this c~mlnand.
I~ will be clear that the apparatus added 2~ to implement the comlnand ~rans~erred by tlte interprocessor instruction can be used by any processor in execution of internal activity, i.e.
invalidating content addressable rnemory contents.
Although the invention has been described in relation to the communication between processors, it will be clear that in the modern data processing systems many system components are being designed with logic 2~0~3 signal manipulation capability. The technique described can be used for improved communication between any of the system components with appropriate processing capability.
The foregoing description is intended to illustrate the operation of the preferred embodiment and is not meant to limit the scope of the invention.
The scope of the invention is to be limited only by the ~ollowing claims. From the ~oregoing description, many variations would be apparent to one skilled In the art that would yet be encompassed by the spirit and scope of the invention.
cannot be inconsistent. Inconsistencies can result in data processing system errors. When a first (source) processor performs a process that results in the change or invalidation of the contents of the content addressable memory associated with the first processor, then the contents of a content addressable memory of the second (target) processor equivalent to the changed or invalidated memory contents of the ~irst processor must be similarly changed or invalidated.
rn order to provide this communication, the related art provides a potential tar8et processor with storage apparatus, wherein a source processor can store signals indicative o the requirement for communication with the target processor by the source processor. The source proceqsor stores signals representin~ the communication desired between the two processors in a predetermined location in main memory, typically referred to as the processor mallbox, and transfers signals to the storage apparatus in the tar8et processor. The target processor, according to a prearranged protocol, reviews the storage apparatus, and when a signal is found in the storage apparatus, the target processor retrieves the contents of a location in its mailbox.
The contents of the mailbox identify the activity that the source processor is requesting the target processor to perform.
This procedure for interprocessor communication may have a significant impact on the performance. The tar8et processor must first identify the presence of a a communication request, must stop the current processing activity and call upon a software procedure to retrieve the contents of the mai.lbox, interpret the contents of the stored request and perform the activity indicated bv the mailbox flle contents. In addition, the source processor may suspend other activity in order to determine whether che activity requested by the source processor has been performed.
A need has therefore been felt for apparatus and method that would provide for ineerprocessor communication by min:imizin~ the impact on system performance, Obiects of the Invention It is therefore an object of the present invention to provide an improved data processing system, It is yet another object of the present invention to provide apparatus and method for communication between processing components of the data processing system.
It is still another object of the present invention to permit execution of a command generated ~ 2801!3 I
in a first processor by a second processor without intervention of a software program in the second processor.
It is a still further object of the present invention to provide for interprocessor communication in a data processing system that reduces the impact of the communication on the performance of the data processing system.
Summarv of the Invention The aforementioned and other objects are accomplished, according to the present invention, by providing apparatus in a target processor that can receive and store a command transmitted by a source proces~sor via a system bus. The source processor lS receive~ a si~naL from the target processor when the COItlmalltl i'9 store(i ln the ~s~orage apparatus. ~When the command i-. seore(l in the ~-lppat.ltus of the target proc:essor, a stdtus signal is genérated in the target processor. When the tar8et processor completes execution of the current instruction, the status signal causes ;he command stored in the target processor to be executed. ~fter execution of the command. the target processor continues the instruction sequence in progress at the time that the command was entered in the target processor apparatus. The transferred command, in the preferred embodiment, can result in two types of activity in 2~0~3 the tarqet processor. The first type of activity is a modification of ~on~rol da~a stored in the target pro~essor, i.e.
modification of data relating to address translation. The second type of activity is the performance of a function requested by the source processor, i.e. execution of the request stored in the target processor mailbox. The source processor can examine the main memory location, altered as a result of the data command transmitted to the target processor, to ascertain that the command has been executed. These and other features of the present lnventlon wlll become apparent upon readlng of the discussion herein along wlth the drawings.
In accordance wlth the present lnventlon, there ls provided a processor for use ln a data processlng system of the type ln whlch a plurallty of processors are coupled to a system bues for lnterprocessor communlcatlon of eslgnal groups along sald bus; sald processor characterlzed by comprlsing- lnstructlon executlon apparatus for proce~ssing of data slgnal groups ln sald procesesor ln reesponse to lnstructlon Esignal groupsJ an lnterface unit for recelving and storlng eslgnal yroups from esald bus whlch slgnal groups lnclude the bu~s addres~s of sald processor and a command slgnal groups and command executlon apparatus coupled to a portlon of sald instructlon executlon apparatus and responslve to sald command signal group stored by sald lnterface unit for performlng an operatlon on sald coupled portlon of said lnstruction execution apparatus, said operation being determined by said command slgnal group.
In accordance wlth another aspect of the invention there is provided a method for permitting a second central processing 1~92~0B
5a 72434-48 unit of a data processing system to control the operation of a first central processing unit, said method comprising the steps of: identifying each of a plurality of preestablished conditions in said second central processing unit; generating a command signal group in said second central processing unit in response to each one of said preestablished conditions, said command slgnal group determined by said one pre-established conditlon; applying said command signal group and an associated address slgnal group to a system bus, said address signal group identifying said first central processing unit; retrievlng said command slgnal group form said system bus by said first central processlng unit in response to said address slgnal group; storing said command signal group in a first central processing unit register; suspendlng operation of said first central processing unlt ln response to storage of sald selected signal group in said register; and performing a predetermined operatlon on a selected portion of said first central proce~sing unlt in response to said command slgnal group by apparatus coupled between said first processing unlt register and said selected portions of said first central processing unit, said predetermined operatlon being determined by sald command signal group.
Brief Descrlption of the Drawinqs Figure 1 is a block diagram of a data processing system capable of utilizing the present invention.
Figure 2 is a block diagram of a processor of a data processing system illustrating components used in the implementation of the present invention according to the preferred embodlment.
1292~01!3 5b 72434-48 Figure 3 is a flow diagram illustrating the communication between processors according to the present invention.
Figure 4 is a dlagram illustrating the format of the data signal groups assoclated with the transferred command that are transferred between the l~Z~)8 source processor and the target processor on the address lines of the system bus.
Figure 5a, 5b and 5c illustrate the format of data signal groups associated ~ith the transferred command that are transferred on the data lines of the system bus.
Figure 6 illustrates the organization of main memory locations associated with each processor that supports the operation of the present invention.
10Figure 7 is a diagram illustrating the execution of the transferred command in relation to other data processing system activity.
Description of the Preferred Embodiment l. Detailed Description of the FiRures 15~eferring now to ~ig. 1, a dar.a processing system capable of advanta~eou~Ly u~ in~ (:he present invencion is show1l. rhe dat.l pr()cessir1g system includes at least two processors (i11ustrated hy processor 10 and processor 1l, a main memory unit 15, at least one peripheral interface units (illustrated by peripheral unit 12 and peripheral unit 13) and a system bus 19. In the data processing system illustrated in Figure l, the main memory unit stores the data signal groups to be manipulated bv the processors. During initialization of the system, The storage space on the main memory unit 15 is divided into a multiplicity of regions, each storing 1292~308 preidentified logic signals. In addition, the main memory unit has certain regions reserved for control data, the control data being accessible to the processors. The use of a common main memory unit for a plurality of processors is described as a "tightly coupled" system.
Referring next to gigure 2, components of the processors relevant to the present invention are shown. The processor includes a system bus interface 1~ unit '1 that senses all the data (logic) signal groups applied to the system bus. The logic signals applied to the system bus include information designating the target component to which an associated data signal group is to be applied within the tar8et processor. The system bus interfsce unit 21 includes the apparatus tor identifying when signals applied to the system bus 19 are to be transmit~ed to the processor with which the interface unit is associated. The system bus interface unit 21 aLso includes apparatus Eor applying a signal, communicating to the source processor that the target processor has received the logic signals, on line 29 to the system bus 19. This signal is generally referred to as the "acknowledge" signal. The data signals from the source processor are stored in a storage apparatus 22. Associated with the storage apparatus 22 is a storage cell 24, such as a register ~2~2~;08 cell, that causes a signal to be applied within the target processor indicating that a data signal group is stored in the storage apparatus 22. The applied signal further indicates to the target processor that signal group stored in the register 22 is a command.
The signals in the storage apparatus 22 are applied to decode logic 24. The signal from storage cell 23 is applied to switch 27. The output signals from switch 27 are applied to the decode logic 24 and to the processor instruction register 25. Output signals from the decode logic 24 are applied to a content addressable memory 26 and to interrupt apparatus 28. The interrupt apparatus 28 applies signals to the system bus interface unit 21 and the lS decode logic Z4 applies signals to the system interface unit 21.
Referrin8 once a8~in to ~igure 2, the processor i9 shown as havillg a content addressable memory included therein. In the preferred embodiment, each processor includes two content addressable memories, one content addressable memory associated with data segments and one content addressable memory associated with data pages. The content addressable memories are used to translate a symbolic address used by a program executing in a processor to a physical address designating a location in the main memory unit. An appropriate 12~21~08 command in storage apparatus 22 can invalidate a selected location or all the locations in a content addressable memory.
Referring next to Fig. 3, a flow diagram illustrating communication between two processors is shown. After the source processor identifies the requirement to communicate with the target processor in step 301, a software lock is set in the operatin~
system to prevent simul~aneous communication b~ two processors in step 302. The source processor, for selected interprocessor communication sequences, prepares and stores data ~iles in a predetermined main memorv unit location, i.e. the tar8et processor mailbox, in step 303. rn step 304, the source processor executes the interprocessor instruction, the instruction then transfers the command to the tar8et processor in seep 305. ln step 305, the tar8et processor 9cknowledges the receipt of the command after the transfer has taken place. If the acknowledge signal is noe recelved, in step 307 the source processor once again attempts to transfer the data signal group to the target processor via step 305. When the transfer of the data signal group is successful, then the source processor continues with the curren~ instruction sequence execution. This instruction sequence execution continues until a preselected activity and then performs the testing of 1~92~10~
the indicia in step 310. The target processor, after completion of the execution of the current instruction or instruction sequence, executes the command in step 308 identified by the transferred data signal group. In step 309, the target processor establishes an indicia available to the source processor indicating completion of the activitv, i.e.
execution of the transferred command. .~t a later period of time, the source processor tests, in step 310, the indicia set by the target processor to determine iE the command designated by the transferred data signal group has been executed.
Reterring ne.Yt to Fig. 4, the format ot ~he portion of the command transferred from the source processor to the targe~: processor on the a(ldress lines of the system bus is shown. The logic signal group is 16 bits in length. Bits 0 through 9 specify the identification number of the target processor.
Bits 10 through 15 specify the function to be performed by the target processor. These functions include (0) flush the se8ment content addressable memory, (I) flush an entry in the segment content addressable memory, (2) flush the page content addressable memory, (3) set activity flag and place an entry in rhe interrupt queue and (4) flush an entry in the page content addressable memory.
Referring to Figure 5a, 5b, and 5c, 12~2~308 portions of the transferred command transferred over the data llnes of the system bus is shown. For functions 0 and 2, wherein the entire contents of a content addressable memory are invalidated, no additional Information is needed. 1~hen the function reques~ed by the source processor is (1) or (4), i.e.
flush an entry in the segment or page content addressable memory, then the format o~ the second data Sl~nal group is shown in Fig 5a and 5c respecti-e1~.. In Fi.g. 5a, data signal group, the bits in positions 2 through 11 specifv the particu:lar entry in the segment content addressable memory to be flushed. I`he data slgna1s trans~erred in FiR. 5a and 5c are ava~lab1e to the source processor in so~tware visibLe registers. In Fig. 5c, the designation of the particuLar page descriptor requires ~wo signal groups, the page descripcor identified by positions 4 through 15 in the first si~nal group and positions 16 through 22 in the second data group. As shown in Fig~ 5b, when the function code (3) is transferred, in the associated signal group transferred over the da~a lines of the system bus, bits 0 through 9 identify the source processor while bits 10 through 15 designate the interrupt level. The interface uni~
includes apparatus to interpret the function code to determine if the data lines have logic signals applied thereto that are relevant to the process 2~0~3 identified by the function code.
Referring next to Fig. 6, an organization of the memory locations in main memory associated with each processor supporting the present invention is shown. At the time of initialization of the system, the operaring svstem allocates a group of memory locations 61 to a selected processor. The memory locations associated with each processor has allocated therein particular memory locations reserved ~or specified tvpe data. ~n particular, a plurality ot locations 62 are reserved for activity flags. Simi~arly, a plurality of locations in the group of main memorv locations associated with each processor are reserved as the mail box and store messages and requests from other processors.
Referring to Fig. 7, a diagram illustrating the opera~ion o~ the present invention is shown. The targee processor executes a series of instructions 71, i.e. by loading the instruction register. At some point, the source processor executes the interprocessor instruction and transfers command 72 to the tar8et processor. The completion of the command transfer will typically occur during the execution of a current instruction. After the current instruction has been executed, the target processor will execute the command 73 stored in storage apparatus 22. The target processor will then 1~2~10~3 execute the next instruction in the sequence.
2. Operation of the Preferred Embodiment In the present invention, interprocessor commands that can be executed by apparatus (hardware) are chosen. In addition, the interprocessor commands are chosen so that if the apparatus for non-software execurion is not available, the apparatus can be added without excessive additional design comple.~it~
and without unacceptable additionaL appararus~ The content addressable memory location invalidation and a portion of an interrupt command are two interprocessor commands implemented in the pre~erred embodiment, however other commands can be si~nilarly processed by the present invention.
The present invention permits a greater independerlce of opera~ion between ~he processors.
This independence is achieved by selecting certain activity for use with the present invention. In particular, the preferred embodiment involves two types of interprocessor communication. In the first type of communication, the source processor informs the target processor that a certain address identified by the contents of a content addressable memory is no longer valid. The command transferred to the target processor then invalidates the address(es) designated by the source processor in the content addressable memory.
Z~08 -14~
In the second type of communication, the source processor requires that the target processor gain access to data signal groups in the processor mailbox, for example, to execute a routine or program under the control of the source processor. In this communication, the source processor transfers the request to the target processor mailbox for use by the target processor. The command transferred to the target processor in this second type ot`
communication indicates the type of activity, i.e.
the data groups in the main memory to be used by the target processor, and the priority level of the activity requested by the source processor. Ti)e designation of the priority level provides for an orderly e.YeCUtiolt of activity by the tar8et processor and eliminates inappropriate~ interruption of activity by a lower level process.
In either type of comnlunication, apparatus has been added to the processors so the transferred command can be executed by the tar8et processor without software intervention. The presence of a signal in the storage cell 23 prevents the instruction register from executing the next instruction until the command stored in storage apparatus 22 has been executed. appropriate decoding apparatus has been added to the processors so that a content addressable memory can have either a selected 1~2~() !3 or the entire contents invalidated. With respect to the command related to the request stored in the processor mail box, the interrupt apparatus 28 tests the priority of the currently executing program S against the priorl;y of the request in the mailbox while simultaneous loading appropriate activitv flags and prioritv designation in the main memory location group associated with the target processor. When the request prioritv is higher than the currentl-executinx pro~rum, then a tu11 interrupt is e~ecutedby the processor and the request in the mailbox will be executed ne~t by the processor If the priority of the request is lower tharl the priority of the currently e~ecuting program, then the currently executin~r~ program will continue in execution.
When ~the source processor origin.1l~y transfers the data signal group, the rteceipt of the "acknowledge" signal permits the source processor to execute other inseructions. According to the prior art, the operation of the source processor would be interrupted until confirmation that the requested operation was completed. In the current invention, the source processor is free to execute other instructions after the identification of the "acknowledge" signal. The source processor does examine the contents of selected locations in the main memory to insure that the requested operation ~2 ~0 has in fact taken place. But this examination can take place after other processing by the source processor, permitting more intdependent operation.
After execution of the invalidation of the contents of a location or locations in a content addressable memory, the command provides that an appropriate activity flag be set in a predefined location in main memory in order that the source processor can insure that the command has been e.Yecuted. ~'ith respect to the command related to the processor interrupt, the command requires that activLtv flags, processor identification numbers and priority levels be stored in selected predefined main memory locations. The source processor can interrogate those locations to determine in the command has been executed, so no indepenclent ~ignal neetd be set in che main memory to i.ndit.ate completion of this c~mlnand.
I~ will be clear that the apparatus added 2~ to implement the comlnand ~rans~erred by tlte interprocessor instruction can be used by any processor in execution of internal activity, i.e.
invalidating content addressable rnemory contents.
Although the invention has been described in relation to the communication between processors, it will be clear that in the modern data processing systems many system components are being designed with logic 2~0~3 signal manipulation capability. The technique described can be used for improved communication between any of the system components with appropriate processing capability.
The foregoing description is intended to illustrate the operation of the preferred embodiment and is not meant to limit the scope of the invention.
The scope of the invention is to be limited only by the ~ollowing claims. From the ~oregoing description, many variations would be apparent to one skilled In the art that would yet be encompassed by the spirit and scope of the invention.
Claims (5)
1. A processor for use in a data processing system of the type in which a plurality of processors are coupled to a system bus for interprocessor communication of signal groups along said bus; said processor characterized by comprising:
instruction execution apparatus for processing of data signal groups in said processor in response to instruction signal groups;
an interface unit for receiving and storing signal groups from said bus which signal groups include the bus address of said processor and a command signal group; and command execution apparatus coupled to a portion of said instruction execution apparatus and responsive to said command signal group stored by said interface unit for performing an operation on said coupled portion of said instruction execution apparatus, said operation being determined by said command signal group.
instruction execution apparatus for processing of data signal groups in said processor in response to instruction signal groups;
an interface unit for receiving and storing signal groups from said bus which signal groups include the bus address of said processor and a command signal group; and command execution apparatus coupled to a portion of said instruction execution apparatus and responsive to said command signal group stored by said interface unit for performing an operation on said coupled portion of said instruction execution apparatus, said operation being determined by said command signal group.
2. The processor of Claim 1 further comprising confirmation means for applying a confirmation signal group to said system bus indicating completion of said operation performed by said command execution apparatus.
3. The processor of Claim 1 wherein said interface unit applies a suspend signal to said instruction execution apparatus to cause said instruction execution apparatus to suspend operation until said predetermined operation performed by said command execution apparatus has been completed, whereby operation of said instruction execution apparatus is suspended after completion of the instruction signal group currently being executed by said instruction execution apparatus.
4. A method for permitting a second central processing unit of a data processing system to control the operation of a first central processing unit, said method comprising the steps of:
identifying each of a plurality of preestablished conditions in said second central processing unit;
generating a command signal group in said second central processing unit in response to each one of said preestablished conditions, said command signal group determined by said one preestablished condition;
applying said command signal group and an associated address signal group to a system bus, said address signal group identifying said first central processing unit;
retrieving said command signal group form said system bus by said first central processing unit in response to said address signal group;
storing said command signal group in a first central processing unit register;
suspending operation of said first central processing unit in response to storage of said selected signal group in said register; and performing a predetermined operation on a selected portion of said first central processing unit in response to said command signal group by apparatus coupled between said first processing unit register and said selected portions of said first central processing unit, said predetermined operation being determined by said command signal group.
identifying each of a plurality of preestablished conditions in said second central processing unit;
generating a command signal group in said second central processing unit in response to each one of said preestablished conditions, said command signal group determined by said one preestablished condition;
applying said command signal group and an associated address signal group to a system bus, said address signal group identifying said first central processing unit;
retrieving said command signal group form said system bus by said first central processing unit in response to said address signal group;
storing said command signal group in a first central processing unit register;
suspending operation of said first central processing unit in response to storage of said selected signal group in said register; and performing a predetermined operation on a selected portion of said first central processing unit in response to said command signal group by apparatus coupled between said first processing unit register and said selected portions of said first central processing unit, said predetermined operation being determined by said command signal group.
5. The processor of claim 1, wherein the other processors of said plurality of processors are also characterized by comprising said instruction execution apparatus, said interface unit and said command execution apparatus.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US86914786A | 1986-05-30 | 1986-05-30 | |
| US869,147 | 1986-05-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1292808C true CA1292808C (en) | 1991-12-03 |
Family
ID=25353015
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000538417A Expired - Lifetime CA1292808C (en) | 1986-05-30 | 1987-05-29 | Apparatus and method for interprocessor communication |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US5850521A (en) |
| EP (1) | EP0247604B1 (en) |
| AU (1) | AU597980B2 (en) |
| CA (1) | CA1292808C (en) |
| DE (1) | DE3750311T2 (en) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| AU630299B2 (en) * | 1990-07-10 | 1992-10-22 | Fujitsu Limited | A data gathering/scattering system in a parallel computer |
| US5983303A (en) * | 1997-05-27 | 1999-11-09 | Fusion Micromedia Corporation | Bus arrangements for interconnection of discrete and/or integrated modules in a digital system and associated method |
| US6493407B1 (en) * | 1997-05-27 | 2002-12-10 | Fusion Micromedia Corporation | Synchronous latching bus arrangement for interfacing discrete and/or integrated modules in a digital system and associated method |
| US7233977B2 (en) * | 1998-12-18 | 2007-06-19 | Emc Corporation | Messaging mechanism employing mailboxes for inter processor communications |
| US6678716B1 (en) * | 2000-06-19 | 2004-01-13 | J. D. Edwards World Source Company | System and method for managing processes |
| US20020099893A1 (en) * | 2001-01-24 | 2002-07-25 | Nguyen Tuyet-Huong Thi | System and method for the handling of system management interrupts in a multiprocessor computer system |
| US20040095948A1 (en) * | 2002-11-18 | 2004-05-20 | Chang-Ming Lin | Data return arbitration |
| US7805557B2 (en) * | 2005-07-12 | 2010-09-28 | Arm Limited | Interrupt controller and method for handling interrupts |
| US8849940B1 (en) * | 2007-12-14 | 2014-09-30 | Blue Coat Systems, Inc. | Wide area network file system with low latency write command processing |
| JP4691153B2 (en) * | 2008-12-10 | 2011-06-01 | 富士通株式会社 | Multi-core processor, control method, and information processing apparatus |
| US8793423B2 (en) * | 2012-03-28 | 2014-07-29 | Advanced Micro Devices, Inc. | Servicing interrupt requests in a computer system |
| US9329671B2 (en) * | 2013-01-29 | 2016-05-03 | Nvidia Corporation | Power-efficient inter processor communication scheduling |
| US10296469B1 (en) * | 2014-07-24 | 2019-05-21 | Pure Storage, Inc. | Access control in a flash storage system |
Family Cites Families (28)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3678467A (en) * | 1970-10-20 | 1972-07-18 | Bell Telephone Labor Inc | Multiprocessor with cooperative program execution |
| US3988716A (en) * | 1974-08-05 | 1976-10-26 | Nasa | Computer interface system |
| FR2288352A1 (en) * | 1974-10-15 | 1976-05-14 | Burroughs Corp | EQUIPMENT AND PROCESS FOR DATA PROCESSING BY ASSOCIATION |
| US4041461A (en) * | 1975-07-25 | 1977-08-09 | International Business Machines Corporation | Signal analyzer system |
| US4149244A (en) * | 1976-06-07 | 1979-04-10 | Amdahl Corporation | Data processing system including a program-executing secondary system controlling a program-executing primary system |
| US4223380A (en) * | 1978-04-06 | 1980-09-16 | Ncr Corporation | Distributed multiprocessor communication system |
| EP0016523B1 (en) * | 1979-02-13 | 1984-09-26 | The Secretary of State for Defence in Her Britannic Majesty's Government of the United Kingdom of Great Britain and | Data processing unit and data processing system comprising a plurality of such data processing units |
| JPS55134459A (en) * | 1979-04-06 | 1980-10-20 | Hitachi Ltd | Data processing system |
| NL7907179A (en) * | 1979-09-27 | 1981-03-31 | Philips Nv | SIGNAL PROCESSOR DEVICE WITH CONDITIONAL INTERRUPT UNIT AND MULTIPROCESSOR SYSTEM WITH THESE SIGNAL PROCESSOR DEVICES. |
| US4349873A (en) * | 1980-04-02 | 1982-09-14 | Motorola, Inc. | Microprocessor interrupt processing |
| US4365294A (en) * | 1980-04-10 | 1982-12-21 | Nizdorf Computer Corporation | Modular terminal system using a common bus |
| DE3026362C2 (en) * | 1980-07-11 | 1984-12-06 | Siemens AG, 1000 Berlin und 8000 München | Device for fast block-oriented data transfer between two computers in operation |
| JPS57117027A (en) * | 1981-01-13 | 1982-07-21 | Nec Corp | Signal sending and receiving circuit |
| US4394727A (en) * | 1981-05-04 | 1983-07-19 | International Business Machines Corporation | Multi-processor task dispatching apparatus |
| US4467412A (en) * | 1981-05-18 | 1984-08-21 | Atari, Inc. | Slave processor with clock controlled by internal ROM & master processor |
| US4417336A (en) * | 1981-06-18 | 1983-11-22 | The Bendix Corporation | Method of testing with computers |
| US4543627A (en) * | 1981-12-14 | 1985-09-24 | At&T Bell Laboratories | Internal communication arrangement for a multiprocessor system |
| US4504902A (en) * | 1982-03-25 | 1985-03-12 | At&T Bell Laboratories | Cache arrangement for direct memory access block transfer |
| DE3376590D1 (en) * | 1982-04-28 | 1988-06-16 | Int Computers Ltd | Data processing system |
| US4731736A (en) * | 1983-04-18 | 1988-03-15 | Motorola, Inc. | Method and apparatus for coordinating execution of an instruction by a selected coprocessor |
| US4862351A (en) * | 1983-09-01 | 1989-08-29 | Unisys Corporation | Method of executing called activities via depictor-linked low level language microcode, hardware logic, and high level language commands; and apparatus for same |
| US4648030A (en) * | 1983-09-22 | 1987-03-03 | Digital Equipment Corporation | Cache invalidation mechanism for multiprocessor systems |
| US4598356A (en) * | 1983-12-30 | 1986-07-01 | International Business Machines Corporation | Data processing system including a main processor and a co-processor and co-processor error handling logic |
| EP0154551A3 (en) * | 1984-03-06 | 1987-12-16 | Codex Corporation | Apparatus for enabling a first processor to cause a second processor to effect a transfer of data between said processors |
| JPH0670787B2 (en) * | 1984-06-29 | 1994-09-07 | 富士通株式会社 | Command transfer control system between processors |
| US4648034A (en) * | 1984-08-27 | 1987-03-03 | Zilog, Inc. | Busy signal interface between master and slave processors in a computer system |
| IT1184553B (en) * | 1985-05-07 | 1987-10-28 | Honeywell Inf Systems | SYSTEM ARCHITECTURE WITH MULTIPLE PROCESSORS |
| US4718002A (en) * | 1985-06-05 | 1988-01-05 | Tandem Computers Incorporated | Method for multiprocessor communications |
-
1987
- 1987-05-27 DE DE3750311T patent/DE3750311T2/en not_active Expired - Fee Related
- 1987-05-27 EP EP87107744A patent/EP0247604B1/en not_active Expired - Lifetime
- 1987-05-27 AU AU73457/87A patent/AU597980B2/en not_active Ceased
- 1987-05-29 CA CA000538417A patent/CA1292808C/en not_active Expired - Lifetime
-
1991
- 1991-04-23 US US07/689,655 patent/US5850521A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| DE3750311D1 (en) | 1994-09-08 |
| EP0247604A2 (en) | 1987-12-02 |
| EP0247604B1 (en) | 1994-08-03 |
| US5850521A (en) | 1998-12-15 |
| DE3750311T2 (en) | 1995-03-30 |
| AU597980B2 (en) | 1990-06-14 |
| AU7345787A (en) | 1987-12-03 |
| EP0247604A3 (en) | 1988-07-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4442487A (en) | Three level memory hierarchy using write and share flags | |
| US4814981A (en) | Cache invalidate protocol for digital data processing system | |
| US4173783A (en) | Method of accessing paged memory by an input-output unit | |
| US4471429A (en) | Apparatus for cache clearing | |
| CA1292808C (en) | Apparatus and method for interprocessor communication | |
| EP0283628A2 (en) | Bus interface circuit for digital data processor | |
| EP0303648B1 (en) | Central processor unit for digital data processing system including cache management mechanism | |
| WO1987005417A1 (en) | Instruction prefetch control apparatus | |
| EP0303661A1 (en) | Central processor unit for digital data processing system including write buffer management mechanism. | |
| EP0175620B1 (en) | Access verification arrangement for digital data processing system which has demand-paged memory | |
| US5091845A (en) | System for controlling the storage of information in a cache memory | |
| US5119484A (en) | Selections between alternate control word and current instruction generated control word for alu in respond to alu output and current instruction | |
| EP0619898A4 (en) | Computer system with two levels of guests. | |
| CA2007167C (en) | Apparatus and method for increased operand availability in a data processing unit with a store through cache memory unit strategy | |
| US5226170A (en) | Interface between processor and special instruction processor in digital data processing system | |
| EP0550286A2 (en) | 2-Level multi-processor synchronization protocol | |
| EP0619899B1 (en) | Software control of hardware interruptions | |
| US4498131A (en) | Data processing system having addressing mechanisms for processing object-based information and a protection scheme for determining access rights to such information | |
| AU606083B2 (en) | Interface between processor and special instruction processor in digital data processing system | |
| US4616315A (en) | System memory for a reduction processor evaluating programs stored as binary directed graphs employing variable-free applicative language codes | |
| EP0153109A2 (en) | Cache coherence system | |
| US4598361A (en) | Allocator for a reduction processor evaluating programs stored as binary directed graphs employing variable-free applicative language codes | |
| US5276892A (en) | Destination control logic for arithmetic and logic unit for digital data processor | |
| CA1328026C (en) | Apparatus and method for enhanced virtual to real address translation for accessing a cache memory unit | |
| EP0437928B1 (en) | Memory management in a multi-processor system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKLA | Lapsed | ||
| MKEC | Expiry (correction) |
Effective date: 20121205 |