CA1183273A - Interface mechanism between a pair of processors, such as host and peripheral-controlling processors in data processing systems - Google Patents

Abstract

Abstract of the Disclosure An interface mechanism between a pair of processors such as a host processor (70) and a processor (31) in an intelligent controller (30) for mass storage devices (40). The interface utilizes a set of data structures employing a dedicated communications region (80A) in host memory (80). There are two layers to the interface - a transport mechanism and a port; the latter is hardware for communicating via the transport mechanism and a process implementing a set of rules governing those communications. Commands and responses are communicated as packets over the host's I/O bus (60), to and, from the communications region (30A) through a pair of ring-type queues (80D and 80E). These rings, and the rules governing their operation, permit the host and controller processors to operate at their own speeds, without creating race conditions of other timing problems while obviating the need for a hardware interlock capability on the I/O bus. The ring entries point to other locations in the communications region where commands and responses are placed. The filling and emptying of ring entries is controlled through the use of an "ownership" byte or bit Fig. 8, 278; Fig. 313, 133, 135, 137, 139) associated with each entry (Fig. 38, 132, 134, 136, 138). The ownership bit is placed in a first state when the message source (i.e., controller or host) has filled the entry and in a second state when the entry has been emptied by its receiver. A message oriented credit system provides flow control and prevents more packets being sent than a ring can accept.

Interrupt generation is reduced because strings of commands and responses can be communicated without need for interrupting the host processor for each one. The interface mechanism requests interrupts primarily only when its command ring undergoes a state change from full to not-full and when its response ring undergoes a state change from not-empty to empty. A "FLAG" bit in a preselected register controls the generation of interrupt requests.

During a multi-step initialization procedure, the integrity of the communications path between host and controller is checked out. In particular, the communications path includes a register and information is written to and read from the register to vecify correct operation of each bit of the register. As part of the write-read processs, certain host-specific parameters, such as the sizes of the ring-type queues and their starting addresses is sent from the host to the controller.

Capability is shown also for allowing repeated access to the same host memory location for successive reads, writes, or any combination of the two. With bus adapters which impose rigid sequencing rules which do not allow reads and writes to be mixed, the adapter channel is pruged between successive accesses to the same location. The port requests the purge and it is executed by the host.

Description

Cross-Reference to Related Application ____.______ ___ This appllcation relates to a data processing s~stem, other aspects of which are described in the following commonly assigned Canadian applications, to which reference may be made for clarification of the environment, intended use and explanation of the present invention:
Serial No. 412,883, filed on October 5, 1982, titled Disk Format ~or Secondary Storage System, and Serial No. 412,823, filed October 5, 1982, titled Secondary Storage Facility Employing 1l) Serial Communication Between Drive and Controller.
Field of the Invention . . _ . .
This invention relates to the field of data processing systems and, in particular to an interface mechanism for connec-ting a host processor wi-th ano-ther processor which controls a storage facility, peripheral device or o-ther subsystem in such sys-tems.
~ackqround of the Invention In data processincJ systems utiliziny secondary storage ~acilities, communications between the host processor, or main ~rame, ancl secondaxy storage facllities have a considerable impact on system performance. Secondary storage facilities com-prise data processiny elements which are not integral parts of a central processing unit (CPU) and its random access memory element (i.e., the host computer), but which are directly connec-ted to and controlled by the central processing unit or other elements in the system. These 3~73 facilities are also known as "mass storage" elements or subsystems and include, among other possibilitie~, disk-type or tape-type memory units (also called drives).
A secondary storage facility typically includes a controller and one or more drives connected thereto. The controller appears to the rest of the system as simply an element on an input-output bus which connects together the various elements of the system. It receives commands and provides responses and other messages over the bus.
These commands inclu~e information abou~ operations to be performed by the storage facility, including, for example, the drive to be used~ the size of the transfer and perhaps the starting address on the drive for the transfer and the starting address on some other system elel~ent, such as the random access memory unit of the host, to or from which the data is to be transferred.
The controller converts this command information into the necessary signals to effect the transfer between the appropriate drive and other system elements. During the transfer itself, the controller routes the data between the ~rive and the input/output bus or a memory bus.
Typically, controllers have communicated with a host CPU at least partially by means of an interrupt mechanism. ~hat is, when one of a predetermined number o significant events have occurred, the controller has generatad an interrupt request signal which the host has received a short time later; in response, the host has stopped what it was doing and has conducted a dialogue with the controller to service the controller's operation. Consequently, every interrupt request signal generated by the controller gave rise to a delay in the operation of the central processor. It is an object of the present invention to reduce that delay by reducing the frequency and number of interrupt requestsO

~3~73 Modern controllers for secondary storage facilities are usually so-called "intelligent" devices, containing one or more processors of their own, allowing them to perform sophisticate~ tasks with some degree o independence~ Sometimes, a processor in a controller will share a resource with another processor, such as the host's central processor unit. One resource which may be shared is a memory unit.
~t is well known that when two independent processors share a common resource (such as a memory through which the processors and the processes they execute may communicate with each other), the operation of the two processors ( i.2., the execution of processes or tasks by them) must be "interlocked" or "synchronized", so that in accessing the shared resource, a defined sequence of operation is maintained and so-called "race" conditions are avoided. That is, once a first processor starts using a shared resource, no other processor may be allowed to access that resource until the first processor has finished operating upon it.
Operations which otherwise might have occurred concurrently must be constrained to take place serially.
Otherwise, information may be lost, a processor may act on erroneous information, and sy~tem operation will be ~5 unreliable. ro prevent this from happening, the communications mechanism (i.e., bus) which links together the processors and the shared resource typically is provided with a hardware `'interlock" or synchronization capability, by means of which each processor is peevented rom operating on the shared resource in other than a predefined sequence.
An illustration may help to demonstrate the problem.
Consider two processors trying to communicate with each other through a memory which serves as a shared resource 3~73 a first one of the processors is supposed to perform a calculation and put the result X in memory location Y, following which the other (i.e., second) processor is supposed to take the result in location Y and use it in a calculation to produce result Z. If the second processor reads the contents of location ~ before the first processor has written X there~ result Z will be wrong.
Si.milarly, if the first processor not only writes X into loca-tion Y, but before the second processor gets a chance to read X
it overwrites into location Y some new data X', the second pro-cessor once again will not receive the correct information if ittherea~ter reads location Y. This loss of proper sequencing, which allows one processor to "~et ahead" of the other and lose context, is re~erred to as a race condition.
In the prior art, three interlock mechanisms are widely known ~or synchronizing processes within an operating system, to avoid race conditions. One author calls these mechanisms (1) -the tes-t-and-set instruction mechanism, (2) the wait and signal mech-~ni~m an~ (3) the P and V operations mechanism. S. Madnick and onovan, Operat1nq Systems, Section 4-5.2 at 251-55 (McGraw-~n Elill, Inc., 1~7~ nother author refers to three techniques:~or ensurlng correct synchronization when mu].tiple processors communicate through a shared memory as (1) process synchroniza-tion by semaphores, (2) process synchronization by monitors and (3) process synchronization by moni.tors without mutual exclusion.
C. Wei.tæman, Dlstributed Mic:ro/~inicomputer S tems: Structure, Irnplemenitation and .A~lication, Sect.ion 3.2 at 103-114 (Prentice-llall, Inc , 19~0)~

3~73 When applied to multiple processors which communicate with a shared resource via a bus, such mechanisms impose limitations on bus characterlstics; they re~uire, for e~ample, that certain com-pound bus operations be indivisib~e, such as an operation which can both test and set a so~called "semaphore" or monitor without being interrupted -~7h le doing so. These become part of the bus description and specifications.
If the testing of a semaphore were done during one bus cycle and the setting during a different bus cycle, two or more processors which want to use a shared resource might -test its semaphore at nearly the same time. If the semaphore is not set, the processors all will see the shared resource as available.
They then will try to access it; but only one can succeed in se-t-t.ing th.e semaphore and gaininy access; each of the other proces~
sors, though, haviny already tested and found the resource avail-able, would go through the motions of setting the semaphore and reading o.r writing data without knowing it had not succeeded in aacessing the resource. The data thus read would be erroneous and the data thus written could be lost.
~0 Not all buses, thouyh, are designed to allow implemen-tat.ion of such indivisible operations, since some buses were not des.igned with the idea of connecting multiple processors via shared .resouraes Consequently, such buses are not or have no-t been pro-v.ided with hardware .interlock (or processor synchronization) mech-anisms, One bus in this category is the UNIBUS (tradernark) of Digital Equipment Corporation, assignee hereof When a bus does not have such a capability, resort ~ ~ ~3;;~3 frequently has been made to using processor interrupts to con-trol the secondary storage ~acility, or some -5a--3~3 combination of semaphores and interrupts (as in the Carnegie-Mellon University C.mmp multiminicomputer system described at pages 27-29 and 110-111 of the above-identified book by Weit~man), but those approaches have their drawbacks. If multiple processors on such a bus operate at different rates and have different operations to perform, at least one processor frequently may have to wait for the other. This aggravates the slow-down in processing alrea~y inherent in the use of interrupt control with a single processor.
A further characteristic of prior secondary storage facilities is that when a host computer initially connects to a controllér, it usually assumes, but cannot then verify/ that the controller is operating correctly.
Therefore, it is an object o~ this invention to provide an improved method for handling host-controller communications over a bus lacking a hardware interlock capability, whereby the processors in the host and controller can access shared re~sources, such as host memory, while avoiding race conditions.
Still another object of the invention is to provide a communicatlons mechanism which minimi~es the generation by the controller oE host central processor interrupt re~uest.
Another object oE this invention is to provide a communications mechanism for operation between controller and host which permits the host to verify correct operation of the controller at the time of initialization.

Summar~ f the Invention In accordance with this invention, the host-controller lnterconnection is accomplished through an interface mechanism which includes a specifically-3~73 configured, dedicated communications region in the hos~'smemory; this communications region is a shared resource operated on by both the host pro-cessor and the peripheral controller's processor, in accordance with a set of rules discussed below. The structure of this communications region and the rules governing its use together constitute the interface mechanism of this invention~
Access to the communica~ions re~ion is controlled partly by the use of interrupt request signals, but 1~ provision is made for sending several commands or responses in sequence, while requiring only one processor intereuption for the entire sequence.
The communications region of host memory consists of two sections: (1) a header section and (2) a variable-length section. The contents of the header section arewords for identifying interrupt service routines. The contents of the variable-length section are a pair of lists or buffers, the first containin~ commands to be transmitted to the controller and the second containing responses received from the controller.
The command and response lists are maintained in buf~ers; each buffer is organized into a "ring" - i.e.l a ~roup of memory locations which is addressable in rotational ti.e., modulo) sequence, such that when an lncrementing counter (modulo-buffer-size) is used for addressing the buffer, the address of the last location in the sequence is followed next by the address of the first location. Each buffer entry, termed a descrip~or, includes (1) an address where a command may be found for transmission or where a response is written, as appropriate and (2) a so-called "ownership" byte (which in its most elementary form reduces to a single ownership bit) ~hich is used by the processors to control access to the entry.

~3~73 Commands and responses are transmitted bet,Jeen the host and a peripheral controller as packets, over an input/output bus of the host, via transfers which do not reguire central processor interruption. These packet transfers occur to and from the dedicated communications region in the host computer 19 memory. The port polls this region for commands and the host polls it for responses.
An input/output operation begins when the host deposits a command in the command list. The operation is seen as complete when the corresponding response packet is removed by the host from the response list.
Only the host writes into the command ring and only the control]er writes into the response ring.
The "ownership" bit for each ring entry is set to a first state by the processor which writes the ring entry and is cleared from that state by the other processor only after the command has been sent or the response read. In addition, after writing an the entry, the same processor cannot alter it until the other processor has cleared that entry's ownership bit.
By thus organizing the command and response lists into two separate rings and controlling their operation throu~h a rigid sequential protocol which includes an ownership byte (or bit) for each rin~ entry and rules for setting and clearing the ownership byte, the need for a hardware bus interlock is avoided and there is no need to require certain combined indivisible operations to occur within the sa,ne bus cycle. This allows the system to utilize, for example, the UNIBUS communication interconnection of Digital Eguip,nent Corp., Massachusetts, which i5 an exemplary bus lacking a hardware interlock feature.

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At the same time, the host and controller processors are allowed to operate at their own rates, so as to avoid slowing down the throughput of transfers.

The rings buffer the asynchronous occurrence of command and response packets so that under avorable conditions, long strings of commands, responses and exchanges can be passed without having to interrupt one or more processors for each separate command or response. The interface mechanism is adapted to generate interrupt requests, at the option of the host computer, only when the command ring makes a transition from a full to a not-full condition or when the response ring makes the converse transition from empty to not-empty.

These and other features, ad~antages and objects of lS the present invention will become mroe readily apparent from the following detailed description, which should be read in conjunction with the accompanylng drawings.

Brief Descri~tion of the orawings _._ _ _ FIG. 1 is a conceptual block diagram Oe a system in which the interface mechanism oE the present invention has utility;
Fig. 2 is a basic block diagram oE a data processing system in which the interface mechanism of the present lnvention may be employed;
Fig. 3~ is a system block diagram of an illustrative embodiment of a data processing system utilizing the interface mechanism of the present invention;
Fig. 3B and 3C are diagrammatic illustrations of a ring 80~ or 80E of Fig. 3A.
Fig. 4~ and 4B are elementary flow diagrams illustrating the sequence of events that occurs when the controller wishes to send a response to the host;

~L&3;;~73 Fi~. 5 is an elementary flow diagram showing the sequence of events that occurs when the host issues a command to the controller;
Fig. 6 is a similar flow diagram showing the controller's action in response to the host's issuance of a command;
Fig. 7 is a diagrammatic illustration of the comrnunications areas of host memory, including the command and response rings;
Fig. 8 is a diagra,nmatic illustration of the forl-natted co,nmand and response descriptors which co,nprise the ring entries;
Fig. 9 is a diagrammatic illustration of the command and response message envelopes;
Fig. 10 is a diagrammatic illustration of a buffer descriptor according to the present invention;
Fig. 11 is a diagrammatic illustration of the status and address (SA) register 38 of Fig. 3~;
Figs. 12~-12D are flow charts of the port/controller initLalization sequence according to this invention; and ~ ig. 13 is a diayrammatic illustration of the "last ail" response packet of this invention.

DETAILED DESCRIPTION O~ AN ILLUS~RATIV~ EMBODIMENT
The present invention has particular utility in a data processing system having an architectural configuratlon designed to enhance dev~loprnent of futur mass storage systems, at reduced cost. Such a system is shown in Fig. 1. In this system, a high level ir.put/out (indicated at 1) protocol is employed foc communications between a host computer 2~ and an intelligent mass storage controller 2B. Such a high level protocol is intended to free the host froin having to deal with peripheral device-dependent requirements (such as disk 3~3 geometry and error recovery strategies). This is accomplished in part throught he use of a communications hierachy in which the host communicates via only one or two peripheral device "class" drivers, such as driver 4, instead of a different I/~ driver for each model of peripheral device. For example, there may be one driver for all disk class devices and another for all tape class devices.
Device classes are determined by their storage and transfer characteristics. For example a so-called "disk class" is charaterized by a fixed block length, individual block update capability, and random access.
Similarly a so-called "tape class" is characterized by a variable block length, lack of block update capability, and sequential access. Thus, the terms "disk" and "tape"
as used herein refer to devices with such characteristics, rather than to the physical form of the storage medium.
Each class driver, in turn, communicates with a device controller (e.g., 2~) through an interface mechanis,n 10~
Much of the inter~ace mechanisrn 10 is bus-(rather than drive-)specific. Therefore, when it is desired to connect a new mass storage device to the system, there is no need to change the host's input/output processes or operating system, which are costly (in time, as well as money) to develop. Only the controller need be modified to any substantial degree, which is far less expensive.
And much of that cost can be averted if the controller and host are made self-adaptive to certain of the storage device's characteristics, as explained in the above-identified commonly assigned applications.
Within the framework oE this discussion, a data processing system cornprises a plurality of subsystems 3~273 , ., interconnected by a communications mechanism (i.e., a bus and associated hardware). Each subsystem contains a port driver, which interfaces the subsystem to the communications mechanism. The communications mechanism contains a port for each subsystem; the port is simply that portion of the communications mechanism to which a port driver interfaces directly.
Thus, in Fig. 1 the exemplary system comprises host computer 2A, intelligent ,nass storage controller 2B and communications mechanism 7. Host 2A includes a peripheral class driver 3 and a port driver 4.
Controller 2B, in turn, includes a counterpart port driver 5 and an associated high-level protocol server 6.
The communications mechanism 7 includes an interface member (8, 9) for each port driver.
The port drivers 4 and 5 provide a standard set of communications services to the processes within their subsystems; port drivers cooperate with each other and with the communications kmechanism to provide these services. In addition, the prot drivers shield the phy3ical characteristics of the communications mechansim form processes that use the communications services.
Class driver 3 ls a process which executes within host 1. Typically, a host I/O class driver 3 communicates with a counterpart in the controller 2B, called a high-level protocol ser~er.
The high-level protocol server processes host commands, passes commands to device-specific modules within the controller, and sends responses to host commands back to the issuing class driver.
In actual implementation, it is also possible for the functions fo the controller-side port driver S and interace 9 to be performed physically at the host side oE the communications mechanism 7. This is shown in the ~ ~3~3 example described below. Nevertheless, the diagram of Fig. 1 still explains the arcnitectural concepts involvedO
Note also that for purposes of the further explanation which follows, it is generally unnecessaey to distinguish between the interface an~ its port driver.
Therefore, unless the context indicates otherwise, when the word "port" is used below, it presumes and refers to the inclusion of a port driver with an interface.
Referring now to Fig. 2, there is shown a system level block diagram of a data processing system utilizing the present in~ention. A host computer 2A tincluding an interface mechanism 10) employs a secondary storage subsystem 20 comprising a controller 30, a disk dri~e 40 and a controller-drive interconnection cable 50. The host communicates with the secondary storage subystem over an input/output bus 60.
Fig. 3A expands the system definition to further explain the structure of ~he host 2A, controller 33 and their interconnection via interface mechanism 10. As illu~trated there, the host 2~ comprises four primary subunits: a central procesor unit (CPU) 70, a main memory 80, a system bus 90 and a bus adapter 110.
A portion 80~ oE memory 80 is dedicated to service a~ a communications region for accessing the remainder of memory ao. As shown in Fig. 3A, communications region 80A comprises four sub-regions, or areas. Areas 80B and 80C together form the above-lndicated header section of the communications region area 80B is used for imple~nenting a bus adapter purge function and area 80C
holds the ring transition interrupt indicators used by the port. The variable-length section of the communlcations region coMprises the response list area 80D and the command list area 80E. The lists in areas ~ ~3Z~3 80D and 80E are organized into rings. Each entry, in each ring, in turn, contains a descriptor (see Figure lO) pointinq to a memory area of sufficient size to accommodate a command or response mes-sage packet of predetermined maximum length, in bytes.
Host 2A may, for example, be a Model VAX-ll/780 or PDP ll computer system, marketed by Digital Equipment Corporation of ~aynard, Massachusetts. (VAX and PDP are trademarks of Digital Equipment Corporation.) System bus 90 is a bi-directional information path and communications protocol for data exchange between the CPU 70, memory 80 and other host elements which are not shown (so as not to detract from the clarity of this explanation). The system bus provides checked parallel inEorma-tion exchanges synchronous with a common system clock. A bus adapter llO -translates and transfers si.gnals between the system bus 90 and the host's input/output (I/O) bus 60. For example, the I/O bus 60 may be the UNIBUS I/O connec-tion, the system bus may be the synchronous backplane in-terconnec-k,~on (S13I) O:e the ~IAX-ll/780 computer, and the bus adapter llO
may be the ~od~l DW780 UNIBUS Adapter, all Digital Equipment Cor-~0 poration products. (T~IBUS, SBI and DW780 are trademarks of Diqital Equi,pment Coxporatlon.) Controlle,r 2B includes several elements which are used specieically for communicating with the host 2A. There are pointers 32 and 34, a command bufEer 36 and a pair of regis-ters 37 and 38, Pointers 32 and 34 keep track of the current host command ring entr~ and the host response ring entry, respectively.
~ommand buEfers 36 provide temporary storage for commands awaiting !

3~73 processing by the controller. Register 37, termed the "IP"
register, is used for initialization and polling. Register 38, termed the "SA" register, is used for storing status and address information. A processor 31 is the "heart" of the controller 2A;
it executes commands -14a 3~73 from buffers 36 and docs all the housekeeping to keep communication flowing between the host 2A and the drive 40.
The physical realization of the transport mechanism includes the uNIsus interconnection (or a suitable counterpart) 60, system bus 90 and any associated host and/or controller-based logic for adapting to same, and bus adapter 110.
The operation of the rings may be better understood lQ by referring to Figs. 3B and 3C, where an exemplary four-entry ring 130 is depicted. This depiction is conceptual, rather than physical. ~he ring 130 may be either a command ring or a response ring, since only their application differs. There are four ring entry positions 132, 134, 136 and 138 consecutive addresses RB, RB~4, respectively. Each ring entry has associated with it an ownership bit (133, 135, 137, 139) which is used to indicate its status. Assume the ring 130 has been operating for some time and we have started to observe it at an arbitrarily selected moment, indicated in Fig. 3B.
write pointer (WP), 142, points to the most recent write entry; correspondingly, a read pointer (RP), 144, points to the most recent read entry. In Fig. 3B, it will ~e seen that entry 138 has been read, as indicated by the position of RP 144 and the state of ownership bit 139. ~y convention, the ownership bit is set to 1 when a location has been filled (i.e., written) and to O when it has been emptied (i~eO, read). The next entry to be read is 132. Its ownership bit 133 is set to 1, indicating that it already has been written. Once entry 132 i5 read, its ownership bit is clearedr to t as indicated in Fig. 3C. This co~npletely empties the ring 1300 The next entry 134 cannot be read until it is written and the state of ownership bit 135 is changed. Nor can entry 132 be re-read accidentally, since its ownership bit has been cleared, indicating that it already has been read.
Having thus provided a block dia~ram exmplanation of the invenkion, further understanding of this interface will require a brief digression to explain packet communications over the system.
The port is a communications mechanism in which communications take place between pairs of processes resident in separate subsystems. (As used herein, the term "subsystems" include the host computers and device controllers; the corresponding processes are host-resident class drivers and controller-resident protocol serversO ) Communications between the pair of processes taken place over a 'Iconnection'' which is a soft communications path through the port; a single port typically will implement several connections concurrently. Once a connection has been established r the following three services are available across that connection~
sequential message; (2) datagram and (3) block data transfer.
When a connection is terminated, all outstanding communications on that connnection are discarded; that i8, the receiver "throws away" all unacknowledged messages and the sender "forgets" that such Inessayes have been sent.
The implementation of this communications scheme on the UNIBUS interconnection 60 has the following characteristics: (l) communications are always point-to-point between exactly two subsystems, one of which isalways the host; (2) the port need not be aware of mapping or memory management~ since buffers are identified with a UNIBUS address and are contiguous ~i3~73 within the virtual bus address space; and (3) the host nee~ never directly initiate a block data transfer.
The port effectively and conceptually is integral with the controller, even though not physically localized there. This result happens by virtue of the point-to-point property and the fact that the device controller knows the class of device (e.g., disk drive) which it controls; all necessary connections, therefore, can be established by the port/controller when it is initialized.
The Sequential Message service guarantees that all messages sent over a given connection are transmitted se~uentially in the order originated, duplicate-free, and that the~ are delivered. That is, messages are received lS by the receiving process in the exact order in which the ~ending process queued for the transmission. If these guaratees cease to be met, or iE a messae cannot be ~elivered for any reason, the port enters the so-called "fatal error" state (described below) and all port connectlons are terminated.
The Datagram service does not guarantee reception, sequential reception Oe duplicate-free reception of datagrams, though the probabili~y of failure may be required to be very low. The port itself can never be the cause of such ailures; thusl if the using processs do make such guarantees for datagr~ms, then the datagram ~ervice over the port becomes equivalent to the Sequential Message service.
The Block Data Transfer service is used to move data between named buffers in host memory and a peripheral device controller. In order to allow the port to be unaware o~ mapping or memory managemnt, the "name" of a buffer is merely the bus address of the first byte of the bufeer. Since the host never directly ini~iates a block 3~73 data transfer, there is no need for the host to be aware of controller buffering.
Since the communicatiny processes are asynchronous, flow control is needed if a sending process is to be prevented from producing congestion or deadlock in a receiving process (i.e., by sending messages more quickl~
than the receiver can capture them). Flow control simply guarantees that the receiving process has buffers in which to place incoming messages; if all such buffers are full, the sending process is forced to defer transmission until the condition changes. Datagram service does not use flow control. Consequently, if the receiving process does not have an available buffer, the datagram is either processed immediately or discarded, which possibility explicitly is permitted by the rules of that service. By contrast, the Sequential ~essage service does use flow control~ Each poetential receiving process reserves, or pre-allocates, some number oE buffers into which messages may be received over its connection. l'his number is there~ore the maximum number of messages which the sender may have outstanding and unprocessed at the receiver, and it is communicated to the sender by the receiver in the form o~ a "credit" for the connection. When a sender has used up its available credit, it msut wait for the ~5 receiver to empty and make available one of its buffers.
The message credits machinery for the port of the present invention is described in detail below.
rrhe host-resident driver and the controller provide transport mechanism control facilities for dealing with:
(1~ transmission of commands and responses: (2) sequential delivery of commands; (3) asynchronous communication; (4) unsolicited responses; (5) full duplex communications; and (6) port failure recovery. rrhat is, commands, their responses and unsolicited "responses"

~3~73 (i.e., controller-to-host messages) which are not responsive to a command may occur at any time; full duplex communication is necessary to handle the bi-directional flow without introducing the delays and ~urther buffering needs which would be associated withsimplex communications. It is axiomatic that the host issues commmands in some sequence. They msut be fetched by the controller in the order in which they were queued to the transport mechanism, even if not executed in that lQ sequence. Responses, however, do not necessarily occur in the sa,ne order as the initiating commands; and unsolicited messages can occur at any time. Therefore, asynchronous communications are used in order to allow a response or controller-to-host ~nessage to be sent whenever it is ready. Finally, as to port failure recovery, the host's port driver places a timer on the port, and reinitializes the port in the event the port times out.
This machinery must allow repeated access to the same host memory location, whether for reads, writes, or any mixture Q~ the two.
The SA and IP registers (37 and 38) are in the I/0 page o~ the host address space, but in controller hardware. ~hey are used for controlling a number of ~5 fa~ets oE port operation. These registers are always read as words~ The register pair begins on a longword boundary. Both have prede~ined addressesO The IP
register has two ~unctions: ~irst, when written with any value, it causes a "hard" initialization of the port and the device controller; second, when read while the port is operating, it causes the controller to initiate polling o~ the command ring/ as discussed below. The SA
register 38 has ~our Eunctins: ~irst, when read by the host duriny initialization, it communicates data and error information relating to the initialization process;
second, when written by the host during initialization, it communicates certain host-specific parameters to the port; third, when read by the host during normal operation, it communicates status information including port - and controller-detected fatal errors; and fourth, when zeroed by the host during initialization and normal operation, it signals the port that ~he host has successfully completed a bus adapter purge in response to a port-initiated purge request.
The port driver in ~he host's operatin~ system examines the SA register regular~y to verify normal port/controller operation. A self-detected port/controller fatal error is reported in the SA
register as discussed below.

Transmission o~ Commands and Resp~nses - Overview ~ .. . _. ._ When the controller desires to send a response to the host, a several step operational se~uence takes place. This sequence is illustrated in Figs. 4~ and 4B.
Initially, the controller looks at the current entry in the response ring indicated by the response ring pointer 3~ and determines whether that entry is available to it ~by using the "ownership" bit). (Step 202.) If not, the controller continues to monitor the status of the current entry until it becomes available. Once the controller has access to the current ring entry, it writes the response into a response bu~fer in host memory, pointed to by that ring entr~, and indiates that the host now "owns" that rin~ entry by clearing and "Ownership" bit;
it also sets a "FLAG" bit, the function of which is discussed below. (Step 204.) Next, the port determines whether the ring has gone from an empty to a non-empty transition (step 206); if '73 so, a potentially interruptable condition has occurred.
Before an interrupt request is generated, however, the port checks to ensure that the "FL~G" bit is a 1 (step 208); an interrupt request is signalled only on an affirmative indication (Step 210).
Upon receipt of the interrupt request, the host, when it is able to service the interrupt, looks at the current entry in the response ring and determines whether it is "owned" by the host or controller (ie.e., whether it has yet been read by that host). (Step 212.) If it i9 owned by the controller, the interrupt request is dismissed as spurious. Otherwise, the interrupt requeSt is treated as valid, so the host porcesses the response (Step 214) and then updates its ring pointer (Step 216).
Similar actions take place when the host wants to send a command, as indicated in Fig. 5. To start the sequence, the host looks at the current command ring entry and determines whether that ring is owned by the host or controller. (Step 218) If it is owned by the ~0 contcoller, the host starts a timer (Step 220.) (provided that is the first time it is looking at that ring entry;
i~ the timer is not stopped (by the command ring entry b~coming available to the host) and is allowed to time out, a failure i5 indicated; the port is then reinitialized. (Step 222.) If the host owns the ring entry, however, it puts the packet address of the command in the current ring entry. (Step 224.) If a command ring transfer interrupt is desired (Step 226), the FLAG
bit is set - 1 to so indicate (Step 228)~ The host then sets the "ownership" bit - 1 for the ring entry to indicate that there is a command in that ring (i.e., the ho~t reads the IP register, which action is interpreted by the port as a notification that the ring contains one or more commands awaiting transmitission~; in response~

the port steps through the ring entries one by one until all entries awaiting trans,nission have been sent. (Step 232.) The host next determines whether it has additional commands to send. (Step 234) If so, the proocess is repeated; otherwise, it is ter.ninated.
In responding to the issuance of a command (see Fig.
6), the port first detects the instruction to poll (i.e., the read operation to the IP register). (Step 234) Upon detecting that signal, the port must determine whether there is a buffer available to receive a command. (Step 236) It waits until the buffer is available and then reads the current ring entry to determine whether that ring entry is owned by the port or host. (Step 238) If owned by the port, the command packet is read into a buffer. ~Step 240) The FLAG bit is then set and the "ownership" bit in the ring entry is changed to indicate host ownership (Step 242.) If not owned by the port, polling terminates.
A test is then performed for interrupt generation.
First the port determines whether the command ring has undergon~ a full to not-full transition. (Step 244) If ~o, the port next determines whether the host had the ~LAG bit set. (Step 246.) If the FL~G bit was set, an interrupt request is generated. (Step 248O) In either case, the ring pointer is then incremented. (Step 250)~
Response packets continue to be removed after the one causing an interrupt and, likewise, command packets continue to be removed by the port after poll.
_he Communications Area The communications area is alligned on a 16-bit word boundary whose layout is shown in Fig. 7. Addresses for the words of the rings are identified relative to a "ringbase" address 252. The words in regions 80B, 80C

3;~73 whose addresses are ringbase-3, ringbase-2 and ringbase-l (hereinafter designated by the shorthand [ringbase-3], etc~, where the brackets should be read as the location "whose address is") are used as indicators wnich are set to zero by the host and which are set non-zero by the port when the port interrupts the host, to indicate the reason for the interrupt. Word [ringbase-3] indicates whether ~he port is requesting a bus adapter purge; the non-zero value is the adapter channel number contained in the high-order byte 254 and derived from the triggering command. (The host responds by performing the pruge.
Purge completion is signalled by writing zeros to the SA
register).
Word 256 ~rinybase-2] signals that the command queue has transitioned from full to not-full. Its non-zero value is predetermined, such as one. Similarly, word 258 [ringbase-l] indicates that the response queue has transitioned from empty to not-empty. Its non-zero value also is predetermined (e.g., one).
Each of the command and response lists is organized into a ring whose entries are 32-bit descriptors.
Thereeore, Eor each list, after the last location in the 11st has been addressed, the next location in sequence to be addressed is the Eirst location in the list. That Z5 is, each list may be addressed by modulo-N counter, where N is the number of entries in the ringO The length of each ring is determined by the relative speeds with which the host and the port/controller generate and process messages; it is unrelated to the controller command limit. At initialization time, the host sets the ring lengths.
Each ring entry, or formatted descriptor, has the layout indicated in Fig. 8. In the low-order 15-bits (260), the least significant bit, 262, is zero; that is~

32'73 the envelope address [text + 0] is word-ali~ned. The remaining low-order bits are unspecified and vary with the data. In the high-order portion 26~ of the descriptor, the letter "U" in bits 266 and 268 represent a bit in the high-order portion of an 18-bit UNIBUS (or other bus) address. Bits 270-276, la~elled "~", are abvailable for extending the high-order bus address; they are zero for UNIBUS systems. The most significant bit, 27~, contains the "ownership" bit ("O") referred to 1~ above; it indicates whether the descriptor is owned by the host (0 - l), and acts as an interlock protecting the descriptor against premature access by either the host or the port. The next lower bit, 280, is a "FLAG" bit (labelled "F") whose meaning varies depending on the state of the descriptor. When the port returns a descriptor to the host, it sets F = 1, indicating that the descriptor is full and points to response. On the other hand, when the controller acquires a descriptor from the host, F = l indicates that the host wants a ring transition inteerupt due to this slot. It assumes that tran~ition interrupts were enabled during initialization and that this particular slot triggers the ring tran~ltion. F = 0 means that the host does not want a transitlon host interrupt, even if interrupts were enabled during lnitialization. The port always sets F =
1 when returning a descriptor to the host; thereEore, a host desiring to override right transition interrupts must always clear the FLAG bit when passing ownership of a descriptor to th~ port.
Message Enve~o~
. _ .
As stated above, messages are sent as packets, with an envelope address pointing to word [text ~ 0] of a 16-blt, word-aligned message envelope formatted as shown in Flg. 9.

3Z,73 The MSG LENGT~I field 282 indicates the length of the message text, in bytes. For commands, the length equals the size of the command, starting with [text _ 0]. For responses, the host sets the length equal to the size of the response buffer, in bytes, starting with [text ~ 0].
By design, the minimum acceptable size is 60 bytes of message text (i.e.l 64 bytes overall).
The message length field 282 is read by the port before the actual transmission of a response. The port may wish to send a response longer than the host can accept, as indicated by the message length field. In that event, it will have to break up the message into a plurality of packets of acceptable size. Therefore, having read the message length field, the controller then sends a response whose length is either the host-specified message length or the length of the controller's response, if smaller. The resulting value is set into the message length field and sent ot the host with the message packet. Therefore, the host must re-initialize the value of tha ~ield for each proposedreponse.
The message text is contained in bytes 284a-284m, labelled MBj. The "connection id" field 286 identifies the connection serving as source o, or destination for, the message in question. The "credits" field 288 gives the credit value associated with the message, which is discussed more fully below. The "msgtyp" field 2~0 indicates the message type. For example, a zero may be used to indicate a sequential message, wherein ~he credits and message length fields are valid. A one may indicate a datagram, wherein the credits field must be zero, but message length is valid. Similarly, a two may indicate a credit notification, with the credits field valid and the message length field zero.

~ ~ ~3~73 ~essa_e Credits A credit-based message limit mechanis.n is employed for command and response 10w control. The credits field 288 of the message envelope supports the credit-accounting algorithm. The controller 30 has a buffer 36 for holding up to M commands awaiting execution. In its first response, the controller will return in the credits field the number, M, of commands its buffer can hold. This number is one more than the controller's acceptance limit for non-immediate commands; the "extra" slot is provided to allow tht host always to be able to issue an i~nediate class command. If the credit account has a value of one, then the class driver may issue only an immediate-type command. If the account balance is zero, the class driver may not issue any co,nmands at all.
The class driver remembees the number M in its "credit account~'. Each time the class driver queues a command, it decrements the credit account balance by one.
Conversely, each time the class driver receives a response, it increments the credit account balance by the value contained in ~he credit~ field of that response.
For unsolicited responses, this value will be zero, since no command was executed to evoke the response; for soliclted responses, ik normally will be one, since one commancl yenerally glves rise to one response.
For a controller haviny M greater than lS, responses beyond the first will have credits greater than one, allowing the controller to "walk" the class driver's credit balance up to the correct value. For a well-behaved class driver, enlarging the command rin~ beyondthe value M-~l provides no perforlnance benefits; in this situation co~nand ring transition in~errupts will not occur since the class driver will never fill the command ring~

3~'73 The Owner ~

The ownership bit 278 in each ring entry is like the flag on an old-fashioned mailbox. The postman raised the flag to indicate that a letter had been put in the box.
When the box was emptied, the owner would lower the flag.
Similarly, the ownership bit indicates that a message has been deposited in a ring entry, and whether or not the ring entry (i.e., mailbox) has heen emp~ied. Once a message is written to a ring entry, that message must be emptied before a second message can be written over the first~
For a command descriptor, the ownership bit "O" is changed from zero to one when the host has filled the descriptor and is releasing it to the port. Conversely once the port has emptied the command descriptor and is returning the empty slot to the host, the ownership bit is changed from one to zero. That is, to send a command the host sets the ownership bit to one; the port clears it when the co~nand has been received, and returns the empty slot to the host.
~ o guarantee that the port/controller sees each command in a ti,nely fashlon, whenever the host inserts a command in the command ring, it must read the IP
regi~ter. This forces the port to poll iE it was not already polling.
For a response descriptor, when the ownership bit O
undergoes a transition Erom one to zero, that means that the port has Eilled the descriptor and is releasing it to the host. The reverse transition means that the host has emptied the response descriptor and is returning the empty slot to the port. Thus, to send a response the port clears the ownership bit, while the host sets it when the response has been received, and returns the empty slot to the port.
Just as the port must poll for commands, the host must poll Eor responses, particularly because of the possibility of unsolicited responses.

Interrupts The transmission of a message will result in a host interrupt if and on~y if interrupts were armed (i.e., ~nabled) suitably during initialization and one of the following three conditions has been met: (1) the message was a command with flag ~80 equal to one (i.e., F = 1), and the fetching of the col~nand by the port caused the command ring to undergo a transition from full to not-full; (2) if the message was a response with ~ = 1 and the depositing o~ the message by the port caused the response ring to make a transition froln empty to not-empty; or (3) the port is interfaced to the host via a bus adapter and a command required the port/controller to re-access a given location during data transfer. (The latter interrupt means that the port/controller i5 requesting the host to purge the indicated channel of the bus adapter.) Port Pollin~

The reading of the IP register by the host causes the port/controller to poll for command~s. The port/controller begins reading commands out of host memory; if the controller has an internal command buffering capability, it will write commands into the bufEer if they can't be executed immediately~ The port continues to poll for full command slots until the ~ ~3~73 command ring is found to be empty, at which time it will cease polling. The port will resume polling either when the controller delivers a response to the host, or when the host reads the IP register.
Correspondingly, response polling for empty slots continues until all commands buffered within the controller have been completed and the associated responses have been sent to the host.

_ st Polling Since unsolicited responses are possible, the host cannot cease polling for responses when all outstanding commands have been acknowledged, though. If it did, an accumulation of unsolicited messages would first saturate the response ring and then any controller internal lS message buEfers, blocking the controller and preventing it from processing additional commands. Thus, the host must at least occassionally scan the response ring, even when not expecting a response. One way to accomplish this is by using the ring transition interrupt facility cle5cribed above; the host also would remove in sequence fro~ reqponse ring as many responses as it finds there.

Data Transmission ___ _ Data transmission details are controller-dependent.
There are certain generic characteristics, however.
Data transEer commands are assu,ned to contain buffer deficrip~ors and byte or word counts. The buffers serve as sources or sinks for the actual data transfers, which are effected by the port as non-processor (~PR or DMA) transfers under command-derived count control to or from the specified buEfers. A buffer descriptor begins at the first word allocated for this purpose in the formats of higher-level commands. When used with the UNIBUS
interconnection, the port employs a two-word buffer descriptor format as illustrated in Fig. 10. As shown herein~ the bits in the low-order buffer address 292 are message-dependent. The bits labelled "U" (294, 296) in the high-order portion 298 of the bufer descriptor are the high-order bits of an 13-bit uNIsus address. The bits 300-306, labelled "~", are usable as an extension to hte high-order UNIBUS address, and are zero for UNIBUS
systems.
Repeated access to host memory locations must be allowed for both read and write operations, in random sequence, if the interfaces are to support higher-level protocol functions such as transfer restarts, compares, and so forth. In systems with buffered bus adapters, which require a rigid sequencing, this necessitates purging of the relevant adapter channel prior to changing from read to write, or vice versa, and prior to breaking an addressing sequence. Active cooperation of the host CPU is required for this action. The port signals its de~ire ~or an adapter channel purge, as indicated above under the heading "The Communications Area". The host per~orms the purge and writes zeros to the SA register 38 to signal compl~tion.

Transrnission Errors Four classes oE transmission errors ahve been considered in the design of this interface: (1) failure to become bus mater; (2) failure to become interrupt master; (3) bus data timeout error and (4) bus parity error.

~3~

When the port (controller) atternpts to access host memory, it must first become the "master" of bus 60. To deal cleanly with the possibility of this exercise failing, the port sets up a corresponding "last fail"
response packet (see below) before actually requesting bus access. Bus access is then requested and if the port timer expires, the host will reinitialize the port/controller. The port will then report the error via the l'last fail'i response packet (ass~ning such packets were enabled during the reinitialization).
A failure to become interrupt master occurs whenever the port attempts to interrupt the host and an acknowledgment is not forthcoming. It is treated and reported the same as a failure to become bus mater, lS although the contents of its last fail response will, of course, be different.
Bus data timeout errors involve failure to complete the transfer of control or data messages. If the controller retires a transfer after it has failed once, and a second try also fails, then action i5 taken responslve to the detection of a persistent error. If th~ unsuccessful operation was a control transfer, the port writes a failure code into the SA register and then terminates the connection with the host. Naturally, the 2S controller will have to he reinitiali2ed. On the other hand, iE the unsucessful operation was a data transfer, the port/controller stays online to the host and the ~ailure is reported to the host in the reponse packet for the involved operation. Bus parity errors are handled the same as bus data timeout errors.

Fatal ~rrors Various fatal errors may be self-detected by the port or controller. Some of these may also arise while 32~73 the controller is operating its attached peripheral device(s). In the event of a fatal error, the port sets in the SA register a one in its most significant bit, to indicate the existence of a ~atal error, and a fa~al error code in bits 10-0.

Inter_upt _ neration Rate Under steady state conditions, at most one ring interrupt will be generated for each opearation (i.e., command or response transmission). Under conditions of low I/~ rate, this will be due to response ring transitions from empty to not-empty; with high I/~ rate, it will be due to command ring transltions from full to not-full. If the operation rate fluctuates considerably, the ratio of interrupts to operations can be caused to d~cline ~rom one-to-one. For example, an initially low but rising operation rate will eventually cause both the command and response rings to be partially occupied, at which point interrupts will cease and will not resume until the col~and ring fills and begins to make full to ~0 not-Eull transitions. This point can be staved off by increasing the permissible depth of the command ring.
GeneralJy, the permissible depth of the response ring will have to be increased also, since saturation of the re~ponse ring wlll eventully cause the controller to be unwilling to fetch additional commandsO At that point, the command ~ueue will saturate and each fetch will generate an interrupt.
Moreover, a full condition in either ring implies that the source of that ring's entries is temporarily choked off. Conseq~ently, ring sizes should be large enough to keep the incidence of full rings small. For the cvmmand ring, the optimal si~e depends on the latency in the polling oE the ring by the controller. For the response ring, the opti,nal size is a function of the latency in the ring-emptying softw3re.

Initialization A special initialization procedure serve to (1) identify the parameters of the host-resident co~nunications region to the port; (2) provide a confidence check on port/controller integrity; and (3) bring the port/controller online to the host.
The initialization process starts with a "hard"
initialization during which the port/controller runs some preliminary diagnostics. Upon successful completion of those diagnostics, there is a four step procedure which takes place. First, the host tells the controller the lengths of the rings, whether initialization interrupts are to be armed (i.e., enabled) and the address(es) of the intercupt vector(s)~ The port/controller then runs a complete intecnal integrity check and signals either succes~ or failure. Second, the controller echos the ring lengths, and the host sends the low-order portion of the ring-base address and indicates whether the host is one whlch requires purge interrupts. Third, the controller sends an echo oE the interrupt vector address(es) and the initialization interrupt arming signal. The host then replies with the high-order portion of the ringbase adc~ress, along with a signal which conditionally triggers an immediate test of the polling and adapter purge furlctions oE the port. fourth, the port tests the ability of the input/output bus to perform nonprocessor (NPR) transfers. If successful, the port zeros the entire communications area and signals the host that initialization is complete. The poct then ~3~Z ~3 awaits a signal ~rom the host that the con~roller should begin normal operation.
At each step, the port informs the host of either success or failure~ Success leads to the next initialization step and failure causes a restart of the initialization sequence. The echoing of information to the host is used to check all bit positions in the transport mechanism and the IP and SA registers.
The SA register is heavily used during initialization. The detailed format and meanin~ of its contents depend on the initialization step involved and whether information is being read from or written into the register. When being read, certain aspects of the SA
format are constant and apply to all steps. This constant SA read format is indicated in Fig. 11. ~s seen there, the meaning of bits 15-11 of SA register 38 is constant but the interpretation of bits 10-0 varies. The S4-Sl bits, 316-310, are set separately by the port to indicate the initialization step number which the port is ready to perform or is performing. The Sl bit 310 is set ~or initialization step l; the S2 bit 312, for initialization step 2, etc. If the host detects more than one of the Sl-S4 bits 316-310 set at any time, it restarts the initialization of the port/controller; the 2S second time thi~ happens, the port/controller is presumed to be malfunctioning. The SA register's most significant bit 318, labelled ER, normally is zero; it may be set to the value of 1 if either a port/controller-based diagnositic test has failed, or there has been a fatal error. In the event of such a failure or error, bits 10-0 comprise a field 320 into which an error code is written; the error code may be either por~-generic or controller-dependent. Consequently, the host can determine not only the nature of an error but also the 3Z'73 step of the initialization during which it occurred. If a fatal error is detected during hard initialization, prior to the start of initialization step 1, the ER bit is set to a value of 1 and no step bit is set.
The occurrence of an initialization error causes the port driver to retry the initialization sequence at least once .
Refeeence will now be made to Figs. 12A-l ~ , wherein the details of the initialization process are illustrated.
The host begins the initialization sequence either by performing a hard initialization o the controller (this is done either by issuing a bus initialization (INIT) command (Step 322) or by writing zeros to the IP
register. The port guarantees that the host reads zeros in the SA reglster on the next bus cycle. The controller, upon sensing the initialization order, runs a predetermined set of diagnostic routines intended to ensure the minlmum integrity necessary to rely on the rest of the sequence. (Step 324) Initialization then sequences through the four above-listed steps.
At the begi.nning of each initialization step n, the port clears bit Sn-l before setting bit Sn; thus, the host will never see bits Sn-l and Sn set simultaneously.
From the viewpolnt oE the hos~, step n begins when reading the SA register resul~s in the transition of bits S n from 0 to 1. Each step ends when the next step begins, and an interrupt may accompany the step change if interrupts are enabled.
Each of initialization steps 1 - 3 is timed and if any of those steps fails to complete within the alloted time, that situation is treated as a host-detected fatal error. By contrast, there is no explicit signal for the completion of initialization step 4; rather, the host 3~73 observes either that controller operation has begun or ~hat a higher-level pro~ocol-dependent timer has expired.
The controller starts initialization step 1 by writing to the SA register 38 the pattern indicated in S Fig. 12A. (Step 326j Bits 328-332 are controller-dependent. The "NV" bit, 332, indicates whether the port supports a host-settable interrupt vector address; a bit value of 1 provides a negative answer. The "~B" bit, 330, indicates whether the port supports a 22-bit host bus address; a 1 indicates an affirmative answer. The "DI", bit 328, indicates whether the port implements enhanced diagnostics, such as wrap-around, purge and poll tast; an affirmative answer is indicated by a bit value of 1.
The host senses the setting of bit 310, the Sl bit, and reads the SA register. (Step 334.) It then responds by writing into the SA register the pattern shown in step 336. The most significant bit 338 in the SA register 38 is set to a 1, to guarantee tha~ the port does not interpret the pattern as a host "adapter purge coi~plete"
response (after a spontaneous reinitialization). The WR
bit, 340, indicates whether the port should enter a diagnostic wrap mode wherein it will echo messages sent to it; a bit value of 1 will cause the prot to enter that mode. The port will ignore the WR bit iE DI - 0 at the heginning of initialization step 1. Field 342, comprising bits 13-11 and labelled "C RNG LNG," indicates the number of entries or slots in the command ring, expressed as a power of 2. Similarily, field 344, comprising bits 10-8 and labelled "R RNG LNG", represents the number of response ring slots ti.e., the length of the response ring), also expressed as a power of 2. Bit 346, the number 7 bit in the register, labelled "IE", indicates whether the host is arming interrupts at the ~3~73 completion of each of steps 1 - 3. An affirmative answer is indicated by a 1. Finally, field 348, comprising register bits 6-0, labelled "INT Vector", contains the address of the vector to which all interrupts will be directed, divided by 4. If this address is 0, then port interrupts will not be generated under any circumstances.
If this field is non-zero the controller will generate initialization interrupts (fi IE is set) and purge interrupts (if PI is set), and ring transition interrupts depending on the FLAG bit setting of the ring entry causing the transition.
The port/controller reads the SA register after it has been written by the host and then begins to run its full inte~rity check diagnostics; when finished, it conditionally interrupts the host as described above.
(Step 350).
This complëtes step 1 of the initialization process.
Next, the controller writes a pattern to the SA register as indicated in Fig. 12B. (Step 352.) ~s shown there, bits 7-0 of the SA regiqter echo bits 15-8 in step 336.
I'he response and command ring lengths are echoed in ~telds 35~ and 356, respectively; bit 358 echoes the host's WR bit and bit 360 echoes the host's bit 15. The port type is indicated in field 362, register bits 10-8, and blt 12 i9 set to a 1 to indicate the beginning of step ~.
The host reads the SA register and valldates the echo when it sees bit S2 change state. (Step 364.~ If everything matches up, the host then responds by writing into teh SA register the pattern indicated in step 366.
Field 368, comprising SA register bits 15-1, labelled "ringbase lo address", represents the low-order portion o~ the address of the word [ringbase ~ 0] in the co~nunications area. While this is a 16-bit byte ~ ~3~73 3~

address, its lowest order bit is 0, implicitly. The lowest order bit of the SA register, 370, indicated as "PI", when set equal to l, means that the host is requesting adapter purge interrupts.
The controller reads the low ringbase address (step 3721 and then writes înto the SA register the patteen indicated in step 374, which starts initialization step 3 by causing bit 376, the S3 bit, to undergo a transition ~rom 0 to ]. The interrupt vector field 348 and interrupt enabling bit 346 from step 336 are echoed in SA
register bits 7-0.
Next, the host reads the SA register and validates the echo; if the echo did not operate properly, an error is signalled. (Step 378). Assuming the echo was valid, the host then writes to the SA register the pattern indicated in step 380. bit 382, the most significant bit, labelled "PP", is written with an indication of whether the host is requesting execution of "purge" and "poll" tests (described elsewhere); an affirlnative answer is signaled by a l. The port will ignore the PP bit if the DI bit 3~8 was zero at the beginning of step l. The "ringbase hi address" field 384, comprising SA register bits l4-0, is the high-portion of the address [ringbase +
O] .
The port then reads the SA register; if the PP bit has been qet, the port writes zeroes into the SA
register, to signal its readiness for the test. (Step 386). The host detects that action and itself writes zeroes ~or anything else) to the SA register, to sim~late a "purge completed" host action. (Step 388.) ~fter the port verifies that the host has written to the SA
register (Step 390.), the host reads, and then disregards, the IP register. Step 392.) This simulates a "start polling" command from the host to the po~t. The ~3;~

port verifies that the IP register was read, step 394, before the sequence continues. The host is given a predetermined time from the ~ime the SA register was first written during initialization step 3 within which to complete these actions. (Step 396) If it fails to do so, initialization stops. The host may then restart the initialization sequence from the beginning~
Upon successful completion of initalization step 3, the transition to initialization step 4 is effecuated when the controller writes to the SA register the pattern indicated in step 398. Field 400, comprising bits 7-0 of the SA register, contains the version number of the port/controller microcode. In a microprogra,nmed controller, the functionality of the controller can be altered by changing the programming. It is therefore important that the functionality of the host with the ability to recognize which versions of the controller microcode are compatible with the host and which are not.
Therefore, the host checks the controller microcoder verslon in field ~00 and confirms that the level of ~unctionality ls appropriate to that particular host.
(Step 402.) The host responds by writing into the SA
register the pattern indicated in step 404. It is read by the controller in step 405 and 406 and the operational microcode is then started.
The "burst" field in bits 7-2 of the SA register is one less than the maximum number of longwords the host is willing to allow per NPR (non-processor involved) transfer. The port uses a default burst count if this field is zero. The values of both the default and the maximum the port will accept are controller-dependent.
Ie the "LF" bit 408 is set equal to 1, that indicates that the host wants a "last fail" response packet when inltlallzation is completed. The state of the LF bit 408 does not have any effect on the enabling/disabling of unsolicited responses. The meaning of "last fail" is explained below. The "~O" bit 41~ indicates whether the controller should enter its functional microcode as soon as initialization comp]etes. If GO = 0, when initialization completes, the prot will continue to read the SA register until teh host forces bit 0 of that re~ister to make the transition from 0 to 1.
At the end of initialization step 4, there is no explicit interrupt request. Instead, if interrupts were enabled, the next interrupt will be due either to a ring transition or to an adapter purge request.

D agnostic Wrap Mode Diagnostic Wrap Mode (~WM) provides hos~-based dia~nostics with the means for verifying the lowest levels of host-controller communication via the port. In DWM, the port attempts to echo in the SA register 33 any data written to that register by the host. DWM is a special path throu~h initialization step l;

2~ initialization steps 2-4 are suppressed and the port/controller is left disconnected from the host. A
hard initlalization terminates DWM and, if the results o DWM are satis~actory, it is then bypassed on the next Lnitlalization sequence.

Last Fail __ "Last fail" is the name given to a unique response packet which is sent to the port/controller detected an error during a previous "run" and the LF bit 405 was set in step 404 of the current initialization sequence. It is sent when initialization completes. The format of this packet is indicated in Fig. 13. The packet starts with 64 bits o zeroes in a pair of 32 bit words 420.

~ 3~
~1 ~ext there is a 32 bit ~ord 422 consis~ing of a lower-order byte 422~ and a higher-order byte 422B, each of which has unique numerical contents. Wor~ 422 is followed by a double word 424 which contains a controller identiEier. The packet is conclu~ed by a sin~le ~ord 426. The higher-order byte ~26A of word 425 contains an error code. The lower half of word 426 is broken into a pair of 8 bit fields 42Z~ and 425~. Field 426B con~ains the controller's hardware revision number. Field 426C
contains the controller's soft~are, firinware or miceocode revision nu,nber.

Recap It should be apparent fro,n the foregoing description that the present invention provides a versatile and powerful interEace between host computers and peripheral devices, particularly secondary mass storage subsystelns.
This interface supports asynchronous packet type command and response exchanges, while obviating the need for a hardware-interlocked bus and greatly re~ucing the illtqrrupt load on the host processor. The efficiency of both input/output arld processor operation are thereby enhanced.
A pair of registers in the controller are used to trans~er certain status, co~nand and parametric 25 inFormation between the peripheral controller and host.
These registers are exercised heavily during a four step inltialization process. The meanings of the bits of these registers change according to the step involved.
8y the co~pletion of the initialization sequence, every bit of the two registers has been checked and its proper operation confirmed. Also, necessary para,netric information has been exchanged ~such as ring lengths) to ~ ~ ~3~73 allow the host and controller to communicate commands and responses.
Although the host-peripheral communications interface of the invention comprises a port which, effectively, is control-ler-based, it nevertheless is largely localized at the host.
Host-side port elements include: the command and response rings;
-the ring transition indicators; and, if employed, bus data purge control. At the controller, the port elements include: command and response buffers, host command and response ring pointers, and the SA and IP registers.
Having thus described the present invention, it will now be apparent that various alterations, modi~ications and improve-ments will readily occur to those skilled in the art. This dis-closure is intended to embrace such obvious alterations, modifi-cations and improvements; it is exemplary, and not limiting. This invention is limited only as required by the claims which follow.

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Claims (18)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. In a data processing system which includes first and second processors, a memory to which information can be written and from which information can be read by each of said processors, such memory having a plurality of locations for storing said information, and bus means for interconnecting the first and sec-ond processors and memory to enable communications therebetween, said bus means being of the type which has no hardware interlock capability which is usable by each of said processors to selec-tively prevent the other of said processors from accessing said memory locations, the improvement comprising: the first and second processors being adapted to employ a portion of said memory as a communications region accessible by both of said processors, so that all commands and responses can be transmitted from one of said processors to the other of said processors through such portion of memory; the communications region of memory including pair of ring buffers; a first one of said ring buffers buffering the transmission of messages issued by the first processor and a second one of said ring buffers buffering the reception of mes-sages transmitted by the second processor; each of said ring buf-fers including a plurality of memory locations adapted to receive from the associated transmitting said processor a descriptor signifying another location in said memory; for said first ring buffer, the location signified by such descriptor being a location containing a message for transmission to the second processor;
for said second ring buffer, the location signified by such des-criptor being a location for holding a message from the second processor; and the first and second processors further being adapted to control access to said communications region such that information written therein by one of said processors may not be read twice by the other processor and a location where information is to be written by one of the processors may not be read by the other processor before said information has been written, so that race conditions are prevented from developing across said bus means and messages are transmitted from said ring buffers in the same sequence as that in which they are issued by the processors, while each of the processors is permitted to operate at its own rate, independent of the other processor.

2. The apparatus of claim 1 wherein said ring buffers are adapted to permit the first processor to send a plurality of commands in sequence to the second processor via the bus means, and to permit the second processor to send responses to those commands to the first processor via the bus means.

3, The apparatus of claim 1 or claim 2 wherein the first processor is a host computer's central processor, the second pro-cessor is a processor in a controller for a secondary storage device, and the bus means includes an input/output bus for inter-connecting said host computer with said secondary storage device.

4. The apparatus of claim 1 or claim 2 wherein there is associated with each ring buffer entry a byte of at least one bit, termed the ownership byte, whose state indicates the status of that entry; for each entry of the first ring buffer, the first processor being adapted to place such entry's ownership byte in a predetermined first state when a descriptor is written into said entry, and the second processor being adapted to cause the state of the ownership byte to change when such descriptor is read from said entry; for each entry of the second ring buffer, the second processor being adapted to place such entry's ownership byte in a predetermined first state when a descriptor is written into said entry, and the first processor being adapted to cause the state of the ownership byte to change when such descriptor is read from said entry; the first and second processors being adapted to read ring buffer entries in sequence and to read each ring buffer entry only when the ownership byte of said entry is in said predetermined first state, whereby an entry may not be read twice and an entry may not be read before a descriptor is written thereto.

5. The apparatus of claim 1 or claim 2 wherein the second processor is a processor in a controller for a secondary storage device and the controller further includes pointer means for keeping track of the current first and second ring buffer entries.

6. The apparatus of claim 1 or claim 2 further including means for reducing the generation of processor interrupt requests to the first processor in the sending of commands thereby and responses thereto, such that interrupt requests to said processor are generated substantially only when an empty ring buffer becomes not-empty and when a full ring buffer becomes not-full.

7. The apparatus of claim 1 or claim 2 wherein the size of each ring buffer is communicated by said first processor to the second processor at the time of initializing a communications path between them.

8. The apparatus of claim 1 or claim 2 wherein the proces-sors communicate by sending message packets to each other, and further including: the first ring buffer being adapted to hold up to M commands to be executed; an input/output device class driver associated with the first processor for sending commands to and receiving responses from an input/output device; the second processor being adapted to provide to the class driver in its first response packet the number M of commands of a predeter-mined length which said buffer can hold; the class driver being adapted to maintain a credit account having a credit account balance indicative of the number of commands the buffer can accept at any instant; the credit account balance initially being set to equal M and being decremented by one each time the class driver, issues a command and being incremented by the value; the second processor further being adapted to provide to the class driver, with each response packet, a credit value representing the number of commands executed to evoke the response; the class driver incrementing the credit account balance by said credit value; and the first processor and class driver being adapted so as not to issue any commands when the credit account balance is zero and further being adapted to issue only commands which are immediately executed when the credit account balance is one.

9. The apparatus of claim 1 or 2 wherein there is associated with each ring buffer entry a byte of at least one bit, termed the ownership byte, whose state indicates the status of that entry;
for each entry of the first ring buffer, the first processor being adapted to place such entry's ownership byte in a predeter-mined first state when a descriptor is written into said entry, and the second processor being adapted to cause the state of the ownership byte to change when such descriptor is read from said entry; for each entry of the second ring buffer, the second pro-cessor being adapted to place such entry's ownership byte in a predetermined first state when a descriptor is written into said entry, and the first processor being adapted to cause the state of the ownership byte to change when such descriptor is read from said entry; the first and second processors being adapted to read ring buffer entries in sequence and to read each ring buffer entry only when the ownership byte of said entry is in said pre-determined first state, whereby an entry may not be read twice and an entry may not be read before a descriptor is written thereto, wherein said ownership byte is the most significant bit in each descriptor.

10. In a data processing system which includes first and second processors, a memory adapted to be used by said proces-sors, and bus means for interconnecting the first and second pro-cessors and memory to enable communications therebetween, said bus means being of the type which has no hardware interlock capability which is usable by each of said processors to selec-tively prevent the other of said processors from accessing at least a portion of said memory/ the improvement comprising: at least a portion of said memory being adapted to serve as a com-munications region accessible by both of said processors all commands and responses being transmitted from one processor to the other through such portion of memory; means for controlling access to information in said communications region whereby in-formation written therein by one of said processors may not be read twice by the other processor and wherein a location where information is to be written by one of the processors may not be read by the other processor before said information has been written; the communications region of memory including a pair of ring buffers; a first one of said ring buffers being adapted to buffer the transmission of messages issued by the first pro-cessor and a second one of said ring buffers being adapted to buffer the reception of messages transmitted by the second proces-sor; each of said ring buffers including a plurality of memory locations adapted to receive from an associated one of said pro-cessors a descriptor signifying another location in said memory;
for said first ring buffer, the location signified by such des-criptor being a location containing a message for transmission to the second processor; and for said second ring buffer, the location signified by such descriptor being a location for holding a mes-sage from the second processor, so that race conditions are pre-vented from developing across said bus means and messages are transmitted from said ring buffers in the same sequence as that in which they are issued by the processors, while each of the processors is permitted to operate at its own rate, independent of the other processor.

11. The apparatus of claim 10 wherein said ring buffers are adapted to permit the first processor to send a plurality of commands in sequence to the second processor via the bus means, and to permit the second processor to send responses to those commands to the first processor via the bus means.

12, The apparatus of claim 10 or claim 11 wherein the first processor is a host computer's central processor, the second pro-cessor is a processor in a controller for a secondary storage device, and the bus means includes an input/output bus for inter-connecting said host computer with said secondary storage device.

13. The apparatus of claim 10 or claim 11 wherein there is associated with each ring buffer entry a byte of at least one bit, termed the ownership byte, whose state indicates the status of that entry; for each entry of the first ring buffer, the first processor being adapted to place such entry's ownership byte in a predetermined first state when a descriptor is written into said entry, and the second processor being adapted to cause the state of the ownership byte to change when such descriptor is read from said entry; for each entry of the second ring buffer, the second processor being adapted to place such entry's ownership byte in a predetermined first state when a descriptor is written into said entry, and the first processor being adapted to cause the state of the ownership byte to change when such descriptor is read from said entry; the first and second processors being adapted to read ring buffer entries in sequence and to read each ring buffer entry only when the ownership byte of said entry is in said predetermined first state, whereby an entry may not be read twice and an entry may not be read before a descriptor is written thereto.

14. The apparatus of claim 10 or claim 11 wherein the second processor is a processor in a controller for a secondary storage device and the controller further includes pointer means for keeping track of the current first and second ring buffer entries.

15. The apparatus of claim 10 or claim 11 further including means for reducing the generation of processor interrupt requests to the first processor in the sending of commands thereby and responses thereto, such that interrupt requests to said processor are generated substantially only when an empty ring buffer becomes non-empty and when a full ring buffer becomes not-full.

16. The apparatus of claim 10 or claim 11 wherein the size of each ring buffer is communicated by said first processor to the second processor at the time of initializing the communica-tions path between them.

17. The apparatus of claim 10 or claim 11 wherein the pro-cessors communicate by sending message packets to each other, and further including: a buffer associated with the second pro-cessor for holding up to M commands to be executed; an input/
output device class driver associated with the first processor for sending commands to and receiving responses from an input/out-put device; the second processor being adapted to provide to the class driver in its first response packet the number M of commands of a predetermined length which said buffer can hold; the class driver being adapted to maintain a credit account having a credit account balance indicative of the number of commands the buffer can accept at any instant; the credit account balance initially being set to equal M and being decremented by one each time the class driver issues a command and being incremented by the value;
the second processor further being adapted to provide to the class driver, with each response packet, a credit value represen-ting the number of commands executed to evoke the response; the class driver incrementing the credit account balance by said credit value; and the first processor and class driver being adapted so as not to issue any commands when the credit account balance is zero and further being adapted to issue only commands which are immediately executed when the credit account balance is one.

18. The apparatus of claim 10 or claim 11 wherein there is associated with each ring buffer entry a byte of at least one bit, termed the ownership byte, whose state indicates the status of that entry; for each entry of the first ring buffer, the first processor being adapted to place such entry's ownership byte in a predetermined first state when a descriptor is written into said entry, and the second processor being adapted to cause the state of the ownership byte to change when such descriptor is read from said entry; for each entry of the second ring buffer, the second processor being adapted to place such entry's owner ship byte in a predetermined first state when a descriptor is written into said entry, and the first processor being adapted to cause the state of the ownership byte to change when such des-criptor is read from said entry; the first and second processors being adapted to read ring buffer entries in sequence and to read each ring buffer entry only when the ownership byte of said entry is in said predetermined first state, whereby an entry may not be read twice and an entry may not be read before a descriptor is written thereto; wherein said ownership byte is the most significant bit in each descriptor.