CA1109563A - Input/output processing system utilizing locked processors - Google Patents

Input/output processing system utilizing locked processors

Info

Publication number
CA1109563A
CA1109563A CA289,452A CA289452A CA1109563A CA 1109563 A CA1109563 A CA 1109563A CA 289452 A CA289452 A CA 289452A CA 1109563 A CA1109563 A CA 1109563A
Authority
CA
Canada
Prior art keywords
input
output
signals
processing unit
sequence
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA289,452A
Other languages
French (fr)
Inventor
John M. Woods
Marion G. Porter
Donald V. Mills
Garvin W. Patterson
Edward F. Weller, Iii
Earnest M. Monahan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Inc filed Critical Honeywell Information Systems Inc
Application granted granted Critical
Publication of CA1109563A publication Critical patent/CA1109563A/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/1629Error detection by comparing the output of redundant processing systems
    • G06F11/1641Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0745Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in an input/output transactions management context
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/079Root cause analysis, i.e. error or fault diagnosis
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/1629Error detection by comparing the output of redundant processing systems
    • G06F11/165Error detection by comparing the output of redundant processing systems with continued operation after detection of the error
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/20Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2053Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where persistent mass storage functionality or persistent mass storage control functionality is redundant
    • G06F11/2089Redundant storage control functionality
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing

Abstract

ABSTRACT OF THE DISCLOSURE

An input/output system includes at least a pair of processing units and system interface apparatus for com-paring the results produced by both halves of the pair during normal system operation under control of a main or host processing unit. The system interface apparatus in-cludes comparison circuits for detecting a mis-compare between the results of each half and sequence control logic circuits which are conditioned upon the occurrence of a mis-compare to unlock or deconfigure the pair to establish in a predetermined manner which of the proces-sing units is faulty. The system interface apparatus, following signal indications of a certain minimum confi-dence within a processing unit, continues testing of the processor using stored diagnostic routines to determine which one of the processing units is good. It then stops the operation of the bad processing unit and enables sys-tem operation to be continued with the good processing unit. To ensure reliable processing, both halves of the pair are tested when a miscompare cannot be related to an error condition associated with one of the pair notwith-standing the fact that the first processing unit tests well.
Following reconfiguration, the operating system associated with the system provides periodic testing of the good pro-cessing unit, thereby ensuring that the system continues to operate reliably.

Description

BACKGROUND OF THE I~VENTION

i~ld o~ ~se The px~ en~ invent:lon rela~es ~o input/outpu~ syst~m~
and, mor~ particularly, to sys~ms w.hich includ~ duplias~e S units for improved raliabilityO

Prior ~rt It i~ well-known t~ provide duplicate arithmetic units whose outputs are connected to compari~on clrcuits for checking whether ~he re~ult~ are correet. SUGh ar-xangements have been utilized in the prior art primarily ~or the purpose of error detection, Accordingly, the two units operated as a single unit and t~e single unit was, therefore, regarded a~ having failed in the event o~ a mis-compare in resultsO Othex prior art ~ystems have em-ployed triplica~e computes sy~ems which connec~ ~o majority logic cîrcu~ts ~or detecting ~he presence of error~ and for establishing the failed sy~em upon the occurrenc~ of an error. ~hese systems, while exceedingly reliablej normally axe quite eostly and complex.
Accordingly/ it is a~ object o~ the pxesent invention to provide a proce~ing~sys~m which has a high degree o~ ~
r~liability and ha a miniml~m o~ complexity~
. Xt is a more spe ific obj~ct of ~he pre~ent invention to pr~vide an inputfoutput processing sy~t~m in which it is .
. 2S po~sibLe to detect which processor within J pair h~ failed~

"
, .
- ' ' :, . ' : .
~;

SUMM~R~ OF T~E INVENTION

The abo~e objects ar~ achieved in a preferred embodi-ment of the present in~e~io~ which compri~as a~ leas~ a pair of inpu~ou~put proce~sing uni~s having ~heir outpu~s coupled to compairson circui~s included within a sy~tem interface u~lt for ~etecting and s~ori~g indications of a processor mis-compare error. Additional~y, the unit in~
clude~ circults for detectlng and storing slgnals indica-ting the presence of other ~ypes o errors associated with each of the processoxs which occurred at the time the mis-compare error was de~ec~ed. These cir~uits are coupled ~o receive signals from set~ of contxol lIn0~ of an error in~
terace to whlch each of the processoss of ~he pair connect~
Appara~u~ including ~equence Gontrol logic ~ircui~s in re-sponse to a mis-compare exro.r ~ignal is operative o gener-ate signals which "unlock" the processor pair~and select ~a~first one o~the palr to be tested~ -. In accordance with a preferred ~mbodiment of ~he pr~-- sent~invantion, the $equence control circùi~s generate signal~ which direct a speci~i~ type of in~arrupt xegue~t to the proces~or selected for tes~n~ The type of in~ r-x~pt request is dependan~ upon whether t~e CiXCUi~B included in the 8ystem interface unit detected the pr~sence of any other types of erro~ as~oci~ted with any one of the pro cessor~O For example, when a~ internal processor erxor is detected, ~lgn~lled by a proce~sor forcing one o the con~
. trol lines o~ ~he erro~ er~ace ~o a prede~ermined ~a~e, : a fir~t type o~ interrupt re~u~t is dire~ed ~y th~ uni~

. . - ~ .
'''` ' ' ' ' . . : ' ' : ' . - ' ' ' ' ' ~ . .
-.~: - . , :
~ 5~ ~
. ~ , ,, , ~ , ~ . - . . , , ..... . . ... . . . .

~ 9 i;;~3 to the "good~ processor. Also, the uni~ S~Op5 the "bad"
processor from continuing operation by forcing ano~hex one o the control Iines to a predetermlned state. ~here no o~her type of error i5 d~tected in eithex proce~50r o a pair, the un~t direct~ a ~econd ~ype of lnterrupt re~ues~
to a first one of ~he proces~or~ of ~he pair and s~ops ~he opera~ion of the second processor.
After testing each of the processors as requir~d, the apparatus logically disconnect~ the faulty processor f~om the system. Thereater, input/outpu~ operations are only performed by the good pxocessor which c n be then periodi-cally tested by the operating sy~tem softuar~ to ~h~ ex~enk deemed necessary.
Thu~! the arrangement of the present inventlon pxovides for bo~h error detection and the availabilLty of bb~h pro-cessors for processing in ~he event that a mis-compare er-ror is detec ed~ Since ~uch testing is:earried out wi~h a : small amoun~ of additional c~rcui~s inc1uded ln the æys~em : in~erfac~ unit sy~tem reliability is in~r~sed. Addi~ionally, ':
in the event that testing fails to dete¢t errors within either one o~ the proce~sors, the control circuit~ can be en~bled to lock bo~h processor~ bark togeth~x. Th~s enables the system to continue reliable processing notwi~h~tanding : ; t~ansition er~r condl~lons.
.
. The ~elec~ed proce~or i~ s~ conditioned ~o per~oxm a ~elf test ~perat~on~ ~dit1~n~lly, ~ ti~er lnclu~ed ~n ; the proc~sor is ~tar~d and c~u~e~ a pr~d~ermined one o ~he control line~ ~o bs forced ~o a pre~e~mined ~a~e ol~
lowing a time ou~ of the tim~r. ~hi~ ~ignal~ that th~ pro~

, .
- . ~
.
- :
. , -- ., : ~ ' . ' ~
- .
- ~ I
~;..................................... ~6 ` ~ , . - . ~ .. , : !

.~ .: . . ` . , , . . ` , .i i , ., cessor has trouble in that it cannot complete the self test operation and is the bad or faulty proccssor. By requiring that the processor respond to the interrup request within a given amount of time, this si.gnals the satisfactory completion of the self test operation by the processor.
Completion of the self test operation provides sufficient verification of a number of ~he processor circuits such that the processor should be able to generate memory commands without error. It is only when the apparatus detects that the processor possesses a minimum confidence level therein is more extensive testing continued. Even w-hen the apparatus and associated diagnostic routines have established that the processor is good, testing is continued with the other processor of the logical pair in those instances where no errors associated with either one of the processors was directed. This ensures processing . .
reliability.
. .

~ ,. . .

~ "'.

, :

3~i3 In accordance l~ith the invention there is provided an inpu~/output system for controlling input/output operations involving a plurality of input/output devices, said system comprising: a plurality of modules, each having an interface port said plurality of modules including at least one memory module and a plurality of command modules each including means for generating output signals including commands said plurality of command modules including a plurality of input/output procassing units and a multi-plexer module coupled to said plurality of input/output devices; and, system interface means having a plurality of interface ports~ each port being con-nected to a different one of said interface ports of said plurali~y ofmodules for communication of input and output signals by said system interface means between said modules, said system interface means further including;
configuration register means coupled to the ports of said input/output pro- -cessing units for storing bit pattern signals coded for designating different configurations of said plurality of input/output processing units to be en-abled for operation, said register means initially storing signals represent-: ative of~an initial locked configuration bit pattern designating at least a pair of said identical plurality of input/output processing units as enabled ~ for operation in a locked mode wherein each processing unit of said locked - 20 pair processes the same input signals in an identical manner to generate identical output signals including command to said multiple~er module and memory module required for execution of said input/output operations; com-parison circuit means individually connected to the interface ports of each ` of said plurality of input/output processing units~ said comparison circuit means for comparing sets of said output signals from pairs of said interface ports of said input/outpu~ processing units paired for normal operation in said locked mode, said comparison circuit means being operative to generate signals indicative of a miscomparison between any one of said sets of output : signals; and sequence control means connected to said comparison circuit means and to said register means, said sequence control means being operative in response to said signals indicative of said miscomparison to switch said reglster means from sald locked mode configuration bit pat~ern to an unloc~ed ~ 7a .~ ' mode configuration bit pattern wl~crein only one input/output processing unit of said pair is cnabled for operation to permit first testing for reliably establishing which process unit of said p~ir is faulty.
In accordance with another aspect of the invention there is provided an input/output system for controlling input/output operations involving a plurality of input/output devices, said system comprising: a plurality of modules, each having an interface port, said plurality of modules including at least one memory module and a plurality of command modules each~ including means for generating output signals including commands, said plurality of command modules including a number of pairs of input/output processing units and a multiplexer module coupled to said plurality of input/output devices;
and, system interface means having a plurality of interface ports, each being connected to a different one of said ylurality of modules for communication of sets of input andoutput signals by said system interface means between said module, said system interface means further including: configuration register means coupled to the ports of each of said processing units for respectively storing bit patterns coded for signals designating different configurations for said number of pairs of input/output processing units enabled for operation, said configuration register means being set to a locked bit configu~ation pat-~ern for enabling one of said pairs of input/output processing units for nor-mal operation in a compare mode wherein each processing unit of said locked pair processes the same input signals in an identical manner to generate identical output signals including said commands to said multiple~er and memory modules required for ~ecution of said input/output operations in response to identical instructions; comparison circuit means individually connected to the interface ports of each of said plurality of input/ou~put :
processing units, said comparison circuit means for comparing sets of said output signals from pairs of said interface ports of said input/outpu~ pro-cessing units, said comparison circuit means being operative to generate signals indicative ~f a miscomparison between any one of said sets of OlltpUt signals; and, multistate sequence control means connected to said comparison .;
circuit means and to said configuration register means, said sequence control . .
-7b -means being operative in response to said signals indicativc of said mis-comparison to s-~itch from an initial statc to a first state in a predeterTnincd sequence, said configuration registcr mcans being conditioned by said sequence control means to switch from said loc~ed mode configuration to a first unlock-ed mode configuration l~herein only one input/output processing unit of said one pair is enabled for opera.~ion in a non-compare mode to permit testing of said one processing unit of said pair for reliably establishing which process-ing unit of said pair is faulty.
In accordance with another aspect of the invention there is provided an input~output system for controlling input/output operations involving a plurality of input/output devices, said system comprising: a plurality of modules, each having an interface port, said plurality of modules includiJ;g at least one memory modules and a plurality of command modules each including means for generating output signals including commands through said port, said plurality of command modules including a plurality of input/output processing means for executing input/output operations involving said plurality of input/
output devices and a multiplexer module co~pled to said input/output devices, each of sald processing means including first and second halves, each half including an input/output processor; and, system interface means having 2 plurality of interface ports, each being connected to a different one of said plurality of modules for communication of sets of inpu~andoutput signals by said system interface means between said modules, said system interface means further including: configuration register means coupled to the ports of each o~ sald processing means for storing bit patterns coded for designating dif-ferent configurations for said plurality of processing means, said config;lra-tion règister means being set to an initial locked configuration bit pattern for enab].ing at least one of said plurality of processing mcans for operation whereln eac1i half of said locked processing means processes the same input signals in an identical manner to generate identlcal output signals including 30 said commands to said memory and multiplexcr modules required for e~ecu~ion .
of said input/output operations; comparison circuit means individually connect-ed to the interface ports of each of said halves of said input/output process-- 7c -:

$~

ing means, said comparison circuit mcans for co~paring sets of said output signals from halves of said interface ports of said input/output processing means, said comparison circuit means being operative to generate signals indlcative of a miscomparison between any one of said sets of output signals;
and, scquence control means colmccted ~o said comparison circuits means and to said configuration regis~er means, said sequence control means being operative in response to said signals incicaLive of ;aid miscomparison to switch said configuration register means from said locked mode configuration hit patt~ to an urloc~ed mode configuration bit pattern wherein only one half of said processing means is enabled for operation for testing of said half of said processing means pair for reliably establishing which half of said processing means is faulty.

The novel features which are believed to be charac-teristic of the invention 60th as to its organization and method of operation, together with further objects and advantages will be bet~er understood from the following description when con-sidered in connection with th~ accompanying drawings. It is to be expressly understood, however~ that each of the drawings is given for the purpose of illus~ration and description only and is not intended as a definition of the limits of the present invention.

_ 7d -.~,....

F DE ~ICIll DT IOU 01' ME DRAW:I:NGS

F~gure 1 ~llustra~es in hloc~ diag~am ~on~ an lnpu~
ou~put sy3tem employing the principle~ of the pres~nt in-ve~t~on.
Figure 2 shows in grea~er detail an ~nput/output pxo-cessing unit of a pxoces~ox pair o~ Fi~ure 1.
Figure~ 3a through 3 show in greater de~all the ~y~
t~m interface uni~ 100 o Figure 1.
Figure~ 4~ and 4b show in greater d~tail the mul~i-plexer unit 300 of Figure 1.
Figure 5a-shows the line~ which comprise a data inter-~ace.
Figure 5b shows khe lines which comprise progr~mmable : in~e~ace employed in the sy~tem ~f Figure 1.
F1gure 5c disclo~es ~ines which comprise the inter-~upt interfaces includea within the s~stem o~ F~gure lo, Figure Sd show~ the lines which oompr~6e a local memory intexface o Figure 1.
, : Figure 5e shows the l~ne3 which comprl~e an ~rror .
notification inter~ace of Figure 1~ :
Figure 6 illustrate~ ~he Porma~ of W~EX and ~D~X
proyxam instxuctions.
; Figure~ 7a through 7a i1lustrate the o~mats of in-terface commands.
: . 25 Figure~ 8a khrough 8d il~lu~trate th~ ~ormats o ~he ~ :
: cont~nt~ of diPfer~nt re~i~tex~ included in khe ~y~kem nter~a~e unit 100 of ~lgure lo ' " '' ~
'~' ' , ,' " ~ : ~ .
.: . ' ~ ' .' :
. . .

- . . .. .. .... , .. . , . .. _, .

~ ~ 3 9 5 ~ 3 ~igure 9 illustrate~3 the ~ignal ~equence for proces-~ing an :Lnterrupt.
~igur~ 10a ~d 10b lllustrate the ~lgnal ~equ~Ila~s ~or transferring a W~EX co~nand.
S Figure 11 illus~rate~ ln tenn~ o~ negative iog~c ~i . e ., binary ONE = negatiYe ~:ran~ition) the lg~al ~e -quences for performln~ mQmory r~ad operation, Fig~lre 12 illustrate~ the format of an interrupt data woxd.
10~ ~igure 13 lllustratas the ~ormat o~ one type s:~f steering data.
Figure 14 ~ llustxate~ an arrangement int~rrupt con~
trol block in memory module. 500 for SIV 100.
Flgure 15 1~ a ~tate dia~ram o~ a se~{uencer in accor-dance with he present in~rention~
~lgure 16 is a flow chart usea in describin~ the operatlon of the present invention.

:
~, - ' , '.
. .
- .
' , . ' ' " ' ' -"
-'''' ~'' ' ' ,.
;. ' , , . , : :
, .

- , . ..
. .
~ .. . . . .. . .

~r General De~xip~lon A3 ~een from Flgura 1, the system which incorp~ra~e~
*he prinalple3 of th~ present in~en~ion lnclu~es t~o in~u /
output proce~sor (IOPP~ pair~ 200~0 and ~0-1, a sys~era ir~-terface unit (SIV~ 100, a hlgh spe~d multipl~xex (HSMX) 300, a low speed multiplexer ~LSMX) 400~ a host proce~or 700, a local memory module 500, and a main memory mo~ule 800.
Dif~exent ones of these moduIe~ connec~ to one of a numb~r of ports of the sy~tem interface unit 1~0 throuyh a plu-ral~ty o~ lines o different one~ o di~erent type~ of in-.
. ter~a~e~ 600 thr~ugh 603. More ~peci~$cally, the ~wo lnput~
output processors of logical pair 200-0 and 200-19 ~he ho~
. processor 700, and high sp~ed`multlplexer 300 connect to ports G, H, ~, F, D, and A,.respècti~ely,~while the low - ~.
- speed multiplexer 400, memory modules 50~ and 800 connect ,:
to ports J, LMO, and R~O, xespecti~ely.
: The input/ou~put ~yfftem o Flgure 1 can be vlewQd as ~lncluding a number of "ao~lve m~dules", ~passive mo~ul~s~
- 20 and "memory module~ h~ IOP proces~or 2ao~ ho~ proces-sor 700, and high ~paed multiplexer 300 serve a~ active module in that each ha~ the ~bility to io~ue memory command3 The active modules nonmally oonnect to porte A throug~ H. A
plurality of pàssive module~ are conne~ted to three port~ J, -.2-5 ~and L. ThesQ modules correspond to ~he lvw speed multi-plexer 400 and the:system inte~ace unit 100 a~d are uni~
`. capable ~f int~rpretl*g and ~xecutln~ c~mma~d~ applie~ ~o.
~ ;~the lin~s o~ lnterfaca 601 as.~e~crib~d he.rein. The la~

~ : : ` ` '. 1 .
.

group of modules oonstitutes local memory modules and remote metnory modules ~not shown) such a~ ~lQ8f3 of khe . m~in ~3ystem ~not ~hvwn) which are capa3:~1e vf executlng two differen~ ~y~es o~ con~narld~ appli~d to the lines of 5 t nterface S03 ~
The inpu~/ou~put ~ystem s: f ~:Lguxe 1 no~nally ~unctlons a6 an ~ npu~/ou~pu~ sub~ys~em responsive tD input/output in-structions ~BSUedl by hos~ proce~sor 7ûO whlch noxmally con-nect~ to port D vla the 1nterf ce 600, 601, and 602 whlch ln coxrespond ~o a data ~nter~ace, a progra~nable in~erEace, and an ln~errupt in~erface, respec~ively, des~ribed in .
greater detail herein. Pbrt~ F and E include lnt~xface3 cr enabling connectios~ of e1ther multiplexer or proces~a~r modulas of Figure 1O . `
For the purpose o:~ the present invention j proces~or 700 is conventional in design and may ~ake the form o~
- l/~S~ Iv~
B those units descri~ed in~lPatent~3,413,613. In the pre-- :!Eexred em}~odiment/ the input~;:utpu~ processor ~00~ initiates~ ~
ànd terminates channel programs xequlred ~or the execut~on o input/output in~tructions, processes interrupt requests received rom the system interface unit 100 and directly controls unit record peripheral devices coupled to :low ~peed multlplexer 400. Th~3 proce~sor pair 20~-0 colmQcts to ports G and H via the data interfa~e 600 antl i~texnlp~ .
interfa¢e 602.
~he low 6peed multiplescer 4a~ whlch ~or the purpo~e~
, - of the pre6ent invention can be cons~ dered conventional ~ n design, pxovides f or attachment of low speed peripheral device~ vla perlpheral atiapeers, each o:E which coupl~s to . .
.
:, . . . : .

... . . . . ~ .. ~ .. . . . .

5~3 the lines of a device adapter interface (DAl). The inter-face and adapter may take the form of those units described in United States Patent No. 3,742,457, which is assigned to the assignee of the present invention. 'rhe low speed devices include card readers, card punches, printers, and consoles.
As seen from Figure 1, the multiplexer 400 connects to port J via the programmable interface 601.
The high speed multiplexer 300 directly controls transfers between the groups of disk devices and tape de-vices 309 through 312 which connect to different ones of the channel adapters 302 to 305. Each of the channel con-troller adapters 303 through 306 which connects to a maxi-mum of 16 devices, in turn, connects to a different one of the ports or channels 0 through 3 via the interface lines of a channel adapter interface (CAI) 301-1. The high speed multiplexer 300 connects to port A corresponding to a data interface 600, a programmable interface 601, and an inter-rupt lnterface 602.
~ For the purposes of the present inv0ntion, each of the channel controller adapters 302 through 305 may be con-sidered conventional in design and take the form of controller adapters described in the aforementioned United States Patent .
No~ 3,742,457.
As mentioned previously, each of the modules connec-ts to different ports of the system interface unit 100. The ): :
unit lO0 controls the connection of the different modules to each other via transfer paths enabling the transfer of data and control Information between pairs of modules. For the purposes of the present invention, the system inter:Eace 30~ unit 100 can be viewed as a switching network enabling cach ~.

'~ ' ~;r .
.. . . ,. . . . . . . .. .. . , . ~ ~ .

of the "2ctlve" mvdule~ to tran~fer data tl) ~n~ ~x~m locaJ mesn~ry mo~u~.e 500 when the xeque~tlng modul~ ha6.
the high~s~ priority and i~; gran~ed the next availal~le memory cycle. ~hat is, a.~ ~xpla~n~d hexeixl, the unit 100 in~:lude~ priori~y loç~ic ciraui~ whiah de~erM:Lne ~he rela~
tive priority a~ requests rom eaç:h c: ~ the activ~ module~
and grants the next avail~le memory cycl~ to the hi~hes~
pric3ri~y re~uest recelvedO
Additionally, the un~ 100 incllldes int~rrup~ prl-10 orlty logic aircult~ whlch detenni~e the relative priority o~ lnterrupt re~uests received from each of the ~nodules and ~elects the highe~t E~riori~ request received and pa~e~, the reque~t to processor 2dQ vi~a a ~w~tching ne~work as explained herein. ~ ~
. --' ' ~ .
15 TH~S PORT INT~3RFACES
l~eiEore d~scribing in greater aetail dif ferent c)n~s of the ~ dules o~ lE'igure 1, each of the inl:erfaces 600 thxc>ugh 603 ref~rred to previously will now be de~cribed with refer~
eno~ to E'igures 5a through 5d"
20 . ` E~efarring fir~t ko F~gure 5a, i~ is ~en that ~his ~l~ure dlsclo~es the 11 ne~ which con~titute the data intex-~ace whic:h is one oiE the lnterfac:es which p~ovldes ~or ~x change of in~orn~ation between an active module and the sy~ I
tem lnter~ace unit 100.. E~cchang~ i~ accompli~hed by co~trol- ~ !
2S ling ~e loglcal ~tates o~ VArioU sLgnal line~ in acoor-dance wlth pre-e~tabll hed rule~ implemer~t~d through a ~-quena~3 of . ~igr~al~ termed " a dialog" .
~ A ~en from Figur~ Sa,~ the int~ri~c~ ~clude a~
.
, . . ,: ;
- l '1 .. .. . .
~c~:~ve OUtpllt por~ reque~t line (AOPR), a plu~lit~ of d~a to SIU l~nes t~S Oa-DT~ 35, P0-P3), a plurall~ o ~te~rlng ~lat~ tc~ SIU line~ (SDI'S 0-6, P), a p~urall~y o~
multipork identi~iea to ~IU llne~ (MITS 0~3 , P~, an ac~
r~t~uest ac!cepted line ~), an acc:ept xead da~a line (~DA~, a plurallty of da~a from ~U bU8 line~ (~FS 00-35 , P0-P3 ), a plurall$y o~ multlport id~ntif.ler ~.rom ~IU lines (MIFS
0-3, P), a double pr2ci~1On fxom SIU line (DPFS), and an a~cept status 1ine (AST). The des~ription c~f the lnter-face l~ne~ i~3 given in gxeater detail in ~he ~ac~iox~ to .
~ollow.
.

.

. . . '- ' ~ ' ~
, ., ~ . .

.
- ,~ , .

' ' '' ' , :

. ~ . .

~.

.. . , . ~ . . ` . . _~ .1 .. . _ ., _ _ . .

' 'i ~ , ~OPR ~h~ actlve ou~?ut pe~rt ~e~ue~t llne is unld~r~tlc)rla~ n~ which exten~s ~Erom s each o~ the a~tive modules to the BIU 100.
WhQn ~3et r thl~l line ~gnal~ thP ~IU that the module xeque~s ~ tran~fer path o-Jer which ~ command or data ~ ~o b~ tran~ferred~
~T8 00-35, P0-P3 The data ~o SIU line~; are a ~our byt~ wide ~ dir~ctional path (foux 10 b~ by~es) that extend betwe~n each of ~he active modulee ~ . and the :SIU a~d are u~ed for tran~ferring - :coxnmand~ or data from each active m~
to the SIU 10~.
-15 SD~S 0-6, P : The ~t~ering data ~o ~IU lin~s ext~nd from ea~h active m~dule to the SIU 100. The~e - - : .
}ines axe u3e~ to apply ~teerlng ~ontrol in-- ~ . fo~nation t~ the SIU 10~ when th~ lin~ AOPR
et. Steering control iniEo~nation con- ;~
. ~ 20 ~ ist~ of seve~ bit~ and a pari~y b~t w~;ich:
.
are coded a~ follow~
. ~ . , ~ ,. .
a~ ~hQ st~e o~ bi~ 0 ~he type of comn~axld - applied to the DT~ lines (whether the ommand i~ a programmabIe ~interPac:e ~om-25: ~ mand or a memory co~n~nd).
- b) Bi~ 4 are coded to: iL~dicat~ which c~ne~
` ~ : t)f t~ae modul~s i5 to re~el~e and :Lnter-pret the co~nmand ~commands ar~ inte:~pr ted only ~y memory module and pr~gr~
. ~ 9~ ~ ~abl~ in~r~ace coT~ands ~hall be inter~
pre~ed by all mcs~ules except i~put/s:~u~put P ~ or~ ~00~~

.
~ ~escr~ on - ç) The state o~ bit 5 indica~es whether . on~ or two words of t~e command : .
: . infoxmation is to be transferred . between the reque~t~ng active module and the designated recei~ng module (one woxd specifies a sing].e p~ecis1On . . ..
- ~ . transfer and t~o word~ specifies a .
double preclsion trans~er)~
: . . - d) The ~tate of bi~ 6 indicates the .
direction of transer betueen-the - . re~uesting module and:khe desi.gnated :
. ~ receiver modu1e.
~:: - ej Bit P .is a parit~ bi~ gsnerated by . . . ~ . .
: 15 . : the requesting active module which is checked by apparatue included~within :
the SIU 100. . ~ ;
MITS 0-3, P . ~ Thè four~multlport;identifier to. SIU lin~es : . :extend from:~he ac~iVe ~odul~ to the 9IU 100.
20 ~; ~ These line:~ are coded:~.o indicate which sùbchannel ~r port within àn active modul.e ; ~ caused the 6etting o line AOP~. ~
; ~ . ARA : The active reque~t accepted line extends fr~m : :
. the SIU 100 to each of the activ~ modu1e~
. . . . .
2~ This line is ~et to indicate that the . ~ ~
: : ~ ~ . :. .
: ` : . designaked r~ceiving module has ac~pted the : active modu1e'.s request which a11Ows the : .
module to remo~e the requested ln~ormation ~ .
- Xrom the data interfac~ 1ines. ~.
,.

;
: . .: . -: ~ : : ,
3~;3 De~c:ription :~ . ~A ` /rhe accept xead data l~ne ext~nds ~rom the :- SIU to each of~ the aa~ive module~. This llne - . is ~et ~y the SIU 100 to indicate to the ac-tive moaule t~at it is to acaepk the previously requested data from a de~ignated module.
D~S ~0-35, PO-P3 The data from SIU iines are ano~her set o:~
` ~ ~ data path lines which are a :four byte wi~e unLdirectional path (~our 10 bit byte3) which extends from the SIU to eaoh active module.
- . ;;. This ~et of lines is used by~ the SI.U 100 to . convey xead t yp~ data to a d~signated one o~
the acti~e modules.
:: MIFS 0-3 ,~ P The four multiport identifier ~rom SIU line~
15: plus odd parit:y line extend from the SIU 100 to each of ~le active modules. ~hese lines are . i -~- . coded to indicate which port or fiubchannel on ' the active module is to accept ~le da~a of a ~ . - . . . .
. previous read operation from the SIU 100.
DPFS The double pr~cision ~rom SIU line extends`
.
from the SIU to each o~ the actlve modules~
~he state of ~his line indicates wh~ther one - ~ ox two word~ o read data are to be acc:ept .
by the active module to complete a ~ans fer 2~ (read GonQnand). .:
The accept ~tatus line extends from ~he SIU~:
100 to -eaah active~ modale. The~ sta~e o~
. . line ;7hich i~ mutuall~ excl~lsive of .l~ei. ARI)~
~i~nals the active module tha~ it shou7 ~ aa-:
3~ ~ cept ~tatu~ informa~ion applied to t~e r . ~ . 17 The lines o~ 1;he p~ogr~unable ints~rfac~3 601 ~howr~ i~
Figuxe 5b pxovide for transfer of command inEo.rmation from an active module and a designated module. The transfer i9 accomplis~d by controlling the logic of states of the vaxious signal lines in accordance ~ith pre-established rules .implemented thrQugh a sequence of signal~ termed "dialog". The programmable interface includes an accept progr~mmable interface c~T~mand line (APC), a plurality of programmable int rface data from SIU lines (PDFS 00-35, PQ-P3), a progr~nable interface ready iine (PIR), a read data transfer request line (RDTR), a plurality of prograr~ma~le inter~ace data to SIU lines (PD~S 00-35, P0-P3) and a read data:accepted line (~D~A). The~description cf the ~ interface lines are given in ~reater detail here.in.

-: - ~ ' ' , :. , :
. PROGRaMWABLE INTERFACE LINES
~ ~ 15 Desl9nation ~ Descxi~tion APC : ` The ac~ept program~ble interface command . line extend~ from the ~IU 100 to each receiving module. When set~ this line signals the module that c~mmand , ~
: -20 information ha~been applied to the ~:. . PDFS lines of the interface by the S.IU
and is ~o be accepted by ~he module.
PDFS 00-35, P0-P3 ~he programmahle inter~ace data rom SIU
line~ are a ~our byte wide u~dlr~¢tional path - 2~5 ~ our 10 bit bytes) that extend~ ~xom ~he ~ ~ :
SIU 10Q to ~ach module~ The~e li~es appl~
programmable int~rf~ in~orma~ion from the . , - . system lnterface unit ~o a de~igna~ed receiving .:
-; modul~
- , . ~ . I

....... .. .

PIR The programmable interface ready line ex-tends from each module to the SIU. When set or high, this line indicates that the module is ready to accept a command to be applied to line PDPS.
PDTS 00-35, PO-P3 The programmable interface data to the SIU
lines are a four byte wide unidirectional path (four ~0 bit bytes) that extend from each module to the SIU 100. These lines are used to transfer programmable interface information to the SIU.
RDTR The read data transfer request line extends from each module connected to the program-mable interface to the SIU 100. When set or high, this line indicates that the previously , requested read data is available for transfer to a module and has been applied to the lines PDTS by the module.
RDAA The read data accepted line extends from the SIU 100 to each module. When set or high, the line indicates -to the module that the data ap-plied to the lines PDTS has been accepted and that the module may remove the information from these lines.
A further interface is the interrupt interface 602 of Figure 5c which provides for interrupt processing by the input/output processor ~; pairs 200-0 and 200-1. That is, the interface enables the transfer of interrupt information by an active ' ' ~; ~ :

~ .

. -- . . . . . .
. . ; . , . " . : .. . , . :

~dule to the SIU 100 a~ well a~ the tran~fer o~ 1~ exrupt ln~
;~rmati~n by thQ ~IU 100 ko the input~output praces~3-r 200 ~or proce~sing. 8imilax to the okher lnte~aces r th~3 t~an~fer inter~upt requeE~t)3 i~ acc:s)mplish~d by cont~olIlng the ls:~glcal 5 ~ates of ~he ~Tarious ~ign~l lin~ in accordance wi~h pre-estab-ll~hed rule~ implemented throu~h a equence o~ signal~ ~ermed 1l dialo~
- ~he inter~aoe ~ncludes an interrupt request line (IR) I a pluxality o~ i~texrupt data lin~s (IDA 00-Ii, P0-Pl) / and a plu-10 ral.ity of interrupt multiport identifier line~ (IMID 00-03? for modules connectad to ports A thr~ugh I~o For modules conneated to poxts G and ~, the interrupt interface further includ 9 a level zero pr~sent line (I.ZP), a higher le~l ~ntex~upt pre~ant line (HLIP), an illterrupt data request line (IDR) ,- a r~l~a~
.

15 l~ ne (RLS), and a pl~rality o~ active irlterrup~ level lin~s (AIL0-2). As ~een from Figure 5c, the Lnterxupt inte.rface po~ct3 G and H ~do not include an interrupt mult.iport ldentifier line., The de~cription o~ the interrup~ line~ i~ given in grea~er de~- :
.
tail herein. ~ , 2û ~ INTERRUPT IN~E~PACE LINES
De~l~nation - : ~ ~
IR The interrupt request line extends rom each ç~ . module to the SIU lOQ., ~hen sey~ thi~ line . . . indicates to the SIU that it require~ service.
-: 25 IDA 0-3, P0 The in~e~rupk aàta line~ ex~end from an ac~
II?l~ 4-11, Pl tive module to ~he SIU lOû9 These line~ ar~
aoded to contaln control in~orma tion r~quired : ~ . . . to be t~anserr~d to the input/output proc~
or. The~e bi~s ar~ cod~ Ec: llows:

. ................... . . , -'; ' ' ' ' , '' '~ :
.:................. . .:
. . ~ .
. , . , ' ':
";.:

.. . . .

j3 a) The state of bit 0 specifies to the SIU 100 which of the two processors (i.e., processor number) is to process the interrupt request.
b) Bits 1-3 are coded to indicate the priority or level number of the interrupt request to the SIU 100.
c3 Bit P0 is a parity bit for bits 0-3.
d) Bits 4-8 are coded to provide a portion of an address required to be generated by an input/
output processor for referencing the correct procedure for processing the interrupt ~i.e., an interrupt control block numbsr ICBN).
e) Bit Pl is a parity bit for bits 4-11.
IMID00-03 The interrupt multiport identifier lines extend from each active module to the SIU 100. These : lines are coded to identify which specific sub-channel of the active module has requested inter-rupt service.
LZP The level zero present line extends from the SIU
100 to the input/output processor. When set, or high, this line indicates that there is a highest priority (level 0 interrupt) request bsing directed to a processor by the SIU 100.
` HLIP The higher level interrupt present line extends from :
- the SIU to each mputjoutput processor. When set or high, this line indicates that there is an interrupt request having a higher level or priority than *he :, :
`~ procedure or process being executed by the processor.

.~ . ' ~- r~
'''~"' 5~3 IDR The interrupt data request line extends from the input/output processor to the SIU 100. When set or high, this line indicates that interrupt data is to be sent to the processor on lines DFS by the SIU 100.
RLS The release line extends from each in-put/output processor to the SI~ 100. This line, when set or high, indicates that the processor has completed execution of the current procedure.
AIL 0-2 The actîve interrupt level lines extend from the SIU to the input/output processor. -These lines are coded to designate the in-terrupt level number of the procedure being executed by the processor.
A further set of interface lines u~ilized by certain ones of the modules of Figure 1 corresponds to the local memory inter-- face lines of Figure 5d. The local memory interface 603 provides for exchanging information between local memory 500 and the modules of the system. The exchange is accomplished by controlling logical states of the various signal interface lines in accorda~ce with pre-established rules implemented through a sequence of signals termed i a "dialog". The local memory interface includes a plurality of data to memory lines ~DTM 00-35, PO-P3), a plurality of request identifier to memory lines ~RITM 0-7, P0-Pl), a plurality of specification lines to memory lines (SLTM 0-3, P), an accept PI cornmand line (APC), an accept ZAC command llne (AZC), "' .

~ - 22 -.
, ' :

5$~3 , . .
; a PI interface re~dy line (PIR), a ZAC interface ready line tZIR), a xe~d data transfer r~uest line ~D~R), a plurali~y : ~f data r~m memory line~ (DFM 00-35, P0-P3~, a plurality of request identii~r frQm memory ~ines ~RIFM 0-7, P0-P13, a ~ double precisio~ from memory line (~PFM), a QUAD line, a read data Gcepted line (RDAA) and a system clock line ~SYS-CLK).
h slmilar inter~ace is used for connecting the maln memory module 800 to the SIU 100.
Memory and pragrammable interface commands are trans~erred out of ~he ~ame ph~sical data lines of the interace. ~he ln-teifaae does no~ inalud~ a set of lines for processinq inter-rupt requests and therefore the modules connected ~o the local : . mémory by the ~IU:100 cannot directly ~ause~ a memo~y in~errupt.
The description of the local memory interface lines is qiven lg in g~eat2r detail hexein.

. LQCAL MEMORY INTERFACE LI~ES
D ~ Descr~ tion .DTM Q0~-3~, P0-P3 rhe data path lines consti~ute a four`byte wide unidirectional ~ath ~ 36 in:Ec)rmati.on , ~o ~ linss and four odd pa.rity lines) that exte~ds .

- . : from khe SIU 100 ko the local memo~y 500.
: . ~hese lines are used to t~ansfer memory or programmable interface com~ands ~o the . local memory 500. ~ ~
RI~M 0-3, P0 The reque~kor identifier ~o memory lin~s : ~`
RITM 4-7, P1 consti~utes two group~ of four lines which - . extend ~rom the SIU 100 to khe local memory . 500. These lines are c~ded to convey in~c~r-: : mation to the local memor~ ident~fying the module wh~ch initiated khe comma~d and ~re :
~ used to return ~he ~a~a requested to ~he - . proper modul~, - . - : . . . , :
; . ; -23~

.. . . . . . . ..

9~3 .qLTM 0-3, P Tl~e sr~ecification lines to memory extand-:Erom the SIU 100 to the Iocal memory 500 and include two port number 9elec~ion l~nes, a read/write to memory line, a double precision ~.
- to memory line and. a parity line. The infor~
ma~ion ~ignal!q applied to the~e lines ar~
coded as follows.
a ) Bits 0~1 are port number seiection . - ~ bits coded to:specify which por~. or . subchannel within the attached module ,. ' ,' .
i5 to:receive or interpret the memory command sent to: the module.
.
b ) ~ Blt 2 i.s a read/write to memor~ bit : ~llich is inc:Luded ln ~he steqring control S information received ~rom the ac:~ive.
module whlch is orwarded by tne SIU
o kh:e local memory 500 wllen a new . command is sent to the memory by t'le IU loa. ~ The state of ~hi:s bit~indiGates 20 - ~ the direction of data trans fer.
c) Bit 3 is a double precision to memory . .
- bit coded to speciy the amount of data to be trans:~erred. ~ It is also .
~ . included in the 5~eering control in~or~
25 . ` ~ . ~ :ma~ion provided by the active module . , ., : !, : ~
which is fortlarded to the loaal memo~
- : . module 500 by the SIU 100 when. a netr conunand i s sent to th~ menory modu~e.

. . ~ , : ; ~ . , ~ . .

24~

AZC The accept ZAC command line extends from the SIU 100 to the local memory module 500. When set or high, this line signals the local mem-ory module 500 to accept the ZAC command and control information appli.ed to the other lines by the SIU lO0. The setting of this interface line-is mutually exclusive with the accept PI
command inter~ace line.
APC The accept programmable interface command line, as described in connection with the programmable interface, extends from the SIU 100 to the lo-cal memory module 500. When set or high, this line indicates that the command information ap-plied to thelines DTM is to be accepted by the : local memory module 500.
PIR/ZIR The programmable interface ready line/ZAC in-i terface ready line extends from the local mem-ory module 500 to the SIU 100. When set or high, ~ each line signals the SIU 100 that the ].ocal mem-`: 20 ~ ~ ory module 500 is capable of accepting a pro-grammable interface ~PI)/memory (ZAC) command.
RDTR ~ The read data transfer request line extends from ~ ~ the local memory module 500 to the SIU 100. This :~ line, when set or high, indicates that the read type:data previously requested by a ZAC or PI
command is available a].ong with the necessary : : control information to be sent to the module requesting the data.

.
25 - :

~ ~
,.
.

5~3 DFM 00-35, P0-P3 The data from memory lines are a four byte wide unidirectional bus which extends from the local memory module 500 to the SlU 100.
These lines are used to return read requested type data to an active module via the SIU
100 .
- RIFM 0-3, PO, The two groups of requestor identifier from RIFM 4-7, Pl memory lines extend from the local memory module 500 to the SIU 100. These lines are coded for directing the read data from module 500 back to the requesting module.
DPFM and QUAD The double precision from memory line and QUAD line extend from the local memory module 500 to the SID 100. These lines are coded to indicate the number of words to be transferred , via the SIU 100 to the requesting module during : read data transfer request time interval. These .
lines are coded as ollows.
QUAD, DPFM
0 0 . one word single precision 0 1 two words, double precision x (don't care) four words :
DSD The read data/status identifier line extends ~
; ~ from the local memory module 500 to the SIU. .. :
~ The state of this line signals the SIU 100 .:
`~: whether the information applied to the lines ~ FM is read data or status information when . ~- .
~; line RDTR is to a binary ONE. When set, the .~: ~ line indicates status in-Eormation of one or two words (QUAD=0) ~ .

~, . ~ - . ,-3 re 5 e ~ i DSD :Ls bQ~ng t~ans:~erred. ~hen-~ to a blnaryZ~3RO, the llne ~ignals that up ~o fc~ur words o da~a a~ eing ~r~n~erxed, the number belng specif~ed by ~he codirl~ o~ lines ~UAD
and DPFM.
~DAA The read ~ata accepted llne, a~ m~n~loned in conn~c:tiorl ~ith the progra~able lnterface, extend~ ~rom the SIU 100 to~ the local memory - : ~module. When set, th~ 3 l :Lne signals the memory module ~haL ~he da~ca appl~ed on the in~erf ce line`~ by the local memory ~odule:
- has been accepted a~d ~h~t the local me~.mory modul~ may remov~ a from ~he~e lines.
SYS-CLK Th~ system clock l~ne ~ a 1~ne which ex-. . tends from the SIU ~0 ~ each module of the syBte~tl. This line is con~ected to a ~lo~k . - ` sourc~ included withln the input/output :
. proce~sor to synch~o~lze ~he operations Qf .
each emory module frDm a c~ommon ~y~eem - ` clock source.

A la~ ~et o interface lines i8 8~GWn in Figure 5e.
. In ~cco~dance ~i~h the present inv~ntion9~ ~veral of ~he~e ; li~es signal certain condltions as ~r example error condi~ion~
~ . ~and operational condi~ion6~ ~Io~e import~ntLy9 the~e lines enable the SIU 100 t3 control the op~at~on of the proces~or.
pair in accord~n~ with the pre~en~ inven~ion.
.
A~ ~een rom ~igure 5e, ~he interface includes a parlty -~ ~- error de~ected lin~ ~P~ trauble line (TBL), a STOP lin~r . . -; an init~alize~line (I~IT), and an opera~nal in line ~OPI).
~-. . ~ .
.
.. . .

.
. ' , 7~
.

ThQ desc~ip iorl of the inter~as~e llne~ is s~iven hereln in gre~ter detail~
.
~ .
. .
. ' . ~*~

- 5 PED Th~3 pa~ity særor detected line ~8 a singlQ
line whiph i~ ~oded ~o indica~e to ~he ~IU
.
lûO ~h~ logi~al "OR~ all khe pari~y er~
. ~ ror de~ec~or circuits internal ~o the at-tached I/O pre~cessor. This line i~ used - 10 by the SIU lQO a~ an indica$10n ~ha~ a ievel zero in~errupt i~ to be i9~ue~7 to ~he proc~s~
so~. :
` ~ ~BL The trc>uble lin~ hen ~e~ by ~he proce~s0r, noti~ie~ the`SIU 100 thàt lt ha~ encount~a~ed:
` an exce~tion aondltic~n w~lla 13~ lev~l zero or , - a ~t~me-c)ut durillg the self tes~
STOP A lin~ ~rom ~he SIU 100 ~o a, module wh~ ~hD .
when ~e~, ind1ca~e~ tha~ th~ module ~houl~
oease all actlvlty7 - 20 I~tIT A line ~rom ~IU 100 to a modiule which, ~h~n ,~
.
~et, cau~es the module ~ as ~e ~he init.~L-allzed ~ta~e. ;~
OPI A set~complement pair o~ 11 nea .to the ~IlJ lûO
.
~;. : . - ` ~rorn a module. The pair i~ cc1ded to indleate~: :
. ~
êS when the modul~ ctive, ia p~werç~d up, a~d i~ r~ad~f to generate ~ acce~t c~n~
avi~g de~cribed the di~ererl~ ~,yp~ o~ exace~ ut~ e~l . by ~he ~o~ul~ o ~1gure 1~ each o~ the modul~ pe:~tlDe~ ~o ~ë
urde~stEm~!ling of th~ pre~e~nt in~renk$on wlll now be de~8c~ibe~
3~ greater deta~ lo ~ ' . - : : . , :
. .: : . , : :

~3YL.~put/output Proc~ssor 2~ 0 Referrl~g to Figure ~, it is ~een $~at ~he pXoces~or 200 comprises a microprogrammed control seation 2~1 ope~ai~ive ~o genera~e control signals in response to microinstructions store~
in a control store 2~1-10 for exeauting ini~txuctions, an instruction buffer section 202 for storing inst~uctions etched from the local ~emory n~odule S00~ a storage ~ecti~n 203 and a processing section 204 for performing axithmetic and logic operations under the control of microprogr~ms ~tored in control.
store 2~1~10, .

Control Store Section 2nl -Considerin~ each sec ion in greater detail, the contxol store ~01-10 is constructed of fi.xed sections which u~e for example a read only memory ~OM). The store Z01-lo lS addressa~le vla signals from any one~ of the eight address ~ources applied to a selector switch 201~ The contents .
of the addxe~sed locations are read out into an output register -201-lS ànd decoded by decoder clrcuits included within a block . 201-16.
~dditionàlly, as shown, signals frQm one of the fields of the mlcroinstruction ~contents of ~egi~tar 201-15 ar~ applied dS
an input to the switch 201-14 for selecting which one of the eight . input sourc~s i5 to apply an address to control store 201-10 .- Th~ microinstruction~ read out to reg$~ter 201-15 include address constants ~or bra~ching the control ~t~re 201-10 to .. - . : : . : . . . .
- appropriate micxoprograt,l ~ou~ines~
`
~ ' :` '. ' : ' , ` ' ' ,, ` ' ' . ': : , .

:" ;
, ' ' ' :

.''' , ' '' ,' . ', ' ~ ' ' . , .
-, ' :, ', . .
, ~, . : . : : ' .
: ~ - . . 29~
. . ~
, . . , , . . .. . .... .. , . ~............. -3~t~ 3 As seen from Figure 2, the eight control s~ore address source5 include: interrupt!exception signals derive~1 from sign~ls applied by th~ system interface unit lOD and sircuits includecl within procesSor 200; a next address register po~ition ~hich receives next ad~ress in~orntation stored in a register 201-22 via~ an ad~ler c:ircuit 201-24, a return addre~;s ~egister position whlch receives the return address aontenta of a re~urn register 201-20~ an execution address register p~sition which receives an address from a pathfinder memory 201-2 via memory output regiater 201-4; a sequence address regis~er po~ition whic~l also .

receives an address from register Z01-4; and a constant position which recelves a constant value Jrom the D~tpUt register 201-15.
The ap~roprlate next address is generated by adder circu~t : 201-24 which receives as one operand lnput, address si~nals fr.om one of the sources selected by switch ~Ql-l~ and as~other opexand input, signals from skip control cixcuit~ o~ a block 201-.'6.
The skip control circuits are conditioned by constant signal~
: . ~ stored in control store register 201-15 whlch ill turn provide an appropriate value as one o~ the operand inputs ~o the adder 201-24. The resultant address genera~ed by adder circuit 201-24 represents the sum of the ad~resses applied by switch 201-14 : :
and constant signals provided by skip control c.ircui~ o~
block 201 250 Briefly, ~the differen~ positions of swi~ch 201~14 ~` ara selected in response to microinstructions read from - -25 contxol store 201-10 to pxovide appropriate addresses for micro-programs stored in control store 201 10 required for th~ executio~
. of an operation specified by the op code of a program in~tructionO
: ` The instruction op code is applied to ~he pathfinder memory 201-2 via path 201-6 a~ ~h~wn. The xetuxn addre~ register -: 30 posltion of swltch 201-14 is sel~cted durlng program sequencing ` ' ~ ' . ' ' ' , .
~ 30 ~ :
, as a consequence of a hranch operation while the constant register position is selecte~l to provide for a br~nch to a predetermined location ln the control ~tore 201-1~ defin~d b~

the constant field of th~ microirlstructi~n ~tor~d in ~egist~r 201-lS.
Int:errupts are processe~ at ~he completion of executivn o~ a program instruc~ion. It is ~een in Figure 2 that a hlgher level interrupt present (HhIP) and level zero int~rrupt (LZP) line~ apply signals to switch 201 14. The s.ignal applied to ~he ~ILIP line is "~NDed" wit:h interrupt inhibit signals from a process control regi~ter 204-22 and ~h~ result is ~R~d witll the 31gnal applied ts the LZP lin~5 When the higher level lnterrupt present signal is no~ inhibited or th~re 1~ a sign~l applied the LZP line, signals from circults, not qhown conn~cted to S switch 201-14 select the exception/interrupt ~051tion. The signal lines lndicative of the presence of an llterrupt (LZP
and E~IPL~ cau~e the selection of an interrupt ~e~uence of microinstructions to be referenced in lieu of referencing ~he microln truction sequence for ex~cuting the next procJram instruction~

5ignal lines indicative of "exception~" are applied to control circuits, not shown, associated with switch 201-14 and cause the ~elec~ion of the exception/interrupt position.
~his provides an ~ddress for referencing an ~xception sequenc~
: 25 o~ microinstruc~ions. Depending upon the type of ~xecution, ~ the exception may be proce~sed immediately because : continuing program instructio~ execu~ion mus~ b~ pre~env~e~ -: ar it 1~ not po~sible (e . g. faults~ lllegal instructlon~. The except~on-is proce~ed upon the c~ompletion of execution o~ the program lnstruc~ion where the condition d~e~ ~ot require immediate . attention (e.g~ ~ime out, ovexflow, etc,~. A~ explai~ed herein,~ :

- ~ ',;~
.
..
: . 31 ~ :

.. ..

the occurrence of exceptions cause the exception/interrupt position of 201-14 to be selected and the setting of an ap-propriate bit position in process control register 20~-22.
Ti~ing signals, designated as PDA in Figure 1, re-quired for establishing appropriate memory cycles o-f operation for control section as well as timing signals for opera-ting other sections of processor 200 and the other modules of the system of Pigure l are provided by clock circuits included within a block 201-30. The clock circuits receive as an input the STOP line which, when in a binary ONE sta-te, inhibits further operation of control section 201. ~le block 201-30 includes cir-cuits for signalling the SIU 100 via the OPI line that the processor 200 is operational. For the purposes of the present invention, the clock circuits as well as the other circuits of Figure 2 can be considered conventional in design and can, for example, take the form of circuits disclosed in the publication titled "The Integrated Circuits Catalog for Design Engineers", - by Texas Instruments Inc., printed 1972. More specifically, the clock circuits can comprise a crystal controlled oscillator and counter circuits while the switch 201-14 can comprise a plurality o data selector/multiplexer circuits.
From the above, it is seen that, as in most microprogram controlled machines, the control store 201-10 provides the nec-essary control for each processor cycle of operation. That is, each microinstruction word read out from control store 201-10 during a cycle of operation is divided into a number of separate control fields which provide the necessary input signals to the various selec-tor switches of Pigure 2 for ad-dressing of the different scratch pad memories and selection : . . -:
for branching, signals for controlling the operation of an .

~ _, r . _ ~ .

., ~ . ' ' .

adder/shifter unit of section 204 ~nd signals for providing control information necessary for generating commands. ~or more detailed information regarding the operation of control section 201, reference may be made to the copending appli-cation titled "Pathfinder Microprogram Control System" invented by G. Wesley Patterson et al., which issued as United States Patent No. 4,D01,788 and which is assigned to the assignee of the present invention. Reference may also be made to other ones of the documents referenced in the introductory portion of the specification.
Instruction Buffer Section 202 This section includes a plurality of registers 202-2 for storing up to four words of instructions fetched from local memory module 500 and applied via a data in register 204-18.
The group of registers 202-2 are connected to a two position instruction register switch 202-~ which is arranged to provide two outputs, a current instruction read output (CIR) and a next instruction read output ~NIR). The selection of instruc-tion words on a half or full word basis is made in accordance with the states of bit positions of the current instruction counter (IC) normally stored in a first of the working regis-. ters of block 20~-12. ~or the purpose of the present inven-tion, the arrangement can be considered conventional in design.
Storage Section 203 .
As seen from Figure 2, this section comprises a scratch .
pad memory containing eight sets or groups or registers associ-ated with eight priority levels. The highest priority level is level 0 and the lowest priority level is level 7. ~ach group or level includes 1~ registers used as described herein.
.

- 33 - ~

; '' ' ' The scratah pa~ memory 203-10 is addre~;sed via an eight position d~a sele~tor swi~ch 203-14 which sel~ctively applies a seven bit address from any one of eight sources to address inputs 203--12. Tlle three m(~st si.gnificant bit pos~t:ions of address inputs 203~12 ~elect one of the eight sets of registers (i.eO the level) while the r~maining four bits select one of the sixteen registersO Signals applied to the active interrupt level (AIL~ lines by the S~U 100 provide the ~hree most significan~
bits to the scratch pad address inputs 203~12. The remaining signals are provided by control store register 201-15 or fields fl om the instruction applied via the IRSW.
The write address r~gia~er 203-22 is loaded via swi~h 202-~ to store signals corr~sponding t~ ~ither bits 9-12 or b.its 14-17 of the current progra~ ins~ruc~ion as designated by one of the fields of the microinstruction contained in re~ister ~01~15.
Accordingly, the wrlte address registel^ provide~ address storage for loading or returni.ncJ a-result tQ one of the general xegisters of scratch pad memory 203-10. r~he write operation oc~urs upon the generation of a write clock ~ignal which occurs elther in 20 response to ~witching to a binary ON;E ~ a clocked write :Elip--flop ; not ~ho.wn, or in response to a field o:~ a microinstructi~n loaded into re~ister 201-15~ When generated by the wri~e . , :, . ~ . . . .
: -: 1ip flop, the write clock si~nal occurs:when. ~le write flip--flop is reset to a binary ZERO upon the occurrence o~
a next PDA clock puIse~ This allowq a wrlte op~ration xelating to a program instructisn to occur during the staxt o~ process;ing the next instruction.
, It will be noted that the contents of the writ~ address register 203-22 are applied to a. decoder network 203-~B via s~lector - ~ 36: Switch 203-14 whic~ is operative *o generate a si~nal on an output , , .. . .
~. . . .
: . : - . _34_ . - I
, . ., 1 .. . .. , , , . . . . . . / , . ..

- line each time register 203~22 s~ores an address of o, 1 or 15.
This signal inhibits the generation of a write clock pulse by gatin~
circuits, not shown~ when write flip-flop is in a binary ONE s~ateO
Additionally, the deco~er network 20~28 receives a mode signal S from the process state register 204-20. The ~tate o~ the sign~l which indicates wheth~r the processor 200 i5 in a master or sl~ve mode of operation is "~NDED" with the output signal and is used to generate an exception signal on another output line which is applied as an input to process control regist.er 204-22 and to one causes selection of the exception~interrupt position o~ switch 201-14. As explained herein, this pr vents alterat.ion o the con-.tents of the process state register location. (GR0) oE scratch pad memory 203-10.
The contents of an addressed register location are read out into a scratch buffer register 203-16 via a flxst two position data selector switch 203-18. The contents of the buffer register 203-16 are then selectively applied to proce~sing section 204 vla a further two position data ~elec~or switch;~03-20. The different positions of each of the data selector switches 203-14, 203~18 20 - ~nd 203-20 are selectable by different fields c~n~ained in ~he microinstructions read out into regi.~tex 201~15.. The scratch pad memory 203-10 receives data ~ignals applied frorQ one of a pair of output buses selectively connected to any one of four working registers of block 204-12.
Each set of 16 registers include~ a process state register ~PS~) location (general register 0) for storing in~ormation essential to controlling the current pr~ce~s. The ~irst eight bit positions o the regi3ter stores steering in~or~ation coded .
to identify the interxup~ing modulev The next po~ition is a privilege bit position coded to idanti~y the mode of operation : - -.

- . .
5~ : - . . :;
. ' ' ' :.
- ~ , (i.e. master or slave). The register also includes an external register bit position coded to indicatP wheth~r the r~gistex contents can be altere~, an aadre~s mode bit position~ two conditi~n ~ode bit positions, a carry ~lit position and 22 bit positions for storing a count which is periodically decrement~d while the asso~iated p~OC~55 iS active (i . e O s~rv~s as a "process timer" ) . Because o~ the frequency of acces~ to the contents c-f the process state register required for ~odification or reference, signals representative of the contents of this register are stored in one of the~registers o~ the processing seation ~04 (i.e. register ~04-20). Thus~ the general register storage location for storing the content~ o ~he process state register serves to store the current ~alue o~ the process 6tate reglst~r of section 204 upon the occurre~ce of an intexrupt~
15Each group of registers further includes an instruction counter (general register 1~ for storing ~he address of the current instruction of the proce.ss associated therewi~A.
Additionally, each group o registers include a page table - base register (general register lS), and a number of general r~gisters (general regi~ter~ 2-14) ~or providing t~lporary storage for opexands and address information~ The scratch pad - memory 203-10 also includes a control hlock base (CB~) regist~r location which stores an absolute address pointing to the base .
of an exception control block and interrupt control block~tables stored in local memory module 500. The irst ragi~ter GR0 of the highest priority set of registers ~level 0) which is never . altered, store~ the control block ba~e in~ormation~ The i~terrupt control block ~IC~) tabl~ include 256 groups of . ~torage locations which ~kore information ~or proc~ss.ing thQ
30 ~ type of interrupt. The exception oontrol block (EC~) tables include 16 groups of storage locations which ~tore info~mation .
for processing the type of exception.
.
.' .
36~

.
., .. , . ~ . . . . . . .

~ , 3 Exceptio~s are proce~sor detect~d conditions which c~u~e ~he pxocessor ~00 t~ e~r ~utomatically on~ of the 1~ Qpo ~ion proces~l ng routin~s . The ~xception ~son~i~ion~ ar~ ~d~
ti~ie~ by a four bit excep~ion number which ~rre~pona~ ~o bits 10 13 of the program in~truction wh~n ~he proces~or enter~ master mode. In al 1 oth~r in~t:ance , ithe exc~p~ion number i~ ZERO. The excep~ion num~er (EC~ 3 is u~d to ~d~n-tl~y one of the ~our word exoeptlon ct)ntr~l bloclcs (:~;CB) which po,ints to an exception process1ng routine. The ~rte addre~;
of an ECB equa1s th~ con~rol b1Ock base (CBB) - 16 (ECB ~
~:ach ECR inc1udes value~ or 1O~ding ~he PSR, IC~ ~nd P~BR
register~ in additlon to a savlng area po:Lnt~r in ~ 0 which points to a ctac:k area :Eor storing ~infoxmat.~orl pertinent. to ~he current procass before the proce~so~ 200 enter~ ~he excep-lS tion routine.
~he addx~ss of an interrupt contro1 b1OCk (IC~3) equal~:-th~ control block ba~e (CBB1 + 16 ~ICB#) . The ICB# is D~taine~
from the ~interrupt word as exp1ained her~31nO ~imilarly~ th~:
IC~ is a four word b1~ck an~ i~ con~ains ~ralu~s for ~he: Pg~, .
2 0 IC, ~ GR14, and PT: 3R reg1skers .

This ~sGtion per:Eorm~ all of the arith~netic and logic operat~ on~ required. to p~oce~s program ins~ruc~ion~ . The ~e~-~ ~ tlon 204 include~ adtler/~hiLfter L~nit 204 1 c~ap~bl~ O~ per~
- 25 ~ormin~ ari hmetic~ ~hi~t, and logic operat1ons upon a palx o~ 36 bit oper~nd~. The result~ produced ~y e~the:r an ad~lex portion or ~h~Eter portion Q unit 204 1 ar~ ~le~ted in xe-~ps~n~e to microin3truction~ an~ therea:E~er ~ ct1Yely .
: ~ ' . ,: . : , ' ' ' ' . :

" ~ -37-.: . . . . ..... ... .~ . . .. .. .

transferred via a four position data selector switch 204 8 on a pair of output lines to any one of the working regist2rs of block 204-12 and to a data ou~put reg~ster 20~-14. The data output regi~ter 20~ connect9 to the lines of the p~ocessor 5 data interface 600.
For the purposes of the present invention, the adder/shifter unit 204 1 can be considered conventional in design. ~lso, the unit 204-1 may include either circuits such ~s those disclosed in U,5 ~-B ~PatentA3,811,039 to John P. Stafford or circuits di-qclosed in 10 other ~ocuments r~ferenced in the in~roductory portion of the present speci~ic~tion~
The b}ock~204-12 includes four working registers R0 through R3 which provîde temporary storage for the instruction counter and for addresses during instruction executionO The registers 15 can be loaded from any one of the sources connected to switch - 204-8 (i.e. adder/shifter 204;-l, addres~ switch 204~, psn/pcR
- switch 204-2~ and scra~.ch pad bu~f2r input ~witch 203-18~.. The ~ , register to be loaded and the wxite signal required or loading the register is established by fields included withi~ the micro~
instruction read out to register 201-15.
As seen from Figure 2, the xegi~texs axe connected to a pair of output buse8 W~P and WRR. The WRP bus connects to address inputs 204-5, to switch 203-18 and t~ scratch pad memory 203~10. The WRR bus con~ects to ~ operand ~witch 203-23 to B opexand switch 204-1, to regi~ter 204~a and to register 204-22. The xegister~ selected for ~onnection ko ~he WR~ and WRP busP~ axe designated by a pair of fleld~ in~luded within ~he microinstruction read o~t to regi~t2r 201~15~

: ~ , . . .

3~-~;' . :,. '. ' . ' ~ : . , , .............. . .
.. ~ ....... .. . .. ~ . .
. ~

;, I
As seen from Fiyure 2, the proc~ss.iny s~ction 204 in-~:~ cludes process s~at~ ~gis~er ~04-20 and a proce~s control regist2r 204-22. ~he proce~3 ~tate reglster 204~2~, as men~
tioned, i8 loaded from scra~ch pad me~ory 203-10 ~ria output bus WR~. The process control regis~er 204-22 is a 36 bit register co~mon to all eight in~exxup~ level~.
~he bit position~ of the pro~ess control r~gist~r 204-22 contain the ~ollowing information. Bi~ po~i~lons 0-8 designate different type~ of excep~lons which include the following~
PCR BIT POSITION EXC~PTION TYPE
0 Operation not aomplete; no re~p~nse ` from SIU on lines ARA or ARD~.
1 P~ge address~bounds ault (key check).
2 Page acre~s faul~.
3 Page not resident in memory~
4 Illegal operation linvalid in~truc-- tion~ illegal slave instruction, ox - . illegal ~lave operation~
.- ~ - .
~ Proce~s tLm~r run out~
6 Overfliow~.
7 Lockup ~ault.
8 Address mlsal.ignment.
The ter~ llfault" does ~ot neces,sarily mean the occurrence of 25 a hardware ailure, but includes programming exxor~, e~c.
Bit positions 9-12 store the parity errors det2cted per : data path substrate~ Blt poAit~on 13 lndicates when a parlty :~ error is dete~ted i~ the ~ata In x~gister~ ~it positions 1~-15 :, , .
store indication3 of parity error~ detecl:ed per control s~ore 30 and pathfinder memory. E3.it lS ~lgnals no response~ to the level - zero lnterrupt presen~ BLt po~ition3 23~-26 identi~ the pro~
, . .
:- - . 39 .. . . . .... . . ..

i3 ce sor number and level received from the PNID and A~
l3it po9ition 27 i8 an in~er~upt inhlbit blt position while .
b~t po8itlon5 2~-35 stc~re intarrupt reque~t bit~ which, when s~t to a binary O~E, lndica~e an interrup~ reque~ to a l~v~l correspondin~f ~o ~he bit po~ition (i~o ~ ~it 28 = level 0~ ~
The bi~ posltions 27-35 are loaded bY pxogram llls~ruc~ion ~rom th~ b~.nk of regi~ers of block 204-12 via output bu~ WRR. Bit po~tion 35 is alway~ ~et ~o a b~na~ O~E.
l'he conten~s of each of ~he register~ 204~20 and 204-22 are selectively applied as ar~ ~ npu~ to another one of the po~
sitions o~ the fc>ur po~ition data selector ~wit~ 204-8 via a twn posit~on data ~elec:tor switch :204-24. Th~ register 244-20 also connect~ to the PI po~i~ion~ of a two position steerlng sQ~lector switch 204-10 and a four po~ition addre~ sale~tor switch 204 ~. .
~he ~teering switch 2û4-10 provides ~erin~ :I nformatlon - to the SIU 100 which i~ used to tran~fex the co~nand to the correct mc~dule. One o~ ~he fl~Id~ containsd in th~ microin-8tXUction8 read out to register 201-15 seI~ct~ the appropr~ate po5ition ~or elther a m~mory con~nand or PI co~nand,r The ste~ring in~ormat~on ~or a memoxy c~mmand. is generated ~rom ~ields included with.in ~he m1croinstruction and with paged addre~s information from scrat(:h pad memory .204-4 or absolute ~ ¦
address inorma~ion ~rom bu~
In the case o~ a PI conunand, the steexing information is ~enerated a~ follows; bit a i~ for¢ed ~o A binary 02;1E :Eor a PI command; blts 1-4 co~respond ~o bi~ 0~3 og reyi~t~r 204-20;
. and bit~ 5~6 correspond ~o bi~ of one e)~ ~he 1eld3 oE ~he~
- : microinstruction~ wh`lch are coded to de~lgnate whe her i~ i~
a single or double word tran~fer and wh~ther it i~ a read o~
s~rite cycle of operation. Upon the ~kart o~ a ~mory oycle or inlti~ti on of a command, the ~ignal~3 frorn t~e ~teering ~wi~h 4 0 ~
5~3 204~10 are loaded into a ~eeri.ng regi~t3r 204-16 which ap-plie~ the s~gn~ t} e appropr:i a~e l~nes o~ ~h~ da~a lr~ter~
~c~ 600 of processor 2~0. As explalne~ h~rein, the c~ d including additional ~eering i.n:~ormation :~8 pro~ide~ by po- I
S ~itit:n 2 of addre3~ switah 204- 6 in the ca6e o~ a PI comman~ j AS also ~e~n from Figure 2, proc~ssing ~ectiorl 20~ in-clude~ a ~cratch pad m~mory 204~4 addres~able via adares~
input~ 204-5 which receives address signal~ ~rom one o .
the regi ster~ conr~ected to th2 w~P bus . The saratch pad 10 me~ory 204-4 provide~ page tabl~ word toxage for each of the eigh~ interrupt leveI~ u~ed in genera~,ing a~:~olute addre~-3e8 ~or addre~sin~ local memory module 500. ~en aadres~ed, the con~ents of ~he s~or~gE: loc:atlorl of sc:ratch pac~ memory .
204 4 are read ou~ to ~w~ of the ~our pD~i~ionS ~:~ the ad 15 dre~ switch 2~4-6. Thes~ two positions are u~ed for page .
referencing of local memory modul~ 500~ Sin¢e the paglny - operations of scratch pa~ memory 204-4 are no* particularly .
per~nt to thei! present invention, no detailed discu~ion is included herein. ~ For ~urther- information re~arding the .
20 use o~ paged addressing~ re~exence may be made to the docu~
ments ~ited at the in~roductc~ry por~ion of ~h~ specification.~ ;
~he othèr tw~ positions of the addres~ ~electc)r switch X04-
6 are used to prov~ de ~he memory or PI co~nand. Mc)re speci~i~
cally, position~ O and 1 of addre~s switch 204-6 ~ when ~elec~
2S ted by àa addr~9 control ~ield of a micxo~Ilstructlon word stored in regl~er ~01-15, generate~ the R/W memory commzlnd in~ormation w~ich includes bit~ 0-8 coded in accordance wl~h predetermlned ~ields o~ the mlcroin~truc~ion woxd and. bl~
- . ~ 9 -35. coded to ~orrespond to either page~ ~dtlre~s iniEorma~io .

` !
'' ' ' ' " 11 ~ ' . ' , . .
- -4~

.
.. . . . . . . ..
,. . .,, ., ,. . . ~ , .

~o~ m~mory 20~4 (po~;itls:n 0) or ~olu~e a~dxess 3:~its ap-- pli~ to ou~pu~ ~U8 WR~ by the workir~g regi~t~;r~ o~ bloclc 204-12 (po~it~:on 1~. When ~he PI pos~tion o swltch 20~6 1~
s~Iected " t~e ~3wltch generates a progra;nmab~ e ln~erac~ com-5 mand word wher~in i;i.t O is a binary ZE:RO? bit 1 .i~ suppliE3tl by a field of the microin~truct~n woxd stored in reqister 201-lS~ ;
bi~ 2 is -~upplie~ by bit 9 of ~?SR regi~t~3r 2~4-2~ and aef:3 ~ea wh~ther the c~rrent process cal~ alter certaln external r~gis-t~r~, bits 5-8 ar~ equal to bi~ 7 o~ regis~er 204~20 ar~d 10 de~in2 the port or s~-chanrlel wi~hin ~he module; ~ 3 is coded to specify the processor pa~r n~ber ~upplied by the SIU 100, bit 4 i~3 a z~sRo and bits 9-35 eq~aI bits 9-35 af bu WRP which correspond to ~he absc)lut~ addre~s o~ the ~x cs:r~and~

E~ror Detect~on Cl~cuit~ 201-3~ - F~
.
In addition to thle above ~escrlbed circuits, each IOP
processor include~ error de~ec:tis:n circu~ conven~ional ~n de~ign, ~uch as parity checlc c~rcuit~, whlch per~Eorm check~
on the vaxiou~ stor~e s~ction~ of each in~u~/out.pu proce~
so~- a~ explained herein. The bloclc 201-32 alsc: ~uppli~ ~19 20 nal~ to the vaxiou line6 o~ interface ~0~1 as explained here in.
Although shown as a ~ingle block, it will ~e appr~ciated that the pàrity generation and check . cir~uits are loaated a~
~rarious points throughout the proce~sor 2û0 a For ~xampl~, ~e 2S ~our parlty bits for data storesE is~ yener~l ~egl~ter 1ocati~n~
o scratc~i pad 203-lo are genexate~i by C~XCllit~ co~ecte~ to the input bus to the s~ratah pad 203~10. Parity circuits con-necte~ ~o SPB regis~er ou~put ch~ck ~h~ ou~put ~lgnal~ ~or ` ,`,` `~ ` ' .:
: . . , ~;
. ~
--~ 2-- . : ` J~ ' . . . . .

. .. , , . .. , . , j 3t5~3 corr~ct pari~y~ Similarly~ parity generation circuit~ gener-a~e parity for signals a~ ~he Oll~pUt of B operand ~wi~ch 204-l to be wri~ten into ~he PTW scratch pad 204-4. The parlky o~
each byt~ read out f~om P~W scratch pad 204-4 i5 ch~.cked by parity check circuits located at the input to address 3witch 204-6~
- Additionally, the control store 201-lO and pa~hflnder memory 201-2 in lude parity check circuits for d0tecting the presence o single bit ailures in memory locations. The oc-currence of an error sets the corresponding control store bit(i.e., bit positions 14-15) o PCR re.gister 204-22. Furthe~, pa~ity circuits connecte.d to tlle Da~a In register 204-18 check all data and instruction~ ¢1ocked .into the Da~a In register 204-18. A parity error detected-on data ~rom ~he SIU 100 sets the corresponding substrate parity error bit (i.eO r ~it.
positions 9 12) or the bad byte and ~he Data In bi~ positic,n 13 of PCR register 204-22.
The block 201~32 includes OR logic circuits which a.re connected to receive signal indications of the parity ~rror bits s~ored in PCR register 204~22... One group of these cir-~.
cuits provides a resultant signal to line P~D which corres~
ponds to the logical OR o~ the parlty error signals~
.' . ' .

.
, -.

43- ~
. . ... .

..... .. . . . . . . . .
I

~ la~ group o circui~ per~lne!n~ ~o ~he ope.ra~io~
oi~ th~ pre~ent i nv~ntion incluae~ th0 clrcuit ~ bloG3c~
201-34, 201 36, and ~01-38. ~lock 201~34 inclu~ a nlne 5 stage co~nter, con~rentior~al ln tlesign, controlled by the c lrcuits of block :20ir36. Th8 c:ounter sex~res a~ a "level . zero" timer whi~:h detect~ when proces~or 200 ~oe~ not r~-spond tc: aI~ interrapt x~qu~t within a period equal to twice the operation-no~- comple te time in~rval, In greater de~ail, l;he colmter is init Lali~ed. to a ~ero s~-a~e by the circui~ of block 201-36 a~ long a~ ~he I,ZP line remains at a binary æERO~ When the ~ZP line ~witches to ~ b~nary ON~5, the circùi~s of block 2Ql-36 remov~ the initialize signal and the cou~ter starts run-15 nlng or i~c:rea3e~ its ce7unt by.one i.n r~ps:~n~a to each PDA
signal from ~he circuits o~ bloclc 201-30.~ ~en i~ r~Ghe~ .
a maximum count ~all binary 0~ 3) and ~he ~IL lin~ still hav~ not been swl~ched to a Z:ERO ~tat.e, ~ie counter gener ate~ an ou~put which ~orces bit~ po~i~ion 1~ of ~h~ PCR re-20 gister 2~4-22 to a binary O~;IE~
The incremen~ing of ~he counter o~ block 201-34 is stopped by ~he circuit~ of block 2ûl 36 when either l:he AIL line3 are swi~ched ~o Z~;RO or ~he LZP line is ~wi~ched to Z~O by SIU 100. The ~ignal~ a~o initia1ize ~he counter.
~5 Las~ly, the circui~s 2Ql-36 apply the ~ig~al~ on the INIT
line a~ an input to switch ~ 14~. When the SXU 100 for~e~
- t~e INIT line to a binaxy ONE, ~hi~ ini~ialize~ or clear~
th~ contents o~ the variou~ regl~ex~ wi~hin ~h~ proce~30r 200 (i.e., PC,R regi~er 20Ds~22)~ When re~et; the proces~or ..
' ~ 4 4 ~

. ... . . . , . . , .. - : , . . . . . . . ..
I

200 begins exec~uion o an initializat~ on routine in con~
trol~ ~toxe 20~10.
~ he circ~ui~s of block 20I~ include s~ ral ~ and ANI: gates~ The~e clrcul~ are u~ed to foxce he TBL li~
5 to a binary ONE. ~he ~BL line i.s foxce~ os~ when }~it po~i-tion 16 of the PCR register 204~22 has been se~ as a resul~
o~ a "time c~ut" prior to the SIIJ swi~c:hing of th~ E>roc:e~sor 200 into letrel zero. That is, ~ignal~ c~rre~pC~n~in~ ~o blt position 16 and the level bit positiorls 24-26 are ~ ed"

10 such that the TBL line is switGhed on when b~ t po8it:ion 16 is a binary ONE and l:he PCR bits indicate ~hat the proce~sor is not in level zero.. Another group of circu:Lts provide a logical OR of the exaep~ion`bit signals stored in ~'CR regist~r 204 22 ~i.e., bit po~3itions 0-8). The output is ~en ~NDed with the level bl~ 24-~6 o~ the PCR regi~ex -~04-~2 0 ~IUS
when ~he processor has been ~wi.tched to le~7el 0, any one O~
the excep~ion ~gnal~ forces ~he TB~ line to a binary ON:~.
EIowever, prior to the proce~sor 2U0 being ~ chea to le~
zero, exception ~ign~ls . are inhib~ ~ed ~rom $wi~c~hlng th 20 ~BL line to a binary ONE. The raa~on for this is that durl~
an initial self te~t operation, the time that a~ error occurs thàre could already be an exceptl~n sign~ï st~red in ~he PCR
regi~ter 204-22 and i~ i~ de~ira~le that thi~ not be de~ect ed a~ a trouble indication. That i5 9 a J3p~CifiC ~:e~
2S testl is used ~o establi~}l ~rouble indica~ion~, a6 explalned .
her~in.

.' ' , ' : ~' ~ ' X~
`'"' : ' ' . ~
i.!
' . ~ . - .. .. ~ . .

~lC~

DETAILED DESCRIPTIO~ OF SYSTEM INTERFACE UNIT 100 Interrupt Section 101 The system Interface ~nit 100, as mentioned, provides for communication between modules of the system of Figure 1 via a plurality of crossbar switches. Separate crossbar switches are used to collect signals from the lines of each of the different interfaces of the modules. Figure 3a shows the switches and circuits of interrupt section 101 for hand-ling the module interrupt interfaces. In the system of Fig-ure 1, there are modules which connect to ports LMO, A, E, G, and J, each of which applies signals to the SIU 100 via different ones of the lines of its interrupt interface 602.
Additionally, SIU 100 also provides signals via an interrupt interface associated with port L of Figure l.
As seen from Figure 3a, each of the modules when re-questing service applies a signal on its interrupt request (IR) line together with appropriate interrupt identifier information on its IDA lines which are applied to the cir-cuits of an interrupt priority and control block 101-2. The circuits of block 101-2 monitor all interrupt lnterfaces `
and signals the appropriate processor pair 200-0 referred to herein as processor 200 when there is a request having a priority higher than that of the process being executed.
~hen processor 200 signals that it is able to accept the request, the SIU 100 gates the identifier information asso-ciated with the highest priority request to the processor. The - ~6 -.

idoritlfi2r ln:Eoxma~ion incluae~ zm eight bit ln~errupt con trol block mlrbber Lncluding ~ parlty bit, a tlu:~e ~it ~nr terrup~ level ~aun~er ~nd a on~ b~ proc~sor n~r Wi~
pa~ity bl~; and a ~our bit c:hann~1 n~er.
S l;:on~idering interrupt ~ction 101 ln great~r de~ailr tha clrcuit~ o` blc~ck 101-2 include deeo~r circult~ which decode the proca~or number an~l interrupt xeçtue~t signals.
- Prc~viding ~at t,here ~ ~ no pari.ty erxor, ~he output ~l~nal~
from ~he ~ecoder c~rcu1t~ are ~pplied to priority logic oir~--10 ~uit~ o~ tha de ignated proc:~ssor log~c: circuit~. The pri-ority logic:: circuiks dec:o~le th~ intarrupt le~el s~gnal~ and d~eter~iline the highe6t priori~y lev~l and ~hen dl3te~rmine the:
poxt priority ~o that thb module hav~ng th~ highest~ prloxity .
level and highest port priority i8 ~selected. ~he int~rrupt . 15 port priority with~n any ~iven level is :a& follow6: .
. .
. Old; port I.; port A, pc~r~ B,~ por~ C; p~r~ D; port Æ;
-: port F, port G; port H; port J and ~port K. :
This means that in the system of Figure 1 the p~3rt of the - cuxx~nt p~oces~ has the highbst priority ~ollowed by the -? SIU 100, ~he hlgh speed multiplexer 300, th~ ho~t proGes~30r 700, th;e pro~e~or 200, and the low speed mul~ipl~xer D"oO.
The priority circuits of block 101-2 are opera~ive to ; ~
generate an output signal ~n one of n ~umber of c~u~pll~ lines, n coxxesponds tQ the n1~ er o~ intf~rrupting modules within the .
, , - `

..

system. The n output lines are applied to an eight position data selector switch 101-4 whic:h selects the interrupt level signals of a level of interrupt having a priorlty higher than the . level currently in pro~ress to be loaded into a regis~ex 101-6.
The output signals from regis~er 1.01~6 are applied to the AIL
1ines when processor 200 forces the IR line to a binary ONE
in response to the SIU 100 having forced p~ior to the higher level interrupt present (~I~IPj l.ine or the level ze.ro present:
. (LZP) Iine to a binary ONE. Whan the current proc~ss i.s not inhibited from bein~ interrupte~, an interrupt request c~uses the processor 200 to suspend the current process and to accept an interrupt word ~rom the SIU 100 including ~he identlfiex informatlon mentioned previou~lyO More speciflcally, the interrupt word is formatted as follows.

Bit O is a ~ew interrupt bit position. When set:to a binary ONE indicates that the interrupt is a new one and when set to a binary ZE:RO indicates that the . interrupt is that of a pre~iously intexrupted process ::
~ that is to be resumed.

Bits 1-17 are unused and are binary ZEROS~

Bits 18-27 define the- interrupt control block number wit:h bits 18 and 27 bein~ set to binary æEROS~ :

Bits 28-31 are ganerated by the SIU 100 and identify the source module as explained herein in accordance with ~he present invention.

Bits 3~-35 are generated by ~he module3 having multiple .
ports and identify the:subchannel or port wlthin the source ~` module as explaine~d here~n in accordance wi-th the present invention 7 ~

'' ` ' ` ` ' ' ' ~ ' : . 4~

. .
~- .: . . . . . , . ... .. ,.. ... . 1 . .. ., ~ . .

For more ~etailed informati.on regarding the imple~mentation of the circuits of block 101-2, reference may be made to the copending patent application ti~.led "Priori~.y Interrupt llardware"

referenced in the introductory port~on of the ~peclfication.

It is also seen that the output lines from interrupt priority circuits 101-2 are applied to a further data selector ~witch circuit 101 8. Since only the reque5ting module having the highest priority will apply a signal to selector circuit 101-B, the selector circuit is connected to provide a predete~mined wire~-in set ~f coded steering signals which identify the physical-port to which the requesting mo~ule granted priority cOnnects (i.eO-bits 28-31 of the interrupt word), In the present embodiment, the following steering cod~s are generated for~identifying the module~ of Figure 1, CODE SIU PO ~ IDENTIFIED

- 0000 : Local memory module - por~ ~O

` 000i port K : .

0010 SIU 100 - port L
Ol~l Low speed multiplexer 400 - port: J
0110 processor 200 ~ port G
- : I101 . high speed multiplexer 300 - port A
1110 host processor 700 - port E.

The foux bit code generated by the selector cixcuit lO1~8 is in turn applied to a group of conventional AND gat.ing circuits included within a ga~ing ne~work 101-12. The other identif~i~r , information provided hy the different ~ouxce sy~tem modules are also applied to othex gating circuit~ of network lO1-12.
.
, . , ~ ~., . ~
'~ . . : ' ' ' ~ I
. ~
''' '- . , ~ . ` ' , ~ 49- ~

. .

Specifically, each module applies an interrupt co~t~ol block number (ICB~) via its IDA lines to a dlff~rent one of the positions of an eight position data selector switch circuit 101-14~ Additionally, each modul.e provides the information identifying the requesting sub(,hannel or port of the source module to other ones o the CJating ~ircuits of network 101-12 via the IMID lines of the interrupt in~erface. When the processor 200 forces its interrupt data req~le~t (IDR) line to a binary ONE, the SIU 100 applies the signals from gating 10 network 101-12 to the data from SIU tDFS) bus lines of the processor data interface 60~0 via one of the positions of a fou~r posltion data selector swltch circuit 101-~0. The other :
positions o~ switch 101-20 are not shown since they are not pertinent to an understanding of ~l~e present inveniion.

15 . Data Tra s ~ 102 ' Fi~ure 3b shows tlle data transfer section ].02 of the syst:~m interface unit 100. I'llis section inclu~es pr~ority circuits ` ~ `
which establishes which 90UrCe module is to trans~er commands to the high speed multiplexer 300 on ll:s programmable .interface :
2~ 601 and whicll source module is to transfer:data to the multiplex~r : ~.
300 on its data lnterface 6no . Additlonally~ section 102 i.ncludes prlority circuits which determine. whioh source module i5 ~oin~
to transer ~ither data o~ commands to local memory modu}~

~ ~ 500.

. .

~. . , :: .
, ~, i, - --SO~

, It will be appreciated that transfers between a pair of modules occurs when one module has generated a request to the other module and that the request has been accepted by the other module. In order for a request to be accepted, the re~uestinq module must have the highest priority, both modules mus-t be in a state to receive information and that the transfer path over which the transfer is to ~ake place must be availahle (i.e. not busy)~ ~
As concerns the signals applled to section 102 by processor 200, the generation of these signals iq to a large extent controlled by the different fields o the microinstructlons read out into proces:sor register 201-l~ of Fiyure 2. For example, the active output port request (A~PR) line from processor ~00 applied to the circuits oE b~lock 102-4 is enabled in ~ccordance with a SIU request type controI bit field of ea~h microinstruction read ou~ to register 201-15:which is coded t~
define a transfer of a read/write memory or programmable inte:~face command. The data to SIU lines (DTS) of the processor data - interface 600 applied to a two position data selectc~r switch 102-2 constitute command information genera~ed unde~ microproqram control whic}l i9 loaded into the processor data outE)ut register`
204-14 of Figure 2. Tlle steering data to 5IU (SDTS) llnes receive signals generated under microprogram control which are loaded into,the processor steering register 204~16 of Figure 2. - '~

.

' ` -51- , .

.

^; ~ . .... ' s ~, ~3~

For th~ system of Figure 1, only I/O processoLs transfer ~ommands to the multiplexer 500 only and processor 200 applies signals to network 102-4. Tile network 102 4 ther fore includes decoder circuits which decode the steeLing information ~rom the processor module to establish when the module desires to transfer commands to the multiplexer 300. In the case of more - than one I/O processor when more t;han one module desires to transfer during the same cycle, a priority network included in network 102-4 selects the module assigned the highest priority and enables the transfer of a command by that modhlle to the multlplexer 300 on the PDFS lines of its progxammable interface 601. More speci~lcally, the network 102-4 apPlies signals to.the two position selector switch 102-2 which selects . signa].s from the appropriate module~ This occurs when the 15 multiplexer 300 signals the SIU 100 that lt is~ready to accept '' a command by forcing the PIR line to a binar~ ON~. At the ~ ¦
same time, network 102-4 forces the APC llne to a binary O~E

signaling the multiplexer 300 to accept the command applled to ..
- ~he P~FS lines. When the proce6sor 200 executes an instru~tion , causing it to send a programmable interface (PI) command to.the multiplexer 300, the processor 200 places the processor number ~ ~ .
- identification into bit 3 of the command, The multiplexer 300 ~ ~ stores the processor num~er contained in the command until it .. wants to issue an interrupt request at which;time the processor number lS included as part of the interrupt data a~3 explalned . herein. When the PI command i.s orwarded to multiplexer 3VQ, the steering information identifying pro~essor 20n as the . requester is stored in a register 102-6 associatcd with multipl~x2r . : 300 (port A). As explained.hereillr when multiplexer 300 responds ; 30 -by generating la read data transfer ~eque~t to SIU 100, the contents o register 102-6 is used to identify processor 200 . as the actual module to receiv~ the.data.
.. . , ~ :
.` ' ~ 52-$3 A similar arrangement: is employed for transferring data signals to multiplexer 300. In Figure l, memory module 500 is the only modul~ which trans~ers data to multiplexer 300.
Such transfer Occurs in response to a read memory command (ZAC) forwarded to the me~nory module 'i00 by multiplexer 300 v.ia network 102-20 as explained herein. W11en multiple~er 300 forwards the comma~d, the SIU l00 generate~ the appropriate ~
~it requestor identifier c:ode ~steering code)~ which it appen,~s to the multiport identifier information received from multiplexer 300O The information is stored by the memvry module 500 and returned to t11e SIU l00 when the module 500 genérates a read data transfer request to desigr.ate that multiplexer 300 is to receive the data. Also, when t.he SIU l00 accepts the reques , it noti fies the multip:lexer 300 by forcing line ARI)A to a binary .
15 OWE.
The read data transer re~uest (RDTR) line when set by memory module 500 s1gnals the ~twork 102-~4 that i.t is ready to transfer information read out during a c~cle o:~: opera~ion.

The local memory module 500 al~o supplies signals to the ~requestor identifier from memory (RIFM) lines ~o iden~ify ~he requestilig modulP to which the informi~tion is to be transferred. ~ :
. More speciically, circuits within a decoder ~etwork 102-14 decode the identify signa].s applied to the RIFM lines and when the signals indlcate that the local memory moclule 500 is ready to transfer information to ~he multiplexer 300 ~s~umed the multi~
plexer 300 is ready to receive the l~Eormatio~, the decod~r ~
network 102-14 applies the appropria'ce siynals to the~ ~elec~or - ~witch 102-12 and circuits within a gating network 102-l6.

.
. .
, ~ 53~

. - - ' ~ ' Addltionally, decoder net:work 102-14 applies a slgT~al to the accept r~ad .dat~ (~RDA3 li.ne of the da~a interfare ~ al~
:: ing th~ mul~iple~er ~00 that it ia ~:o accept ~he dat~: rom SIU
-(DE'S) ~ines of it~ in~e~:face 60û. The c~rcult3 o:E block 1~2~ . .
16 apply the appropriate mul~i.port ident~ Eier in:~ormatlon to multiport idantifier fr-om SIU ~MIFS) line6 ldenti~ying the requesting subchannel which i~ obtained from the ~ [ llnes.
When the transfer ha~ taken place, the networl~ 102~14 force~
the RDAA lin~ to a binary O~ ~ignaIing the reque~tlng module:
that the data has been ~cceptedD~ memory module 500.
~ n arrangement slmilar ~o netw~rk 102-1~ is tlsed b~y SIU
lnO ~o tran~fer PI and memory coDmaDd8 rom a~ one of th:e modules of Figure i to local memory module 500. The ~odule 5~0 is operati~ to force either t:].~e programmable inkerface reque~t (PIR) line or ZA~ interf~ce rçque~t (ZIRj li.ne applied ~o a - de-coder ne~work 102-20 to ~ binary ONE when it is ready 'co accept eit~ier a progranmlable interface or memory comrnand. Additionally, - .
thè p*oCessQr 2~0, the processor 700, and multiplexer 3Q0 app~y a net.work 102-20 Aignal~ to t~e act~ve output por~ request 2~ . (AOPR) line and s~eerlng da~a to SIli lines of the~r respect:ive data interaces. The network 102~20 upon decoding the steering informatior~- ~pplied by each of th~ module~ i8 operative ~o ~ènerate ~he ~ppropriate 8ignal.s t`o a three posi~io~ selec~or switch 102-24 for enabling t~e modu~e having the highest priority to apply slgnal6 to the data t:ransèr to SII~ line~ of memory module datà interfal~e 603. It 1~ alao seen thQ~c network 1~2~20 applies BignalR ~o either the accept programmable comm~d (APC) l~ne or accep~ ZAC colr~and mode (AZC) together wit:h the ~ppro-pria~e xequestor identlfica~ion signal.~ on the reque~t ider~
- fier ~co memory (RITM) l:Lnes o the local memory module inter-~ac.e ~03 via a gating network l02-26.

.
.
!j4 - , . . . :. . .
: ,-, :. .... ., .... .. ... : . .. . ... .. . . ..

3~ ,3 The last two networks 102-30 and 102-40 are used ~o transfex memory data and procTra~nable interface data to processor 200 in response to memory commands and PI commands xespectively prevlou~ly generate~-~ by the processor 200. As seen from Figure 3b, the priority decoder network 102~30 h~s the same input lines as network 102-14 and operate$ in the same ~anner to forward the requested memory data to ~rocessor 200 via a data selector switch 102-32 and -~he ~our positicn selector switch 101-20 of Figure 3a. ]:t will be apprecia~ed that since processor ?00 processes a single com~land at a time, there can be no conflict between the modules applyinc3 data to selector switch 101-20 for transfer to the processor DFS lines in response to proce~sor requests. That is, after the processor 200 sends a command to one of the modules o~ Figure 1, it~
~15 operation is stalled pendincJ rect~ ipt of the requested dat~.
The SIU 100 upon a~cepting the processor's request forces the `
processor's ARA line which causes the processor to del~y operatlons.'~
The`separate network 102-40 processes return data reques~s ~ from~thoae modules responding to PI commands. ~he network 102-40 decodes the signa~s applied to the ~TR lines and from .
register 102-6 together With registers of the otber modules, n~t shown. When the ~IU 100 detects that module is trying to return requested data to pro~e~st~x 200 ~i.e~ requestor iden~i~ie~
- stored in multiplexer 300 registt-~r 102-6), the ne~worX 10;>-~40 generates signals which conditioIIs a three position data ~selector circuit 102-~2 to ~pply *he sit~nalg from the PDTS

, ! ' ' ~ ' , ' , ' , ' ' ' ' , ' `:
`, : ' ` , . :, ~ - ~55~ ~ ;

~S~ i3 - line~ of the PI lr.terface oE the Module trying to return requested data ~o processor 200. These ~ignal~ are in turn applied to ~he processor ' ~ DFS line~ vi.a selector switch . 101-20 of Figure 3a whlch is conditioned by the module-request si~nal. During a next cycle o~ operation, the neL~ork :L02-40 forces the RDAA line to a binary ONE sign~lin~ th~ modu~e that the data applied to the PDTS 3.~nes has been accep~ed and tha~
the module ~an now remo~e such data (i.e., clear its output register). Thus, it is seen that switch 101-~0 selective].y applies an~ one o~ three types o data ~o the DFS line~ of the processor's data interface 600.
For the purpose of the present inventiOn, the circuits included within dif~erent ones of the bloc~fl of F~gure 3b may be consldered conventional in design and lnclude loglc circuits ound in the afor~mentio~led publlcation by Te~as Instruments Inc. Al~o, for the purpose~ o the present invention, the swi~ching nstworks can:compri~e eonvention~l cros~bar switche~.

.
~ Cuntrol Section 103 .
Fi~ure 3c shows in block diagram form section~l03 o the system interface un.it 100. Thl~ section incLIldes compare and con~rol logic circuit~ 10~10 and lU3-1l for loglcal pro-cessor pair~ 2.00-0 and 200-1. Sln~e these circuit~ are du-plicated for each processor pair, only one ls shown in detall herein (i.e., Figure 3d). Also included are the circuit~ of blocks 103-20, 103-24, and 103-25 whlch connect to ~ PI inter fa~e 6Q3 and ~nterpret ar.d execute Pt co ~ ands directed to t:he SI~I internal logic circuit~ ~hrough port ~.
As seen from Figure 3c, ~he internal logic clrcu~ts ~n .
... . . . : . . :

addition to the circuits which proc~Rs PI co~and3 include an lnternal int~3rrupt con~.ro:L register 103-30 which feeds internal interrup~: loglc c:l~cui~ 103-28. 'rhese circuits in con~truction are sim~lar to the priori~y lnterrup~ logic S circuit~ 101 shown in Figur~ 3a. The internal lnt~rrupt: logic circuits 103-28 generate 2ight types o:f interrupts. The ln-terrupt types pertinent to the present Lnvention are a~ fol-lows:
1 - in~cerval timer exhaw3t generated by the inter~al timer counting ~hrough zero;
4 = processor error, de~ec~ed wi.th no mi~compare;
5 ~ mis-compar~ error detected along with a pro cessor error; and?
-6 - mLs-compare error w:Lth no other error~ exist:ing.
: . :
~ The inte~rupt prlority withi~ port L i~ based on type . num~el and the priority is as follow~
Ty~?e :~ 4 -- . hlghest :

. 6 . .

O

. 3 -- low~st.
The irlterrupt types 4-7 are hardwired to level 0 while the in~
terrupt levels for other types (i . e ., 0, 1 , 2 , and 3 ) are programmable us~ng the coded level ~ nal9 stored in inter-:

, ' . ' : ' ~ I
: -57- :

' ;

I

- . ~ 3 rupt contro1 regls~er ~03~30 . The circui~s 103-28 ~s~ab~ ish the interrup~ ha~ring the ~ighest priority and g~nera~e ~ppr~-priate request signals wh~ ch are appli~d t~ lthe lnterrup~
lo~ic circuits 101. The format of the reqlle~t is sho~ in S Figure 12. ~s ment1Or~ed, the c1rcuit~ 101 report the inter-rupts to the designated input/~utput procQssor pa~r.
The SIU in~cernal loglc circuits in response to an PJ~EX
instruction to port L enable the con~ents of ~1fferent ones of the registers 103-12 through 1û3-17, regis~er 103~-30 ~
and timer 103-40 to be read ~via a multipositio~ se1~etion switch 103-40. The con~igura~ion register 103-15, as i~ned oc~al address 0, store~ identiXie~ informa~ion and the opera-t~ onal status of all SIU port~ s ~ormatt:ed as showTl - in Figure 8a. The interval timer 103 40 wh~ ch, for the pur pose of the present i~Tention) can be considered convent:lona1 in design lncludes a 24 bit register assi~,ned cc~:al~ ad~ress~
2 for storing a count defining a part1cu1ar. ~ime in~erv~1.
.
'rhe wraparourld register 1~3-17, a ignPd octal address ~, is à working register used by test. a~d clia~nc)stic rout1nes . .
:: The initialize regist.er 103-16, assigrled o-~ta1. address 4, stores ind3cations for select1ve1y initia1izi~g and m~sk~
ing SII' ports. Initializing take6 place :~n responsP to sig-. nals generated by initia11ze contro1 logic c~rcuits o block 103-18. Tha~ is, the regis~er 1û3-1~ is 1Oaded via a W~EX in-struction and the ini~ia1ize bi~ posi~ion~. are res~t 'by the circu~ts 103-18, as e~c~1ained herein. The masking operations ~ake p1ace ir~ a aimi1ar ~a~hion and are nat per~inent to the present invention. T~e format of the re~i.s~er i9 shoe~ -ln .
- - Figt re 8b.

. . .
: . .
.
a- :

5~3 The fault status registers 103-12 and 103-14 are as-signed octal addresses 10 and 7, respectively. Fault s~atus register #l is a 36 bit register used to signal all errors detected by SIU 100 with the exception of processor or mem-ory reported errors. The storage of information relating to an error condition "locks" the register to the first detected error until it is cleared via an RDEX instruction (PI command).
It is formatted as shown in Figure 8c. Fault status register #2 is also a 36 bit register used to signal all processor mis-compare errors and any other faults not stored in fault status register #1. It is formatted as shown in Figure 8d.
As seen from Figure 3c, section 103 also includes parity generation and checking circuits of block 103-35. These cir-cuits~ for the purpose of the present invention, may be con-sidered conventional in design. They generate parity check bi*s for the signals applied to different processor interfaces by each processor and check them against the parity check bit signals furnished by the processor pairs. The results of the parity check are applied as inputs to the compare and control logic circuits associated with the processor pair. Although not shown, the parity circuits 103-35 also receive signals from the processor pair 200-l and furnish result signals to the circuits 103-11.
Detailed description of Section 103 Figures 3d, 3e, and 3f show in greater detail the circuits 103-102, 103-lO0, and 103-18 respectively in addition ~o the cir-cuits associated with registers 103 12 and 103-15 of Figure 3c.
Ref err~ng ' .

~ - 59 -.4~.i ~3~
first to Figur~ 3d/ th.i~ figuxe illus-tr~tes in cletail the ; sequencer control circuits of block 103~102. The ~equencer control circuits include three clocked D type flip~flops 103-130, 103-131, and 103-132, which are enabled by a c:iynal GllCMPE~REN10 applied v.ia an ~ND gate 103-106~ This gate receives a signal AUTOE~CNF~00 normally a binary ONE and a signal ~EG100110 from fault status xegister #2. Signal REG100110 is a binary ONE when a mis-compare is detected o~
ports G and H. The signal SETllGN10, when forced to a binary O~E, switches the Yl flip-flop 103-103 to a binary ON~. Simi~
larly, the signals SET21GH10 and SET31GH10, when forced t~
binary ONES switch flip-flops lQ3-104 aI~d 103-105, respec : tively, to binary ONES. ~ signal RESET10 is used to switch the Y1, Y2, and Y3 flip-flops 103~103 through 103-105 to binary ZEROS. One o~ input sections of the flip~f1ops is shown in greater detail~ It compris~s a pair of M~D gates, - the outputs of ~7hich are connected in a "wired OR~
: The collection of N~ND gates 103-108 through 103-129 yenerate the signa~s SEI~llC.EI10 through SE~13~JEIl~ in response .
to the signals shown. For the most p~xt, these s.ignals cor-respond to output signals from a decoder 103-140 ~j~ich de-codes the states of flip-flops 103-103, 103-104, and 103-105, .
In greater detail, the Yl, Y2, and Y3 flip-flop~ 103-130 throuyh 103-132 r respectively, are set in accordance with ~he 25~ folIowing boolean expressions. The do~ and plus siyn sy~bol.s .
represent a logical A~ID and;logical OR op~ration, re~pect$vely.

:
' . : ' .

. ~ . .
: -6G-.: ', ~ ' ,,,, ' . , .. : ' s~
Se~ ¢Yl-GI1100 = ~R~S~iT] [GHCM~ EN100] ( [ (Y0-PTH-ERR100~ ~ ;
+ (Yl ~ ~MS110 3 ] ~ C (Y7 ~ + (¢Yl R:E:AD7CI.R10 ) ] ) Set lzy2-GHlo~ - [RESET~ [GHCMP-E~R~EN100] ~ ( [ (~O~ERR GH~
~ ~ Y 1 ~ PTC:-TBL ) ~ ( iZY 2 ~ ~ RhAD/CLRl 0 ]
+ [ (Y3 ) ~ ~Y7 o SMS ) ~ (~ZYl ~ SMS j ~ ) Set ¢Y3-GH100 - [RESET] [GEICMP-ERR-ENlOa] ~ ( ~ (Yl) ~ (YO-ERR-G~) ~ ~ (Y7 ~ PTHTBL - SMS ) + (Y 5 - R:E:AD7-CI Rl O ~ ~ ) wherein~ : YO~
. ~1 = ¢Yl ,~
10 . - ~Y2 = 3~C ~ ¢Y2 j~
Y3 = ~ ¢Y~
~4 ~ Y3 Y5 = ~Yl ~ Y3 .
Y6 = ~ - ¢Y? ~3 .
- 15 . - Y7 = ¢Yl IZ~2 Ç~Y3 Other com~ination3 o~ the decoflcr 5igllal5 àre applied ~ :
to a further group o~ NAND gates 103-141, :lO3-14~/ and 103- `
143. These gates decode combinc~tions of s:iynals applied ..
thereto and yenerate the:control slgnals ~CNFIG10, ~ECNFIG~I10, and MISC~YL~CN~'GO10, which are applied to the input circuits o confisrura~ion regi t~r 103-15, shown in ~iyùre 3f. ~ .
- : ~

- - , , :. . ~ . :
.

' ' ' :' -. ,' ~ ' ' ' .

-61 - :
.

,, , , , ,,, . . .. ... ~..... . ~ , --~ pair o ~lip-flops 103-150 and 103-151, when switched to binary ONES via signals SET31J100 and GHCMPER~EN10, pro-vide indications of ~he processor configuration to panel in-dicator circuits as a tes~ing aid. A pair of OR ga~es 103-154 and 103-155, in response ~o ~he GU~pUt signals ro~ de-coder 103-140, genera~e a ~ype S or type 6 intexrllpt signal which is applied to the internal interrupt circuits of block 103-28. Tlle interrupt signal.s are generated in accordance with khe following boolean expre~sions:
INT-TYPE 5 = ~2 + Y6 INT~TYPE 6 = ~11 ~ Y1 ~ furthex group of NAND and AND ya~e circuits 103-160 through 103~162, a JK flip-flop circuit 103~1645 a~d a gate 103-165 provide a reinitialize interrupt siynal to the cir-cuits 103-28 ef Figure 3c. This si~nal is ~enerated in ac-cordance with the followin~ boolean expression:
REINITIALIZE IN~ERRUPT ~REXNIT-IN~ GEIlOG) - (PTH-TBL-Y7) (Y. 3 ) + (SMS - ~!Y1~
When enabled b~ the signals shown, the circuits sw.itch flip-2Q flop 103-165 to a binary ONE which~ in tllrn, causes gate 103-1~5 to ~enera~.e signal ~EINTINTGH10, Thi~ sign~l r ini~ializes the interrupt circults. A last pair of ga~es 103-166 and 103 167, in response to ~ignals from fault status register ~2 switch processor numbex signals FORC~PN10 and ALTPN10 to the appropriate states~ These .signals are also applie~ as inpute to the interrupt circuits 103-;~8.
.
, , :
- ; :; ' .

.:
-.

Figure 3e ~hows in greater d~tail th~ co~p~re logic /o 3 ~c~
circuits ~ of Figure 3c. The~e circuits include a p1ura1ity of AND gates of hlock 103~200 which compare the s~ates of ~he signals applied to the different in~er:Eace lines of both processors of pair 200~0. When a mis-compa.re (non~comparison~ is ~etectea, the circuits ~orce a corre~-ponding one Of the mis-compare error signals to a binary ONE. Signal GHCMPERR10 signals a mis-compare of the GH
pr~essor pair while signal DATACMPER~10 signals a mis~
compare on the DTS lines o~ the data interface. The re~
maining si~nals STRCMPERR10, POCMPgE~ROR10, and OPIMSC~ROlC, respecti~ely, indicate the occurrence of a m.is-compare on the ~teering lines, interrupt .interface 1ines, and OPI~1inesO
These signa1s are applied t.o ~he input circuit.s of faul-t ~tatus register #2.
A pluraiity of NAND~AND gates 103-201 thrGugh 103-20 .
compare the~states of the TBI, and PED interface lines~from th~ G and ~I processors. They condltion ~ND gates 103-21.0 and 103-211 to force sicJna].s G~TBLCl~00 and G~lPEDCMP00 to binar~ ONES u~on th~ indicatio.n of l'troubl.e" or a parlty error condition. These siqnals are app1ied`to the input cixcuits of ault status reyister ~2.
- The AND gates 103-214 through 103-21~ force an enab1e signal POENAB10 to a binary O~IE whel. both G and ~ processors are acti~e and connected to operate 1Ocked or compar~ mode , , ' , ` , ~ '. ' ,..

.

~ 63-.
..

(i. e., sigr~al POCMP10 = 1) . A~; eYplained herein, ~he states of the confi~ur~tion regis~er 103~15 are used to df~fine ~his type of operat~on.
It will alqo be noted that signals repre~en~al:i~7e of the ~tates of the pro~essor TBL line~ are applled ~71a gates 103-217 and 103 ~18 to the sequencer control circu~ ts o~
block 103-102.
A last grc>up of circuits o~ block 103-lOC include error gathering ~ D/AND gates 103- 2?~ and 103-2~2 which the parity error signs.ls genera~ed by ~he check circuit:s of block 103-35 for both the data and interrupt i~terfaces of each pro-cessor. The output signal~ are applied ~o cL further group of ~ND gates lQ3-224 through 103 226 of a port encoder~.
The encoder fs:~rce8 output signals PPO100, ~PPllOO, PP2100, and PP3100 to the ppropriate states to lndica~e the port from which an ~rror ha~ ~been det:2cted. The signal~ PPO100 through PP3100 are applied to bit positions 12-15 of falllt - status register ~1. The eamplQments of th~ error slgnals are alsd applled to bit position~ 0-15 o:E another section of fault status reg~ster ~,'1.
~'igure 3f ~i~closes the inpu~ and outpu~ gates asso~ia~e~
wit:h fault status regi~ter ~2 and configura~ion register 103;~
15~ .A8 seen from the figure, th~ N~ND gate~ 103-30û through.
103-303 generate ~:Lgna1s which are applied ~o bi~ posi~iQn~
1, 4, and 5 of fau1t ~t~tus reg1st~r ~2. The A~ and OR ga~es.
103~305 through 103-310 in response to a P~ command or de on-flguration s$gna1 force load s.Lgnal~ l.DINPl' (~:) ïO and LDINPT (~l~ 10 to binary ONES or setting o~ bit positions 33 and 34 of cQn-figur~tion regi~t~r 1û3-15. Th0 signal MISCMPLDCNFtJ010 i~
.

, ~ ,', ' . '.
- --6~
- . . . .
.
.- . . : , .
. i . . . .. .. . .. . . ... ... . ..

1~~
applied as ~ load enabling signal to register 103-15~
The output ~ignals :Erom coniguration regl~ter 103-15 are combined by A~JD ga~es 103-314 through 103-317, ampl~fier circuit 103-318, ga~es 103-319, and 103-32~ ~o generate com-pare mode sigrlals POC2IP10 ~nd PIC~?l~. The circui~s which gener~te the signals for compare proce~sor pair Pl are shown for co~pleteness. I~ wil~ be not~d that additiona]. control si~nals which define processor E and F are also u~ed since this pa~r may not be connected in ~he system.
A last group of circuits includcs amplifier ci.rcuit3 103-330 and 103-332 in additlon to NAMD gates 103-334 and 103-335. These cireuits force the STOP interace line~ ~o the appropr~ate states in response ~o output 8ignal~ f.rom bit positions 31-34 of conf~guration reglst~r ~03~15.

~E ~ SPEED MULTIPLEXER 3 00 COMM~N SECTION
Figures 4a and 4b di6clo~e in greater det-ail ~.he c~mmon control ~ection 301 and a port~i.on of the channel adapter section 302. Referrlng fir6t to Figure 4a, it iB seen that the coTmnon control sec~ion i~cludes~a pair of r~gister~ 3~1-2 and 301~5 ~or storing the words of a PI command received via the PDFS line~ of th8 multiplexer program~able lnterface 601 through a ~wo poslti4n dat~ sel~ctor ~witch 301-1. Th~ fiwl~ch 301-1 enabI.es PI co~and . signal8 from an alternate pa~h (i.e~, ~F~ llne~) t~ be l~aded ~nto retistsrs 301-2 and 301-5. Hovever, in th-~ preferred embodiment, -- -- -- .

- ' :

~ ~65~
.
:

only the PDFS position will be usedO It is also seen that. a register 301-40 receives via driver circuits 301-3 memory data applied to the DFS lines of the multiplexer data i~ in~erace ` 600.
The command signals from both regi~ter3 301~2 c~d 301~5 ~re selectively applied vla a two position data selector .qwitch 301-6 of the four channel adapter ~e~ti~ns via drive.r circuits of block 301-8. Also, the command signals can be selectively applied to one position of an ei~ht position data se.lector switch 301-20 via a two poSition data selector switch 301-42.
The same switch 301-~2 also applies the data si~naIs from register 301-40 to each of the four channel adaptex sections via driver circuits of block 301-43~
A pair o~ parity check circuits 301-45 and 301-49 perform a check upon the conten~s of registers 301-2, 301-5 and 301-40 an~ apply siynals representative of the results to ~he clrcui~s of block 301-4 which provides status si~nal~ applied to C
switch 301-5~0. The~e circuits compri~se logic circu-:i~s, conventio~al in design, whlch combine signals from register 301-2 with signals from the channel;adapter sections to-generate control signa1s necessary for executin~ the commands received from processox 200.
Additionally, the signals from regi~ter 301-5 can also he loaded into a selected one of the plurality of regi~ters of blocks 301-10, 301-12 and 301 14 via drlver circuits of bl.ock~
301-8, 301-15 and 301-16. The block 3~1-10 comprises four 8 bit rè~isters, conventional ln deæign, which may take the form of registers disclosed in the aforemQntion~d Texas Instrwment pu~
cation (eOg~ TI 7481). Output 5ignals frorn each of these re~ister~
` ~can be selectiYely ~applied a~an input to c~n interrupt po~lt~on o~
. selector switch 301-20 together with the cor~esponding signal~
.
from a four position selector switch 301-30 and an ei~ht po~tion . ~ :

~ . ~ -66~

5~
selector switch 301-3~. The c~ntents of the ICB, lev~l and mask register~ o~ the channel adapter sections can be read durin~ the performance of testing and verification operations in response to PI commandsO
Additionally, the intexrupt c~ntrol block re~isters of block 301-10 are selectivel~ connected to a 14 bit int.errupt data (IDA) register 301-22 in response to signals generated by an interrupt level priority networ~ 301-24~ Groups of blt positions o eac~ of the 24 hit level registe:rs of block 301-12 are applied to correspon~ing positions of a different one Q:E the 8 posi~ion multiplexer selection swit~hes 301-26 throllgh 301~28.
It is also seen tha~ each o the level r gisters of b:Lock 301-12 connect to different position~ of the ~ur position ~].ector switch 301-30 and eight position selector ~witch 301-32. I~
is also seen that each of the 8 bit mask registers of ~lock 301-14 connect to different positions of the four eight selector switch 301-32 and to he interrupt enabi.e priority and type logic circuits of block 301-34~
As seen from Figure 4a, the circuit5 of bL~ck 301~34 recei.ve 2~ groups of interrupt xequest~signals from chann~l adapters in~
additi.on to groups of inkerrupt si.gnals generated by the controller adapt~rs attaGhed to ~he channel adapters~ More specifically, .:
each CA channel can ge~erate four diffexent types of interrupt requests. ~hey i~lclude a fault~interrupt caused by setting of 2S a parity error indicator hit w~thin a common status register~
not shown, which can be conGidered as part of block ~01-4,~a data control word [DCW) inte~rupk, a programmable interrupt, a~d an exception inte~rupt produced by th~ de~ection ~E an ill~gal command etc. The ~ault inte.rrupt i~ made co~mon to each c~annel so as to have one input to bLo~k .301--34 which i~ ~he ~me for all four channel~.
' .
. -67~

.
.. : , .. . . . . ... ~ .. .. . . . .

~'~3~ 3 Each controller adapter can also generate four different types af interrupt requests which aYe dependent upon the type of device connected to the adapter. In the case of a disk device, the types of interrupt reqùests include: a ~ault i~ite~rupt caused by detection of pari~y error~, a xotational position sensed interrupt, a data trans~er termination interrupt and an off-line interrupt cause~ by completion of an off-lirle operation such as a seek operation. The follr types of channel interrupt requests and the ~our types of C~ interxupt requests t,oget~er provide a group of eight types per CA channel designated as events EV0 through EV7. Each type of interrupt re~uest is assigned a three bit type number such that the four channel ~ypes of interrupt requests are numbered 0~3 corre~ponding to EVO-EV3 while the four controller`adapter type~ of interrupt requests are numbexed 4-7 corresponding to EV4-EV7. The events having the lowest codes have the highest priorit~ (e.g. 000 - hi~hest priority = EV0 = fault interrupt and 111 = lowes~ priori~y - . . :
type = EV7 = off-line interrupt). The priorit~ ~or the dif~erent -types of interrupt re~uests is fixed and i~ determined by the t~ye nùmberO For Eurther information reyarding the assignment of priority t~pss, reference may be made to the copellding appliration titled "Programma~le Xnterface Apparatu~" which . .
is asslgned to the as~ignee of the present in~entionO Each of the channels provide 7 interrupt requests inputs t~ block - 2S 301-34 together with the common fault input provided by block 301-4.

~` ' ' : ' : . ' ~' ' .
. , . ' .
.

.. : :
,, - , . ' ' .

The circuits wi-thin block 301 34 logically combine the signals from each of the m~sk reqi~ters of hloc~ 301-14 with the interrupt request signals from each channel and ad~pter and select the interrupt type having ~he hi~he~t priori~y ~or each channel. The three bit type code ~or ~ach channel is applled to a corresponding one of the muitiplexer selec~or circuits 301-25 through 3~1-28. The sets o~ t~pe codes genexated by block 301-34 are also applied as lnputs to cor~esponding one~
of the positions o~ a four posit.ion level/type selec~or switch 301-35.
Each of the multiplexe~ circuits 301-25 through 301-28 upon being enabled by the circuits of block 301-34 provIcle an appropriate three bit level code as an input to an intexrupt level priority netwo~k 301~à4. rl`he network 301~24 generates 15 . signals on a pair of lines which connect as control input~ eo - ~he ICB regist~rs of block 301-10, th~ ~witch 301-3'i and a four position interrupt multiport identifier IMID switch 301-36~ The signals generated ~y network 301-24 deslgnate the channel or port having the highest priori.ty~ In the case where more than one channe:L has the same priorIty level, the circui~s of netwoxk 301 24 select the channel assigned ~he lowest channel number (i.e. CA~=OOX~=highest prioxity, CA3=llXX=lowest priority)., In ~hose instances where ~he controller adapters employ subchannels or subpor~, a pair o lines from the CAI provide signals to the low order two bit positions, of switc:h 301-36. The high order 2 bit positions o the switch are permanently with the coxre~ponding cha~nel adapter-numbe~ (aOg. 00=CAO etc~0 The output of swi~tch 301-36 is applied to IMID regi~ter 301-23 a~ deplct~d in Figur~ 4~
The output s~qnals from ~he selec~ed IC13 regis~er of block 301-10, the level signals from the ~e~ected multiplexer circui~cs and the type sig~als from bloak 301-34 are~merged into t~e IDA
' ' : ,' ' ' .

,' ' ` ' ~ , ' ' ' ~ ' :.

register 301 22. Alsv, these si~nals ar~ applied ~o t~le p~ri~y generator circui~s of a block 31)1-37 which g~nerate~ a pair of odd parity bits fo~ the signals stored ln the register 301-22. A further flip-flop 301-21 which can be considered part of regi~ter 301-22 receives a ~ignal from ~he r,ircuits of block 301~34 to indicate ~he presence of an interrup~ request.
~ s seen from Figure 4a, da~a signals stored in bit register 301-40 are applied via the ~I reglster position of two position - data selector switch 301-42 to ~ two position channel write (CW) .
switch 3Ql-44. The first position of the switch 3~1~44 when selected loads one of the four groups of channel adapter poxt registers 301-46 ~elected in re~ponee to si~nals:genera~ed by ~`, priority select and cont~ol circuits of block 301-48. ~he circuits of block 301-48 which receive input signals from , registers 30i-2 and 301-68 and the c~annel adapters shown apply output signals to the line~ a~d output register 301-65.
- . . .
The registers o~ group 301-46 includ~ a 40 bit registQr for storing a list pointer word (LPW~ for ~he port associated therewith, a 40 bit D~ regi~ter for ~toring the addre~ of data~ to be read or stored and a ~0 bit register ~T for storing tally and contro~l information relating to a current data transfe.r operation. rlle same registers of tlle four channel ~dapter ~ections conne~t to different position~ of a four position~data selector ~witch ~.Ol~S0 -~
which receive contr~l signals ~om tha circuit~ of ~lock 3~1~48.
The output signals fro~ switch 301 50 are applied to a pair of adder networks 301-52 and 301~54 in addition t~ a pari~y checl~
circuit 301 5~ operati~Je to checX the c~ntent~ for error~. The . ` adder network 301-52 i~; operative to updat:e the c:onteilt~ of the ~ ¦
: règister selected via switch 301-50 while t:he~ adder ne work 301-54 applies ~3utput signals to a p~rity generator circuit 301 58 The signals f~om th circuits 301-52 and 301-5~ are returned to the selected regis~er vi.a the update n~twclrk po~itis~n of ~wit:c:h 3Dl-44 .
- - ' . , . :
.
-~ 7 0 - ~

35~i3 A~ also seen from Fig~lre 4a, the output signals of switc:h 301~50 are applied selectively ~o an 8 bit steering register 301-60 via a steering switch 301.~59 and to the DT switch 301-20.
. Each of the data selector switches 30:L-59 and 301-61 receives output signals from D~ switch 301-20 which in addition to the sources mentioned is connected to re~eivP data signals from the DF lines of eac~ of the channel adapter sectio.ns CAV-CA3. The output signals from DT switch 301-20 and 2~C switch 301 61 are applied to a parity generator and check circuit 3al-5~ and to the bank of registers of block 301-64. Additionally, switch 301-61 is connected to rece.ive ~one and command information derived from ohannel adapter service lines applied to block .
301-4 when the multiplexer 300 is being operated in a particular .
mode not pertinent to the pre~ent invention. The four registers of block 301-64 designated as ZACr PDTS,~D~ata 1~ and Data 2 , - respectively store memory commarld signals, PI data signals and channel adapter data signals. The output signals from these -~
.
: : registers are applied either to the -lines DTS of t~e multiplexexs . data interface 600 or the PDTS lines oE the mul-tiplexers inter-.
~face 601. When the Z~C regi~ter of block 301-64 lS loaded, this causes an AOPR flip-flop 301-65 to be 5witched to a binary ONE
which signals the SIU 100 that the-mul~iplexer 300 is requesting a path over which it can tran~fex a memor~ ~AC) com~and and data~
.
: The appropriate memory steering information applied via ~witch ~301-59 will have been stored in regi.ster 301-60 and a pari*y -~ check and generatox circuit 301~66 i~ operative to generate ~dd ~ parity for *he 8teerin~ informa~ion.
., .
:-- -, .- :
-~
':

-. ,' . ' : - ~ .
. . . . i ~ 71-. . !
.. ~ . ; ~ . - : j - - . . - . ,: , 1 CHANN~L ADAPTER SECTIONS
.
Figure 4b shows the regi~.ters and data selector switch which compriSe each of the channel adapter sections CA0 CA3.
Since each of the sections are identical, only section CA0 is shown. It is seen that the section receives output siynals ~rom data transfer switch 301-6 and ~I swi~ch 301 42q The sig~ls from DT switch 301- 6 are applled via driver circuits of bloc~;
302-2 to a two position data selector (~D) switch 30~4. Th~
output command signals from switch 302-4 can be loaded select:ively into either a mode regis~er 30~-5 or into a pl~lrality o~
control flip-flops 30~-3 in response to control si.gnals ~rom 301~
Output signals from ~he mode regi~ter 302-5 and he control flip-flops are applied as inputs to the l~ic circuits o block 302-7 which generate the required control signals for executlon of a command by the controI~I.er adapte~ co~nected to the sectionO
Also, the circuits of block 3~2-7 receive cont~ol signals from block 301-4 from the r~gistex group 301~46 a~sociated~with the chan-nel adapter and from the lines of the controller adapter inter~ace.
In the present embodiment, the controller ada~ter interfac~
includes the ollowing lines.

CONTROLhER Al)AP~ER LIMES
Uesignation Descri~tio~
~TA The d~ta to adapter line~ are 40 lines which extend ~rom the module 300 to the controller adapter used to transmit data including commands and addresses.
to the adapter.

~72--S~3 ADTA The acc~pt d~ta to adapter line extend~ f rom the module 300.to the adap~er and w11en set:
indicates that data is ~ai.lable on the D~A
lines and ~hat i t shou1d be accepted by the adapter.
ACTA : The accept control to adapter line extends from the module 300 to the adapter and when set indicates that a PI conmland or data is available on the ~TA lines and that it should be accepted o by the adapter.
CHBS~ Tlle~channel busy line extenas from the modul~
300 to the adapter and wh n 1n an indir~ct mode .
. indicates to the adapter that th~ multiplexer 300 is now in an Auto data.transÉer mode;
~ ~the c~annel remains busy until the termination:
. of the Auto data transfer operationO In a. :
~ ~ . direct mode, this line is set-when.a memory .
- . (ZAC) comman~ is received.from the adap.~er and remalns set until èither the requested-read ~ data i~ trans~erred~or status. 15 returned from ~, the memory module.
` CDR ......... Th~ channel data ready line extends from the . module 300 to the adapt~r and when set indicates that tha module 30b i~` ready to accept more .~ data or~,omma.rlds~rom ~he adayter.
- ` EDT The end data ~ransfer 1ine extends f~om the . module 300 to the adapter and ~s used during Auto `
data trans~er operations:in indirect mode to .
. indicate that the 1ast wc)rd:of data hag be~n 30~ trans~erre~ (Write) or that th~ last word of data ha~ heen~s:tored¦(Re~d).

~ 73~

,. .- :
!

5~

- DFA Tl~e data from adapter lines are ~0 line~ ~hich extend from the con~roll~r adapter to moduLe 300 used t~ t:.ransfer data includi.ng status mernory addrec;ses, commands, to mc,dule 300~
5 PI~FA The port identifier from adapter lines are two lines from the adapter to module 300 used in conjunction with the in~errupt l.ines t~
indicate whic:h subport on the con troller adapter caused the interrupt, ADFA l'he accept data from adapter line extends Erom the adapter to module 300 an~ when set ind.icates that data or memory Gommand is applied to ~he . ~ DFA lines and æhould be accepted.b~ module 300.
AD-BUSY . - The adapter PI husy line e~tends from the . adapter to module 300 and ~hen set indicates : that the adapter-has accepted a PI command and is not capable of accepting any more commallds.
ADR ~The adapter data ready line extends rom the . - adapter to~the mo~ule 300 a~d~whe.n set , indicates to the ch~nnel that the adapter is ready to accept more data, IFA The interrupt from adapter lines axe ~our lines which extend f rom the controIler adap~er to moauLe 3no and indicate ~he t~pe of interrupt . requests (i~e. genara~es EV4-EV7 signals applied . to block 301-34).
TFA - - ~ The terminat~ from adapter line extend.s from . . adapter to mcidule 300 and when 6et indlcate;
the :t~rmination of ~ data transfer operation .
~ to modul~ 300.

. .

~ 74~
. .

3~3 It will be appreciated that the con~roller a~apter inter~ace includes other lines required f~r performin~ other Eunctioning s`lch as initializing~ ena~ling, ett_.
Output signals from switch ~02-4 are applied ~o a further two position selector switch 30~-6 which also receives data signals applied to ~he line~ DFA by the controller adapter associated therewith. Durin~ a data transfer operation, the output signals ~rom the D~ posi~ion of switch 302~6 are loacled into differe~t one~ of the our 40 bit data registers 302-8 fox transfer to common section 301 via a four positictn ~witch 302-12 or to the controller adapter via a two position selector ~witch 302~10. Additionally, Olltput signals from WD switch 302-4 are tran~fe*red to the con~roller adapter via the WD
position of switch 302-lOo Dif~erent one~ of the xegis~ers 302-8 are selected for loading~and unloading b~ the address signals stored in read and write address registers of block 302-14 which `
are modified by signals generated by `the cir~uits of block 302-7~.
Also, these WA and RA registers supply signals indit~ative of ~he number of words stored which are used to determine the; sSatus of a transer op~ration.
During a data tran~fer operakion, ~he par~ty check and generation of circuits block 302-lg are operative t~ check the parit~ of the data signals xeceived from the controller adapter via switch 302-6 and generate appropriate parity as required~ It .
is also seen thàt switch 302~4 receives ~iynals from the first pair of channel write data regi~ters tW Reg.0/ W Reg 1) which store two word~ of information fos ~ransfar from H ~witch 301~4 to eith~r the registers 302-8 or directly ~o the controller adapter via the s~lector switch 302-10~

- :.
7~-.

DESCRIPTION OF OP~,RATION

With reerence to Figures 1 t~rough 14, the state dia-gram of Figure ].5, and the flow chart of Figure 16~ the opera-tion of the pre~erred embodimerlt of the present inven~ion will now be described.
As discussed above, the interface lines of both pairs o~f ~/O processors are duplicated. Th~y ~re connected in parallel to the comparison circui.~ of SIU 100, shown in Fi~ure 3c.
Since both processor pair~ 200~0 and ~00-1 operate in the same fashion, in accordance with the present invention, the operation of one pair (200-0 or P0)~ will be described herein.

During each clock in~erval, ~he compare logic circu.~s ~3~
103 100-compare the sets o~ signals applie~ as out~uts on.
each of the interface lines of processors ~ and ~O The co~
iguration registër 103-15 has bits 33-34~ both set to bLnary ONES since bo~h processors of pair P0 are ~normally operated in a .
"loaked" or in a compare mode ~or purpo~es of error detection .

It will be appreciated that bit positions 33-and 34.o~config-~ration rPgis~er 103-15 will ha~e been set via~a PI load re~

gister comman~ to SIU port L ha~ving the forma~ shc~m i~ Figure 7b. Thus, circuits of Figure 3.~ :force the s~ates c~f each o.~

the 5TOP line~ of interace 604 of each processor ~o a binary ZERO`enabling the clock circuits and cyc:ling~ of processors G
.
and ~ control section 201 of Figure 20 ~lso, signal POC~lP10 2S i5 forced t9 a binary O~, enabling the operation o ci~c~its 103-200 and 103-205 through 103-~08 in ~igure 3e.

Also, during~normal operation, the SIU parity ci.r~ults `
: :. 103-35 generate parity bit~ fox the signals applie~ to the inter-face lines o~ each input/ou~put pro~essor interfa~e (data and interr~pt interfaces). The generated parity check bit~ ux-nished by the processor and. the results are applies as inputs to.NAND/~ND gates 103-220 and 10~-222 of Fiyure 3e I:E a mi~-compare error is detected, signa]. POCMP~RR10 is forced to a binary ONE via OR gate 103-300, This switches bit position 1 of fa~lt ~ta~us re.gister #2 to a binary ONE. It is assumed, by way of example, that a mis-compare is detected on the DTS data lines of data in~exface 600. The ~ al mentioned is clocked immediately into the status register. This allows sufficient time for interrogat:ion by an IOP proces~or where the mis-compare condition i5 trans.ient.
The in~ormation concerning where the mis compare occurred is used by the test and d.iagnostic routines as~explained herein.
The inormation store~ a~ to what port had the mis-compar~ is pertinent to the opexation o~ ~he sequencer control circuits 103-102. This example is conc~rned with poxts G and H~ .
Referrin~ to Figure 16, i~ is seen tha~ the c:ircuits 103~102 check on whether there was an !~ror on th~ process~ which will also be storèd in fault status xegister ~l by the GiXCUit5 cf ~0 Figure 3e. Of concern are par.ity errors detected hy he SIU 100 or internally by the processor during the mis-compare. Any parîty errors detected are stored in fault status .register ~1 by the circuits of Figure 3e along with the designation of the ~3 port which was the source of the error (see Figure ~
From Figuxe 15, it i~ see~ tha~ when the SIU contxol logic circuits detect an error or there was a processor de~eete~ ~rror signalled via the PED lines, the sequencer flip~flops are set.to ei~her state 010 or state 110. That is, ~:he mis~compare forces enab1e sig~al G~CMPER Nl0 to a binary ONE and the Y~ ~lip-flop `
~ 77~
, - ,: .. .. .. . . .. . . ... . . .

103-104 iB ~witched to a binary ONE via ~ignal SET21GH10.
The signal SETllGlO i6 forc:ed to a binary ONE when the error detected is a~soci~ted w:tth proce~sor H. That is; a parity error detec~ed ir~ proce~sor H (REG73101) D Q) or an SIIJ
error detected on por~ E~ (HERRûO s5 O) furcPs signal PTHERR10 to a binary ONE when signal YOGH10 frvm decoder lû3-14û is a binary ONE indicating that th~ sequerlcer i~ ~n s~ate 000.
The SIU circu~ ~8 of Figtlre~ 3d and 3:~, a~ expl~lned he~e-~, deconfigure or logically di~conn~ct the processor of the pAir h~ving the error by Loading ~Lgnals corre~ponding ~o the ` desir~d processor con~'~:guration into bit positions 33 and 34 of con~igura~ion register 103-15. For example, if there was an error detec~ced a3æociated with processor G, the sequencer flip-$10p~ would be.forced to state 01~. Thi3 c~ause~s the clecoder lQ~-140 to switch signal DECN:FIGlQ to a blnary ZERO and sig;nal DECNFIH10 to a binary ONE. In greater deta~ 1, for arL lnput code of "010", the decoder 10~-140 forces only output signal Y2GH10 to a binary 0~. This results in ~ign~ls DECNFIG10 and DECMFH10 being forced to the states mentloned, .
However, where the error detected is a~soclated with pro- :
cessor EI, the sequencer flip-~lops are forced to ~tate "llO".
Thfs causes the decoder 103-140 to swikoh ~gnal D~CNF~lO ~o a binary ONE and signal ~ECMFH10 to a binary ZERO. That i3, .
or an input code of "011", decod~3r 103-140 forces only signal Y6GH10 to a binary O~E. The d~cod~r 103-140 also force~ ~ignal ~ISCMPLI)CNFGOl~ to.a blna~ ONE in bo~h case~ which load~ b~t positions 33 and 34 ln ac~ordance with ~he g~ates of ~ig~TIal~
LDIlilPT(G)10 and LJ:)INPT~)10. The~e ~ign~ls are ~enera~e~ b~ th~
input circuit~ of Flgure 3 in re~pon~e to ~he .~ignal3 DEC~FIGC!,10 - ' ' ' ~ - :, , - . . , `': '' . : . ' . ' " ' . -,:
~7a~
.. ,. . : ~ :' ''' 3~ 3 and DECNFI~10. I~ should also be noted th~c s~ates of blt.
po~itions 33 and 34 of confl~;uration regi~tex 1~3^15 also es-tablish the states of the proces80rs STOP llne~. Mor~ ~pec:i-fically, when proc~sor G ls configured and processor H 1 s 5 deconfigured, signals STOPGOO and STûPHOO ~re ~orced to binary ONE: and binary ZERO, re~pec~ivel.y. This ~;'COp5 ~he "clock" ~f the proce~or whlch i8 not receiving ~e interrupt xeque~t andr thus, "freezes" its state at the t ~me of the error .
In each instance, the dec:oder 1()3-140 cond-ltions OR gate 103-154 to ~Senerate an in~errupt type 5 to ~he lnte~nal lnter-. rupt ~ircuit~ I03-28. Thi3 ignals the proce~sor recel~lng ~
the interrupt reque~ hat a mls~compare wa~ detected and that .
an error wa~ detec~ed indic~t~ $ the bad processor. The 6ig-nal~ REGlOOlOO and RE&100010 rom conf~guration regis~cer 103-15 force sl~snals FORCEP~10 and ALTPN10, re pe~t~vely, to a bi-na~ E and binary ZERO. The state of these si~nals ~ignal the interrupt circuits which logical proces~or pair ~s ts~ re-- ceive the interrupt request. S~nce, in thi~ example, proce~sor G or ~1 ~uered ~he mi~-comp~re, all in~errupts are d~rectçd . . ..................................................... . .
20 . to that logi:cal pair (i. e., pair PO)-. The 6tate of signaI
. ALTPNlO specifies the processor pair to recelve ~he i.nterrup~.
When si~nal ALTPNl~ is a b~nary ONF., lt designate~ the pros:es-sor pair Pl (proces~or 1~ and F) . When slgnal ALTPN10 ~ s a blnary Z~:~O, it de~ignates the pai~ PO ~processos G and H~.
In greater detail, when elther proces~r pa:Lr PO ~r P~
i8 detected ~o have a mls-co~..pare. as lndicated~by bi~ po~it~n~
: Q and 1 of 6tatus reglster ~2, thi.s forees ~he ~lgn~ FORCEPN10 to a binary ONE. Thls slgnal~ a mi~-co~pare and i8 u~ed to have the appropriate PN des~gnati.-~n loaded ln~co the SIU lrlter~

.. . . .

~' ' : ' ' ' ' , .

.

. " ~, , . , , . . , , . . . ~ . . . .

/~
rupt request woxd of Figure ~. Normally, this designation : is specified by the opsrating system softwara during the loading of the processor pair and the SIU 100 cixcuits e~-sure that the interrupt logic ~ircui~s ~orward the re~uest to processor pair P0 (i~e., load a binary ZERO specified by the state of signal ALTPN10~.
Summarizing the above, it ls see~ that the:SIU circuits store lnforma~ion indicating the s~atus o~ the SIU ports u~on detecting.a ~is~compare. Based upon:the status, the SIV cir 10 cuits decon~igure a proces~or d~tected as having an error and issue a level 0 type 5 interrupt to the proces~or pair detect- -ed as having the mis-compare error~ At~that time, the SIU
circults have completed opexations and cont~ol is tran~erred over to the test and diagnostic routines specified via the le~el 0 type 5 interrupt procedure.
~ s seen from Figure lÇ, the "good" processox performs a s~lf test prior to testing by the test and diagnostic routines~
However, the "bad" processor does not have an~oppo.rtunlty ta:
: run a self test since its state has ~een "frozèn". During in~
ternal testing, the "good" processor~ should not set the line TBL since the - inte.rrupt was di:rect~d to the "good~ rocesso~
and the "bad" processor was decoll~igured. If ~he 'rBL :line . . should come high, ~his signal~ a "fat.ali' non-recoverable cor.,~
., . . ~ .
dition which would be reported to ~e operator ~n a con~en~
25 ~ tional manne~. It should be realized that: the possi~illty o~
such an error is highly improb~ble. As xp3.ai.ned here.in,.~he~
-"good" processor, upon reachin3 a~pol~t at. whj;ch s21f t0.st~ig . `` ` . i8 complete~ thereafter requcsts the interrupt. requ~st wQrd rom the SIU: 100 by forc1ng line~IDR to a binary ONE. ;~

Before discussin~ internal testi.ng or test and diagnos-tic routines, the situation where no error is detected will be considered. If a mi~~compare error occurs, such as on DTS
. lines, but nelther the S~U nor the processors has detected a parity error, then the sequerlcer fllp-flops are ~orced to sta~e 001, as mentioned. More specifically, in the absence of a parity error, signal ~RGH00 is a binary~,O~E ~hich, ~o-gether wi~h signal YOGH10, forces signal SET31GH10 to a binary ONE. The Yl and Y2 flip-flops 103-130 and 103-131 remain re-set because of the absence of detec~ing parity errors associ~
ated with proce~sors G and H~ :~
As seen from Figure 15, processor G and process~r ~ are to be configured and deconi~u.red, respecti~ely~ In greatex detail, the decoder 103-140:o Figure 3d, in response to the .
:15 code "001" forces only signal YlGH10 to a binary ON~ There-fore, signals DECNTIG10 and D~CQFI~10 are ~or~ed~ to a binary ONE and a binary ZERO, resp~cti~ely. At the same time, load ~configuration`register signal MIsc~æLDc~FGo~o is forced to a . binary ONE. This, in turn, loads ~onfiguratio~ registeY bit~
- 20 positions 33 and 34 with values 'l10". A1sor signa1 YLGHQ0 forces signal INTTYPE600:~c) a binary ZERO generating a t.ype 6 inter.rupt request to processor G. This si.gnals the detection of a mis-compare bit and that no error~was det:ected indicating which processor of th~ logi.cal pair ~g baa. Again, the stat:es o~ bit positions 33 and 34 of configuration reg1ster 103~15 switch the ST~PG00 and S~OPH00 lines to the appropriate states in`addition to forcing processor nu~ber signals ~O:~CEPN10 and ALTPN10 to a binary ONE and bi:nary æERO, resp~cti~ely. ~hat:

. . , : . -:

. .
, . . , , . . ~ .

5~3 - is, the STOPG00 line is forced to a binary ZERO and the STOP~OO line is ~orced to a binary ONE. This is efective to "~top" or freeze the state o~ proces~o~ ~ and to allow processor G to con~inue operation. A ~inary ZERO .is loaded into the PN bi~ positi.on of ~he interrupt request ~ord dl~
rected to ~he SIU internal .interrupt: logic cixcuits 103~280 When the interrupt request has priority, t.his info.rmation is forwarded to the interrupt. logic circui.ts 101~
~s seen ~rom Figure 14, the SIU 100 gives con~rol over to the level O routines. The operati.on of inputJoutput pxo- :
cessor 200 will now be discus~ed in great~r d~tail~ As men-tio~ed, there are two types o~ SIU detected processor error~l.
type S error with mis-compare and type ~ mis-~ompa.re withou~.
exror. These error interr~pts.cause interrupt control bloç~:s ~ICB's) S and 6 to be reerenced ~see Figure 14). The addres~
pointex IC i~ each block points to the entry.points ~f the diagnostic routines in local memoxy SOO.
C.onsiderin~ first ~he situation ~he~; the SIU 100 detect~
a mis-compare error, but no parity erro.rs assoclakPd wlth -either proce~sor of pair PO, the 5IU100 applies signals in-dicative of a type 6 interrupt to the internal interrupt ; logic circuits 103-28. A~suming t~ere is no higher priorit~
- interrupt request, the SIU 100 passes along.the request to thè logic clrcuit~ lOl. Since type 5 and 6 interrupts ~re ~5 hardwired to level O r the~pxiority level.o~ ~he SIU xequest . applied.to circuits 101 by port. L i~ ZERO~ In khe absence : o any level O request~ ~rom other h;gher priority source~
: : (ports), the SIU logic c~ rcuit~ 101 o Fiyure 3E~ orce th~
- LZP line o~ each intexrupt inieraae 601 t;o a binary ONE r ~, . . . . .
' . ~ ' , ',': ~ ' ` : ' .
~ '; . . ' - .

: . -3~ 3 signalling the presence of a zero level int2rrup~.
In order ~o ensure that the processor has acs::ep~ad the interrupt, the se.quencer control circuits 103-102 generate the REINITINTGH10 signal which i~: applied to the SIU inter 5 rupt circui~s 101. This lowers and raisPs ~he approp~iate llnes o~ the int~rrupt in~erface.
Referring ~o Figure 2, it i5 seen that the signal ap-plied to the LZP line conc1i~ion.s con~rol stvre 2Ql-10 to branch to a particular ~tar ting storage location D The sig- -nal applied to the LZP line overrides ~he :I;nterrupt: inhibit signals stored in process control reglster 204~22 ~i . e ., .in hibits interrupts ) ~ Also, the signal applied to the LZP
lln~ initiates the start of a t;ime out interval whlch is twice in duration o the operation not comp:let~ periodd ~ That, is, it conditions ~he circuits 201-36 to start the counter~o:E
~lock 201-34. The counter is thereafter i~cremente.d in :re-sponse to each system clock pulse.
Upon ~ranching t:o ~he starting locatian, ~he Erocessor control sectIon 2 01 is sequenced through m.icrolnstructions 2Q stored in control ~tore 201~10. The microinstructions con-dition proce~sor ~Q0 to pe.rfo~m a self check in whi.ch a ma-jority of the processor circuit.~ a.re ex~rc.ised wi~:h a view toward causing an in~ernal error.. For exa~ple, da~:a signals generated from certain microins~.ru~tions are l~adecl in~o ,~nd read from scratchpad memol^les 203-10 and 204~4, tr~msferred to the woxking registexs 204-12 through adder~shiter 2~4-~o .
q!he self check ~est aheclcs a sub~tant:i.al amour~t o the pr~ce~-sor' s circuits and, in particular, those circuits ~Jhich are difficult to c~heck by means of te9t and di~gnostic routines~

~ .
:
.
8 3 Thus, the amount of testing the diagnostic programs are required to perform is minimized.
Additionally, arithmetic and logical operations are performed and the result is tested for correctness. When cor-rect, sequencing through control store 201-10 continues to a point where the processor 200 makes a request for interrupt data by forcing line IDR to a binary ONE. That is, when se-quencing proceeds properly through control store 210-10, the processor 200 reads out microinstructions for responding to the interrupt request from the SIU 100.
When sequencing does not proceed properly, the pro-cessor 200 does not reach the previously mentioned point in the control store 210-10 sequence. This results in the counter of block 201-30 being incremented to an all ONES count signalling the occurrence of the time out. The time out, in turn, causes bit position 16 of the process control register 204-22 to be switched to a binary ONE. l`he AND circuits of block 201-38, in response to bit position 16's being set, in turn, forces the trouble line TBL to a binary ONE which signals the SIIJ
100 of the fault. It will be appreciated that the implemen-tation of the self check microinstruction sequence can be considered conventional in design for the purpDse of the pre-sent invention. It could, for example, take the form of cer-tain tests described in the copending patent application of Myrl Kenneth Bailey, Jr., et al., entitled "Diagnostic Test-ing Apparatus and Method", issued as United States Patent No. ~ ;
4,048,481. Also, an example of a self check microinstruc-tion sequence can be found in the copending patent application o~ Marion G. Porter et al., entitled ~Fail Soft ,,", ..

5~3 Memory", issued as United States Patent No. ~,010,450.
At this time, the SI~ sequencer 103-102 is in a state (see Figure 15) such that it will not switch state in re-sponse to the trouble line TBL. I-lowever, the trouble in-dication is stored in fault status register #1.
Assuming that processor 200 executes the self check microinstruction sequence without error, the processor 200 executes a microinstruction which forces the IDR line to a binary ONE. The SIU circuits 101-2 of Figure 3a in turn are operative to apply to processor pair PO via interrupt inter-faces 602 the interrupt request word data formatted as shown in Figure 12. The request worcl includes a level number of ZERO and a code of 110, signalling a mis-compare with no error detected. The steering information is coded to desig-nate SIU port L.
Upon receipt of the IDR signal, the SIU 100 loads the interrupt level into AII. register 101-6 and applies the in-terrupt data word signals having the format of Figure 13 to the DFS lines of each processor interface 600. At the ~0 same time, SIU forces the ARDA line to a binary ONE signal-ling the processor 200 that the interrupt word applied to the DFS lines. This sequence is illustrated in Figure 9.
As soon as the AIL lines are forced to ZEROS, the circuits ;
201-36 stop and initialize the counter of block 201-3~. -This signals that the processor 200 operated without trouble and, therefore, was able to assume a level 0 interrupt state.
Referring to Figure 2, the ARDA line signal causes the interrupt request word to be loaded into the data in register ',' . . . . .

~3 204-18.- ~t that time, the SIU 100 removes the dat,~ from the DFS lines~ Additionally, the proc~sor 200 is opexative upon receipt of the ARDA signal to reset the AOPR line to a binary ZERO. It will be appreeiated ~hat although processor H also receives information applied to the interrupt interface lines, its "stopped" state prevents it from ma~ing any response thera-to.
Next, processor G, under microprogram control, fetches the control block base (CB~ from scratchpad locat.ion zero during the time the interrupt word is loaded into the data in register 204-18. The zero level number signals applied via the ~IL lines as an input to swi.tch 203~14 and to`the .
process control register ~04-22 establi`sh that ~he procPss or routine is to be r~n at level Z~RO. The interrupt word contents are transferred via the DI position of B switch ~04 l through the adder/shifter 204-2 vicl the adder/shi~ter posi~
tion of switch 204-8 into worXing regist~r IC of register bank 204-12. Also, the scratchpad.address rPglster 203~l2 is forced to ZEROS to read out the CBB contents from scratchpad . ~03-10 into buffer 203-16. ~ :
` For a new interrupt, tha primary ~BB must be aligned shif~ing the CBB let ll ~it positionsO The CBB is applied to ~he A operand input of adder/shifter 204-2 v1a ~he S~B.
pOSitiOII o A swit~h 203-20. q'he re~ult is transferred via switch 204~B into working regi~ter R2.
. Under microprogram control, processor ~00 orms the ICB
address by ~irst`applying the lnterrupt da~a ~on~ents of the R1 working regieter via~th~ WR~ bus and the W~R position o the A switch 203-20:to adder/shifter 204-2 wher~ they aré

, shifted rlght by nine~bi~ posltions and loaded lnto worklng ,, . ~ ..
-~ 86~

- - - - . . . . ..

?L~ f~3 . register R2 whic~ stores Css #l. The shifting removes the ICB nu~aer from the interrupt data word. ~uring the same cycle, the cuntents of wor~ing register ~2 are then trans-erred via the WRP bus ~o ~ufer 203-16~ Next, the ICB
number contents from buffer :203-16 ar~ applied via ~ switch 203-20 to adder/shifter 204-2 and shifted left by four bit positions. The shifted result is then loaded into working register R2. The shifting opera*ion is effective to multipl~
the ICB number by 16. ~he adder~shifter 204-2 ls operakive to sum or combine the contents of the b~Efer 203-16 applled via the A switch 203-20 and the conten~s of wor~ing register R2 applied via ~ switch 204-l. The result which id~n~ s the addre~s of the ICB in local memory module 500 is loaded .
into working register R2~ . :
15- Referring ~o Fiyure 14~ it can be~ seen:tha~ the type 6 - defines the particular ICB routine which is to process the SIU mis compare interrupt. Therefore~ proc~ssor 200 executes -the inte:rrupt r~utine at the addres~ ~pecified in ICB ~. This :
routine performs an exhaustlve test o the proessor.
More specifically, under microproc3ram con~rol~ ~he-pro cessor 200 initiates a read double operation or.etching a double word of the ICB (i.e.,. PSR and IC~ from module S00 using the ICB address stored in working register R2. The ICB address, togethex wikh other inEormation i~ loaded into aata out register 204-l4 from the R2 register via the ABS
positlon o address ~witch 204~6 and ~he ~ bus ~ e., Z~C
command ~enerated having;the ormat of Figure 7c). Th~ dialog signal sequence between the SIU lO0 and local memor~ module 500 is i1lustr2t d in Fig~lre ll and is discussed laker herei1l.
' ' ` ' ~ .
, ~ B7~
,: ' '' . . , ' :'`

Additionally, steering register 204 16 is loaded via the R~W position of ste~ring switch 204-10 and proce~sor 20n forces its AOPR line to a binary ONE ~o si.gnal SIU 100 of a memory requ~st, ~lso, the I~B addre~s is incremen~ed by eiyht and returne~ to working register R2~ The pxocessor 200 then delays execution of further microins~ructions un-til the SIU 100 signals acceptance of the request (iOe., network lQ2-20 forces the AR~ l.ine ~o a blnary ONE).
Next, processor 200 loads the csntents o the PCR re-gister 204-22 into working r~g:ister R3. At this time, work-ing registers Rl, R2, and R3 s~ore ~he interrupt word, the ICB address plus eight, and ~C~ contents, re~F~eck1vely.~ Th~
PCR contents stored in the work:ing regi6ter R~ are checked to determine that there was a re~ponse from the SIU 100 on the ARA or ARDA line~ The pxocessor 200, under microprogram ~ontrol, is operative to ~enerate another double read request to memory module 500-fox fet~hing the ne~t.two words of the ICB.
During the checking o~ the PCR contents,.the ~SR and IC
.20 words rom ~emory module soo are tran~ferred ~o data in re~s-ter 204-18. The first word ti.e.. PSR) is tra~sferred via the DI position o B switch 204-1 and ad~er~shifter 204-2 to .
working register R3~ The second word (i~e~ IC) is loa~ed in to the IC working register~ .
The processor 2qo under mi~roprogram control, performs ~ i c~peration~ necessary to load the interrupt word s~eering in . ~o PSR regi~ter 204-20. Firsb, the PSR cont:ents of workillg re~ister R3 are shifted lef~ by eight bit posltions. This j : . . ' !.
' '. , ' ,, -a8~
, ," .' ,; .~ ,. ' . ,. ' . ~ , ~ ' 5~63 elimina~es the ste~ring :Eield included in the left most byte of ~he word si~nce i~ has no significanGe ~o the pro~
ces~ing of the interrupt. q~he result is then trans~erred to working regis~er R3. The in~errupt word contents of 5 working regi~ter Rl are transerxed to bu~fer ~03-16 via the WRP bu~. It will be noted that bits 28-35 include the steering informa~ion generated by the SIU 100 and multi-plexer 300 which i~ to be inserted into P5R register 204-20.
During a next cycle of opexation, the ~ontents o~ work-ing register R3 are appli~d via W~R bus and the W~ position.
o B switch 204-l to ~he B operand input o adder/shi~ter 204-2 while the contents of buffer 203-16 al~e applied via the SPB position of A SWitGh 2~3-20 to the:A operand input of adder/shifter 204-2. T~e A operand and. B operand are con.-catenated and aligned by the shiftex to fcrm the new PSRwhich is transferxed to working register ~ .
: The processor 200 delays executi.on o~ f~r~he~ microin-structions until rec~ip~ of ~he next two ~ords o~ the ~C~.
. Up~n receipt o the ARDA;signal ~rom the BIU 100, the pro-cessor 200 ~ransfers the new PSR contents of workin~ re~is-ter Rl into PSR register 204-20 via the W~R bus,. During sub~
sequenc cycles, the words from the ICB loaded into data in register 204-lO are transferred into the ~ppropriate scratch -pad register loca~ions (i.e.~, GRl4 and PTBR addresses). 'rhere- .
af~er, the processor 200 fetche3 lnstructions of the pro~ram .
speciied by interrupt pxocessing routine using th~ IC working regis~er content~. .
- A5 indicated ~n Figuxe 16l exceptton conditions axe no~ ~
~ test~d by the initial test xoutine Inot genexated intentionally).

' ` ' . . .
. , . . ~
.. . . . .

5k~B
The tests pex~ormed are simi.lar to those ~asic tes~s per- .
formed by the sel~ check rou~ine, but more ex~ensi~e as to ~he combinations of da~a patterns generated and instruction sequences executed. Thus, thi~ initial phase should test processor 200 without generatîng any exception conditions.
Any SIU detected failures signalled via ~he TB~ line during the execution o~ this test routine cause the SIU 100 to generate a level O type S interrupt to the other processor half of the logical pair, here, processor ~I.
The types of condi~ions which are detected~as pxocessor failure~ are a~ follows:
l. operation not c~mpleta (OMC), indicating , th~ occurxence o~ a ~ime out:while attempt-~
.
in~ execution o a processor lnstruction;
- and, ` :~ 2. any othex exception cc~nditlon~ .
The above ~ailures, as discussed previously, cause diferen~
onès of the bit positions o.the procesæ control register ., . 204-22 to be switched to binar~ ONES~ Since the processor .
20 has entexed level 0, an exception aond.ition detected by the processor causes error detection circuits o:block 20l-30 to force ~he trouble line TBI, to a binaxy ONE. r~his is in con-trast to the self check routine wherein e~cception c~ndi~ions wexe inhibited from forcing the trouble llne ~B~ to a blnar~
25 ONE. As indicated, it ls on:Ly when bit pos.itlon 16 of the : :
procesR control regis~er 204-2~ i5 forced to a binaxy ON~
upon the occurrence o~ a tim~ out and when the proGessoL 20() is not in level O that the e.rror detea~or 201-`8 orce~ the . tr~uble line TBL to a bin~y ONE.

` ` ` ' ' ' ` ~ :.

.
.~o_ , , ' ' .
' ~' ' ' ' ` ' ~. , ~ . .

.. .. . . . .. .

The SIU 100 detects the c~roup one cond:itions ~y the proessor switching the troubl~ line TBL t:o a binary ONE-Group two conditions are ~tected by the progra~. under execution by its réading of tho PCR regis~ex contents.
Lastly, group three conditio~ls are al50 detected by the SIU 100 as failures since these are alc.o trapped ~s ex-ceptions.
Referring to Figures ~dr 15, anci 16, i~ is seen tha~
the sequencer cont.rol circui~,s 103-102, in .response io trouble line signal PTGTB:L,12 be.in~ forced to a binary ONE, switch to state 01.1 which i.s a dummy st ate . At the next ~lock pulse, the sequencer circlllts l.03-102 switch tQ st.ate 010. This is the same stat:e a3 that entered i.n tn~ si~uaW
tion where a mis-compare wa~ detected and the SIU 100 de-tected a parity error assoc:iated with processor G. ~cc~rd-ingly, in the manner previouc,ly descri~ed, the SIU sequencer circuits 103-102 are operatitre to con~iguxe the ~ood proces-sox H and deconfigure proces~or G. ~1SG, the circuit:s force the INTTYPE500 si~naL to a bin,~ry ZEP~O siynalling the level 0 type 5 ir.~terrupt to th.e SIU 100~ Again, tOhe STOP~00 an~.
STOPIl00 are forced to a binary ZERO and bi.nar~ ON~, respec-tively. This enab:les processo:r G for opexation and ree~es the state of processor ~. Processor H, in. the same manner as processor G, starts eY~ecution of the s~lf check rou~ine.
When the initial test routine is executea b~ processor G without error, the level 0 rl~utine references WREX and RDEX instructions specifyins wri~ing informati.on into and reading information from th~ S:IU wrap regist~er 103-17~ The WRE~ and RDEX inst.ruc~.ions have the format. illust:Lated in Figure 6. Each instruction col1dition~ processor 200 to ...

generate under microinstruction control a PI command having the format of Figure 7a. For further information regarding the specific manner in which such commands are generated, reference may be made to the copending patent application of Garvin W. Patterson et al., entitled "Programmable Inter-face Apparatus and Method", issued as United States Patent No.
4,006,466.
Successful execution of the RDEX and WREX instructions verifies the processor's ability to initiate external opera-tions involving other modules of the system of Figure l.
Upon verifying that the processor can execute these instruc-tions properly, the test routine references a urther WREX
instruction which conditions processor 200 to generate a PI load control command. This command is formatted as shown in Figure 7b. This command has bit 19 set to a binary ONE
which signals SIU 100 to stép the sequencer control circuits 103-1~2.
Considering the above in greater de~ail, the PI command is generated by processor 200 and loaded into data out register 204-14. The command includes one level or type of steering information ~i.e., bits 5-8). However, the steering information bits in the case of the SIU 100 are ZEROS. Additionally, the processor 200, under microprogram control loads signals from register 201-15 and PSR register 20~-20 via the PI
position of steering switch 204-lO into bit positions 0-8 of steering register 14. These signals have the format of Figure 13 and provide another level or kind of steering information for use by the SIU 100 or transerring ~he PI command to the designated port (i.e., port L).
..

~, - 92 - ;:
. .

.

Follow~ng ~he load~ng of bo~h registe~s 20~-14 and , ~04-16, th`e processor 200 forces the AOPR lln~ to a binary O~E w~ch beginR t~e slgnal ~equeIIce for tran~fex of the PI
coD~nand to the SIU lC30. Al~o, the proce~aor 200 increme1nts the lnstructiorl countQr CIC~ and 8tores th~ resu~t -ln work-ing register R3. Then the processor 200 delays execution o~E
the ne~t microinstructior~ unttl lt rece~e~ a 5ig~1al vla ~e ARA line from the SIU 100 indlca~ing the accept~n~e of the~
r~que~t .
lo The slgnal ~eque~ce for command transfer i8 ShOW}l in ~igure 10a. The SIU 100 vlews the PI command as requiring a pa~r of SIU cycles, an address/command cycle follow~d by a data:cycle deslgnated A and D, respec~i~7ely9 in Figure l~a.
Assuming that the SIIJ lû0 i~ ready ~o accep~c the PI eom~Tld, :
the PIR line iB a binary ONE:. The SIU prlority rle~work 102-4 of Figure 3b is operative t~ apply the command word via selector switch 102-2 to the PDFS lines of the SIU 100 dur$n~
the f~rst cycle o~ operatlon, The processor ~00 waits hoLd-ing ~he information in the data out regis~er 204-14 untll the SIU 100 sw~tche~ the ARA li:ne to a blnary Y.ER9.
Upon detecting the change of s~a~P in the A~ lin~ 9 ~he proce~sor 2a~, under m~roinstruc~sn controL, completes the:
proce~sing of the WR~X in~truc~ion by transerring ~he da~a ::`
.
word format~ed as shown ~n Fig,ure 7a from ~uffer ~03-16 throllgh ~he ~dder/shifte~ ~04-2 vl a the adder/shi~ter po~itlon of switch 204-8 into the data out xeg~er 204~14. As seen fro Figure 10a, thi~ word is presen~ed to ~he SIU 100 durlng ~he ~irst clock pulse ater th~ ~prooe~or 2~0 d~tef~t~ the s~hange of state in the ARA line. The da~c~ word r~main~ on ~he DTS ~ ~
; , ' ~ ' ~ ., ~ .- , .

.. - . ~ , : 1 ,g3 . - ~

95~j3 lines until ~he occurrence of the ne~t clock pulse at which time the operation is completed.
Referring to Figure 3c, it is ~een that the command word and data word are loaded i~to the PI register 103~25 . and I03-24~ respectively, via the PDFS li~s. Since thi.s is a Ioad control command, the conten~s o~ the data regi~ter 103-24 are ignored. ~he circuits of block 103-2D decode the.
command bit signals and check its parity. Upo~ the next clock pulse, the circuits 103-20 force signal SMS10 to a binar~ ONE.
Re~erring to Figuxe 3d, it is seen that signal SMSl.0 switches Yl flip-flops 103-130 to a bin~ary ONE via NAND gat~s 103-112 and 103-111 by forcing signal SETllG~10 to-a bi~ary ONE. As seen from Figure 15~ ~his s~eps ~he seque.ncer cir-cuits 103-102 to state "101'l. When i.n this s~.a~e, a tr~uble - line indication from the processor:does not cause the se- .
quencer circuits 103-102 to setp to a state which could cau~ie : -the processor to be deconfiguxed. ~hat is, it inhibits t.he .
SIU 100 ~xom rèsp~nding to trouble line chanye3 in state.~ .:
As seen from Fi~xe 16 t the test routines now test pro~
cessor G for exception conditions to verify tha~ they are being set under the proper condi~ions. Such testing could : ~ ;
involved the writing and reading of information tQ and ~rom local memory 500. ~his in~olve~ the processor generatin~ :
: 25 memory (ZAC) commands which re~ults in th~ dialog signal se~
- quence between ~IU 100 and loca~ memory modul~ 500, illus~
trated in Figure 11~ . :
The proCessor 200 waLt~ u:n~ he S~ nekwork 10~-20 of Figure 3b accep~s th~ r~ques~ signalled ~y the ~OP~ lin~
.:
: . .. .

. .
.
. . . .
. '; , , . , . -,, .: ~ , .. ... . -içi3 ~
by line ~RA ~eing forced to a binary ONE. Assumlng that ~he SIU 100 has accpeted the request fxom the processor 200, it then forces the AZC line to a k,inary ONE whlch directs module 500 to initiate a data read~write cycle of operation. As in-dicated in Figure 11, coincide~t with sett.ing the A~C line,the xequestor I.D~ signals, the ZA~ command signal~ and double precision signal originating ~rom the;proce~sor 200 are applied to the RITM lines, the DTM li~2s and SI.TM lines, respectively, o~ interface 603 in response to signals from network-L02-20.
As mentioned previously~ the local memgry module 500 retalns the~requestor I.~. signals which~it return~ to the ', SIU lO0 as steering information with the' data readO Refer- 1, ring to Figure 11, it is seen tha.t the lodal memory module lS 500 responds by switching ~he ~IR line to~a bina~ry ZEROo This enables the SIU 100 to disable the requestor path. The locai.
memory module 500 Lnitiates the transf r of data to the 6IU :~
100 by forcing the RDTR line~to a blnary ONE:in a~dition to - ~ ' placing the requestor I~D. originatins fr~m the processor 2G0 ~ I
20 ~ and a double precision signal on the RIFM lines and ~h~ DPFM~
line, respectively, of interface 6030 . ', The SIU lO0 responds ~o the switchin~ of the RDTR line by ~orcing the RDAA line to a ~in~r;y ONE as shown in Figure 11. This signa1s the loca1 memory :module 500 that the pa,th 25 - ~o requestor module 200 i~open and to proceed with the da~
. transfer. The signal to the R~AA 1in also, causes the modu].e 500 to place a second data' woxd on inté.r~cLce ~'03 ~at t~e;,trail~
- - - . ing edge~ of the: clock pulsl3 :Eol10wlrlg the r~ce.ipt oE ~ S1:~
, , ~ nals` on the, RDA~ ~ 11ne a~ ~hown in -L~re 11. At~tle~omple~

tion o t.he operation~ a~ soon as the module 500 is ready to accept another ~ommand, it switches the ZIR ~ine to a binary ONE.
-- At the t~me of ~orcing the RD~ line, the SIU ]00 no~i-~ies the requesting module 200 t~lat a data word is being ap plied to its DFS lines by ~orcing the A~DA line t~ a binary ONE ~see Figure 9~.
During excep~ion testing, it will be appreciated ~hat a failure for the processor G to generate ~n except.ion conaition . is recorded by th diagno~ic-test routine~ Status indications as to the results of excepti~n testing are s~ored in the wrap~
a~ound register 103~17 via a PI load register command issued to the SIU port Lo ~lso, status indications as~to the proces-sor G tested is also -stored in wraparound register 103-17.
As seen from Figure 15, the software, upon exS3mining the .results of such testing, can also issue a PI read and clear command to the ~ault status register #lu Here, bit ~8 of: the PI command is set to a binary ONF. (see Figure 7a~.. The com-manfl decoder olrcuits 103-2~ generate the appropriate co~rol sig~als to clear the regis~er designatéd aE~:er its con~ents are read. ~he read and cl ar oommand is the resp~llse to re-sèt the:source of an interrupt in the system~ That is, the .
status stored in ei.ther fault ~;tatus register #l ox #2 due to :~
exception testing produce~ an interrupt. 8y having exception ~esting take place while the s~quencer is:in state 101, this isolates the ~equencer from xesponding to~changes in ~tate in ~ the trouble line TBL, as mentioned be~ore.
;- ~ As seen from ~'igure lÇ, :~ollowi.ng the exception testing, processor 20~ i5 op~e~rative to execute another WR~X in~;truction .: ~ , , , , j ~ :., '' ''` ' :

coded to specify a step ~is-co~pare sequen~e (SMS) load con~rol command to th.e SIU 100. As des~rlbed prPviously, th~s causes the command decode log~c ci~cu~ 103-20 to gen~ra~e signal SMS10. Th~s, irl turn, switches the ~equencer clrcuits 103~102 to sta~ 111. In greater de~ail, the sl.gnal 5~S10 conditions Nh~D gate3 103-120 and 103-123. to switch signal SET22GH10 to a binary ONE. Thls switches Y2 flip-flo 103-131 to a binary ONE.
The swi~ching of the sequencer circuits 103-102 by ~he second SM5 command causes the SIU iQ0 ~o deconfigure proces ~or G, con1gure processor ~l, and issue a l~vel 0, type 6 in~
terrup~ to proc~ssor H (see Figures 15 and 16). In grea~er ~etail, when the Yl, Y2, and Y3 flip-flops 103~130 throu~h 103-132 are ~11 ONES, ~.he decoder 103~^140 of Figure 3d~ ln ~ respon~e to a code o 111, orces ~ignal ~7GH10 to a b~nary - O ~ . Thl~ forces deco~flguration signals ~ECNFIGGl~ and DEC~FIGH10 to a bl~ary Z~RO and binary ONE, respecti~ely.
Also, signal Y7GH10 ~orces ~ignal INTTYPE600 to a binary ZRRO conditloni~g the SIU lnterrup~ eircuit:3 103-28 to genex-20 ate the lè~el O, t~pe 6`interrupt. The ch~nges in ~ta~es o~
the configuration register ~it po~i~ion~ 33 and. 3b~ foree the ~top ~igna~s 5TOPGOO and STOPHOO to the appropriate ~tate~
(i.e., 8top processor G ~nd ena~le processor H ~or operation).
Upon switching to 3tate 111, it wlll be noted tha~ ~hl~
cau~es the reinitializlng of the int`erruptO A~ ~entloned, once a level O lnterrupt i~ generatQd by ~he SIU in~errup~
. logic circuit8 101, the cireuit3 canno~ ge~erate or is8ue : another level O interrupt un~il the fir~ inte~ru~t i~ cl.eare.d~
~ - Tbe circuits o~ F~.gure 3d (iOe~, N~D ga~s lQ3-100, 103 162, '` '' ': ' `, ' ' ` `' ~
. .
. . :.
-; . ~
: . g7 . : ~ :

... .. . . . . . . . , , ~, , . . ~ .

and AND gate 103-161~ by forcinq the reinitialize signal REIMINTINTGHlo to a hinary ~NE~ cause the interrupt logic circuits l0l to force the hi~h level interrupt present (HLIP) to a binary ONE and apply the level 0 signal~ again to the ~IL lines~ The rPason, as indicated previously, is that the interrupt request signal~ only designa~e the par~
ticular logical processor pair (here, pair P0) and ~ot the paxticular processor. Therefore, when the trouble line i5 raised, it is not certain whetner processor G or ~I hàs en~
countered the problem. Therefore, each timp t.he seque~cer circuits sequence to state 111, the interrupt logic circuits 101 are initlalized.
As seen from Figure 16, processor ~ begir~s exe¢ution o~ its self check routine. The self check and initlal test routlne are performed in the manner previously descri.be~.
In the event of a failure as signallea by the state of the txouble line TBL during such testing, sigr..a:L ETHT81,00 forced to a binary ZERO~ Thls switches the sequencer cir-cuits from state "111" to "110".
In greater detail~ si~nal PT~T~L0~ cau.se~. NAN~ gate 103-126 to switch ~ignaL SET32&H10 to a binary ZERO, Since signal SET31GH10 is a binary ZERO at this time, the Y3 flip~
. flop lG3~132 of Figure 3a is reset to a binary ZERO.~ -As seen from Figure 15, this causes the 5IU circuit.s to configure processor G and deconfigure pxocessor ~I in a~-dition to genera~ing a level 0, typ~ 5 in~err-lpt. It will be noted from Figure 15 that this i~ analogouc; to what hap-- pens wi~h respect to processcr 200 connecLed ~-o port G ~hen -~ the sequencer circuits switch rom ~ta~e "001" to i'010"

- . -, . . .: : ' ' '' (i.e., state "1117l ~s "001").
According~, the SIU 100 generate~ the necessary con-trol signals in the manner previou~ly described. ~n grea~ex detail, upon bein~ switched to sta~e "110", ~he decoder cir-cu~ts 103 140 of Figure 3d force ~ignal Y6.G~lC to a binary ONE, Thiæ, in turn, forces the configuration slgnals DECNFIG~10 and DEC~FIGH10 to a bina7~ O~E and a binary ZERO, respectively. This causes bit po~itions 33 and 34 of con~igura~ion register 103-15 ~o switch to "10t'l enabling proceæsor G and di~abling prvces~or E~ ~ia the stop llnes STOPG00 and STOPH00, ~l~o, signal YG~H00 force~ level 0, type 6 interrupt signal INTTYPES00 to a binary ZERO.
If a trouble indica~ion from processor E is ~ot de~ected.
durlng the execution of both the int~rnal self che~k routin~ ~r initial diagnostic routine, the diagnostic routlne e~ecutes.
a WREX instructio~ w~ich direc~s an S~lS com~and to the SIU
port L. In the manner descri.bed previously ~he c:ommand de- ¦
code circui~s 103-20 force signal S~S10 ~o a bina~y ONE.
Thiæ causes the sequencer circl1its 103~-102 ~:o ~witch from state "111" to 9tate "100", as illus~rated in Fi~u.re 15-In grea~er detail, signal SMS~0, when ~orced to a bi-nary ZER0, switches ~ignal SET32GH10 to a binar~ ZER(). Since ~igna1 SET31GH10 1Q a binary ZE~O at thi~ ti.me, the Y3 flip f1OP 103-132 is reset to a binary ZER~. Xn a sim11ar fashlon, ~, signal S~S00 switches signal SET22~-H10 to a bin~ry 2ERO.
Since signal SET21GH10 is a binary ZERO a~ thls t~e, ~he Y2 flip-~lop 103-131 i~ reset ~ ~ blnary ZERO.
~hile the sequ~ncer c~rcuits 103-102 are in ~te "100", - . the test routlne te6t5 e~ceptivn oonditlons in the m~nner - - .
., ~ ,.

. . .
., . : ~;
, . ' ! ~
_99 _ ' ' ' , `'` '` ~ ' ,' ', '' ~ $'~ 3 previously descrl~ed ln connection wi~ processor G~ De-pending upon the results of such tes~lng, the te8t rou~ine can either lssue a read and clear co~mand $o s~atus regis ter ~2 clearing the m.is-compare error conditlon w~ich is s ollowed by another PI co~and whi~h reinitlalize~ bi~
positions 33 and 34 of cnnfiguxation register 103-15 again placing the processors G and H in th~ locked or compare mode (i.e., set bit posi~ions 33 and 34 to binary ONES~.
The above would be done, for example, where i~ was d~termined that processor H te~ted good. This s~gnals the case of an inte~m~ttent or transient erro~ condition. Each error is recorded on an error ~ile 2nd a threshold is estab-l~shed for intermittent ailuxes in ~erms o ~he number o rail`ures per unit of time. W~len the erro~ rate e~ceecls ~he threshold, the system ~otware generates a message to an operator console request~.n~ initiati.on of:a special d~ag-no9tic -routine.
It will also be no~ed that the origin~l leve]. 0~ type 6 lnt.errupt could hav~ resulted ~rom an SIU error~as oppose~
to a processor error. Therefore, th0 system software as an al~ernative can perform an int;~rmediate te~:~ of the mi.s-compar~ circuit~ within the SIIJ 100. At this point, the processor pair P0 has alr~ady been te~ed with the error detected having been lsolated spec~fically to a mls-compare error on one of the proce~or in~erace llnes.
~ n accomplishing such testing, the system programs/data are loaded from a~ auxiliary or backup source in a evnven-tional manner ollowi~g t:~e loading o~ the new pro~e~æor co.n-figuration into regls~er l03-15. The loacling is acc~plish~d . .

~ '' . ~ ' ' . ': , -, . . . ~, , . , . -100~
. . ,', ~ :

via PI command to reg~ster (oc~al 5) of SIU port L. Thl8 command enables the lo~ding of configuratlon register 103-15 and initialize regis~er 103-16. That i8, the com~and decod~r circuit~ 103-20 generate signals which load bit pos~tions 5-27 of regi~ter 103-16 and bit po~ition~ 20-35 o~ conflgura-tion register 103-15~ The contents of the initialize regis~ ¦
ter 103-I6 establish which port(s)~ ar2 to receive an in-itializ~ pul~e of a predetermined width (i.e., 1.4 mlcro-~econds~. This is ~enerated by the initlal~ze Corltrol cir-cults 103-18 (i.e., ~y ~ conv~ntional one ~ho~ circult '~
triggered by a binary ONE in ~it positions 0~27)~ ;
If, dur~ng exception t~7~tillg, a problem or e~ror were encou~tered, the diagnogti~ routine execu~es a WREX ~ns~ruc-tlon coded to specify an SMS command. As seen from Fig~ire ~6, this switches the sequencer circuits from state 'll00"
to state ~7110~. This change in state is analog4us to going from sts.te "001" to state 7~010~
Considerlng the a~ove in greater detail,~slgnal SMSl0 conditions NAND gate 103-~20 of Figu~e 3d to ~witch s~gnal SET22GH10 to a binary ONB. At this ~ime, ~ND gate 103~117 force~ s~gnal SET21GH10 to a binary ONE in turn settin~ Y2 flip-flop 103-131 to a binary ONE. The decoder 103-140 conditioned by flip-flops 103-130 through 103-132 to force slgnal Y6GH10 to a ~inary ONE. In the manner previously 2S da~crlbed, coniguration signals DECNFIGG10 and DECNFI&H10 cause processor G to be con~8tlred and proce8~Qr H to be de-- c~nfigur~d. Also, a level 0, type S interrupt 3.~ ls~uefl to processor G in respon~e to si~nal INT~PE500 belng or~d:t~
a b~nary ONE by signal Y6GH~0, .:
~, . ..

: . , , ' . :
- : .
~101-~

As seen from Figures 15 and l~, ~he secluencer cir cu~ts 103-la2 rema~n in state 110 un~ii the issuance of another read ~nd clear command, In the manner de~cribed~
proce~sor G b2gins executlon of th.e sel~-check routine which should be completPd withou~ error (a~sume s~gl~
errors). Thereafter, processor G answers the type S le~el O interrupt whereupon ~t transfers control to the routine designated by ICBS of Fi~ure 14.
As mentioned previously, the type 5 interrupt define~
~hat the identity o~ the proces~or producing the m~s-compare error i~ known. In the ~equencing just de~cribed, ~he good processor was detexmined by actual tes~i~g. Ho~ever, ~rom ~gure 15, it is seen that the sequencer ci.rcuitæ 103~102 also entsr state "llO" when t~e SIU~c~xcuits have de~ect:ed a parity error assoclated with processor H a~ the ~ime the mis-compare error was dete¢~ed. It will be appreciated ~a~
6tate "110" is equi~alent to st~te "010" ~ich the seque.nce~^
circuits 103-102 assume when the SIU circuits detected a parity error associatbd with processor G at-the time~o~ the detected miscompare error.. Also, the ~ta~,e "013" i3 en~ered from state "001" when "trouble" was detec~ed in proce~vr G~
Accordingly, the test rou~ine referenced by the level 0 ~ype 5 in~errupt ope~ates t~ examine the contentEi of the ault statu~ reglsters i&l and ~2 to determine whether the 2$ entry into the routine was cau~ed by entr~ frvm.~he leve:L 0 type 6 error routine. In th~ case whe;re :~he entr~ was ~rom th~ level 0 type 6 error routine, the ~y~tem i8 relo~d~d ~lld restarted in the marner pre~iou~ly de~crlbed. Th~ sequeneer circuit3 103-102 axe returned ~o an lnitial s~ate ~aoo~ vl~ a .

.

, . ~ . . .
.
- , ~ 1 0 2 ~
i, : . . -.

read~clear cor,mand.
- When the entry into level 0 type 5 rou~.ine is caused by the SIU 100 ha~ng de~ec~ed the bad processor, the SIU
100 causes the other or "good" pxocessor to perfor~n a self test test operation in the manner prev~ous~y described. This situation arises when the SIU :L00 deteats a parity er~or associatea with processor X or detects an error during testing of processor H af-ter processor G tested good in the case of state 110, or detects a parity error associated with processor G in the case of state 010.
As seen from Figure 16, the ievel 0 type 5 routine is operative to repor~ the sta~us of fault sta~us registers #l and #2 a~ well as the contents:of the process cont.rol.regis-ter 204-22 of Figuxe 2~ Thi.s indicatefi ~o the system;the identity of the "bad proces~or".
Also, the diagnostic routine issues a load register 5 command followed by a read and clear command to fault st:atus register ~2. 1'his places the processor pair hack into the loched or compare mode for furthèx testiny by the operat:ing system so~tware~
Thereafter, the operatiIIy system has the capability of determining whether to continue operation wit'l~ one processor~
That is, it will simply cause a re~tart of the ~ystem,loading the configuration register 103~1~ with the ~ppropriate value, Thereafter, the operatiny system is able to provide ~or pe~
.
`odic teSting of the single conEigured pro~e~sor thereby en~ :~
sur~ng sy8tem reliability~
From the foregoing, i.t is seen ~hat ~;h~ apparatus o~
the present in~ention is ablG t:o deter~ine reliably the `

~ 103 ~ ~

: , -95Ei~ ~

presence o~ a ailured processor of a logical processor pair.
~his is accomplished in a manner whi.ch ensure~ that a proc~ssor is established as being bad ~nly by means o:~ positive indica-tion through direct detection o an error or by test.ing o~ the S bad processor ollowing testing of a good proGessor.
It will be apprecia-~ed that many modifications may be made to the preferred embo~.iment of the present inv~ntion 5UC~
as changes tq ~he individual proCesgor pairS ~ to the sequence control circuit~ and to other units withcut departing fror.~ .
the teachings of the pIeSent invention . Ad~itionally ~ i~ wil:l ;
be. obvious to those skilled in the art that signals repre~;enta-tive. of other types o:f erro3~ condit:ions may also be signaled : to the SIU 100 and used for testi~ng purposes.~
. Wnile i.n accordance with the pro~isions and statutes thère has been illustrated and described the bes* forms of the invention known, certai~ changes may be m~de to the sys-. .
tem described without departing t:rom the spirit o~ the inverl-tion as set~forth in the appended claims an~, in some caseC;~
.
certain features of the in~entiorl may be used t~ advantage 2D with~ut a ~orresponding u~e of other fea~ure~.

What i8 claimed is ,:

, .
.' ' - ' ~ 04~
- . ~ , . .

Claims (41)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. An input/output system for controlling input/output operations involving a plurality of input/output devices, said system comprising: a plurality of modules, each having an inter-face port said plurality of modules including at least one memory module and a plurality of command modules each including means for generating output signals including commands said plurality of command modules including a plurality of input/
output processing units and a multiplexer module coupled to said plurality of input/output devices; and system interface means having a plurality of interface ports, each port being connected to a different one of said interface ports of said plurality of modules for communication of input and output signals by said system interface means between said modules, said system inter-face means further including: configuration register means coupled to the ports of said input/output processing units for storing bit pattern signals coded for designating different configurations of said plurality of input/output processing units to be enabled for operation, said register means initially storing signals representative of an initial locked configuration bit pattern designating at least a pair of said identical plurality of input/output processing units as enabled for operation in a locked mode wherein each processing unit of said locked pair processes the same input signals in an identical manner to generate identical output signals including command to said multiplexer module and memory module required for execution of said input/output operations; comparison circuit means individu-ally connected to the interface ports of each of said plurality of input/output processing units, said comparison circuit means for comparing sets of said output signals from pairs of said interface ports of said input/output processing units paired for normal operation in said locked mode, said comparison circuit means being operative to generate signals indicative of a mis-comparison between any one of said sets of output signals; and sequence control means connected to said comparison circuit means and to said register means, said sequence control means being operative in response to said signals indicative of said mis-comparison to switch said register means from said locked mode configuration bit pattern to an unlocked mode configuration bit pattern wherein only one input/output processing unit of said pair is enabled for operation to permit first testing for reli-ably establishing which process unit of said pair is faulty.
2. The system of claim 1 wherein each port of each input/
output processing unit includes an error notification interface for signalling internal errors detected by said input/output processing unit associated therewith and wherein said system interface means further includes error register means operatively coupled to said error notification interface of each processing unit for storing first signal indications of said internal errors, said sequence control means being connected to said error register means, said first signal indications from said register means, conditioning said sequence control means to switch from an initial state to a predetermined state for conditioning said configuration register means to switch to a predetermined unlocked bit configuration pattern for disabling the operation of an input/output processing unit of said pair with internal errors and for enabling the other potentially good input/output pro-cessing unit of said pair for diagnostic testing.
3. The system of claim 2 wherein said system interface means further includes check circuit means connected to said ports of each of said input/output processing units, said check circuit means being operative to generate check error signals for indicating the invalidity of each set of output signals received from each of said plurality of input/output processing units, said check circuit means being connected to said error register means for conditioning said error register means to store second indications of said check error signals, and said sequence control means being conditioned by said check error signals to switch from said initial state to said predetermined state for altering the pattern stored in said configuration register means to enable deconfiguration of said input/output processing unit of said pair with internal errors and con-figuration of said potentially good processing unit of said pair for diagnostic testing.
4. The system of claim 2 wherein each said error notifi-cation interface includes a plurality of control lines, a first one of each plurality of control lines for selectively stopping the enabling of said input/output processing unit associated therewith, and wherein said system interface configuration register means further includes a plurality of bit positions for storing signals corresponding to said different bit configuration patterns, each of said register bit positions being connected to a different first one of said control lines of each processing unit error notification interface.
5. The system of claim 4 wherein each input/output pro-cessing unit includes: a clocking unit for generating timing signals, said clocking unit being connected to said first con-trol line of said error notification interface; and a micro-program controlled unit connected to said clocking unit, said microprogram controlled unit storing sequences of microinstruct-ion words for generating control signals for directing the operation of said input/output processing unit, said first con-trol line when switched to a first predetermined state by the content of one bit position inhibiting the operation of said clocking unit to prevent further operation of said microprogram controlled unit and freeze the state of one of said input/output processing units at the time an error is detected by said system interface means.
6. The system of claim 2 wherein each input/output pro-cessing unit includes a number of circuits including: a clocking unit for generating timing signals for said input/output pro-cessing unit, said clocking unit being connected to said error notification interface; and a microprogram controlled unit connected to said clocking unit, said microprogram controlled unit storing sequences of microinstruction words for generating control signals for directing the operation of said input/output processing unit, one of said sequences being coded to include a self-test sequence of microinstructions for exercising a majority of said number of circuits; and, said system interface means further including: interrupt means connected to said sequence control means; and, status register means connected to said comparison circuit means for storing indications of said miscomparison, said status register means conditioning said interrupt means to direct an interrupt request via said port to the pair of input/output processing units designated by said status register means to have said miscomparison, said clocking unit of said good processing unit of said pair being enabled by said error notification interface causing said microprogram controlled unit in response to said interrupt request to reference said self-test sequence of microinstructions for verifying that said potentially good processing unit is operating properly.
7. The system of claim 6 wherein each input/output pro-cessing unit further includes: fault detection means connected to receive a signal indication of said interrupt request, said fault detection means being operative to detect when said potentially good input/output processing unit is unable to execute successfully said self-test sequence of microinstructions;
and means connecting said fault detection means to said error notification interface for signalling said system interface means of a fault condition in the absence of successful execution of said self-test sequence.
8. The system of claim 7 wherein said error notification interface includes a trouble indication line connected to said means, and wherein said fault detection means includes internal timer means for generating a time out signal at the end of a predetermined time interval, said timer means being connected to said clocking unit for advancing through said time interval, said signal indication of said interrupt request conditioning said timer means to start said time interval, and said means being conditioned by said time out signal to force said trouble indication line to a predetermined state indicating said fault to said system interface means.
9. The system of claim 8 wherein said interrupt request is coded to specify one of a plurality of types for designating which one of a plurality of test and diagnostic routines is to be executed by said potentially good input/output processing unit during the further testing thereof.
10. The system of claim 9 wherein said memory module inclu-ding a plurality of storage locations for storing a number of different interrupt control blocks coded to identify a pre-determined one of said test and diagnostic routines; and wherein each input/output processing unit further includes interrupt control means coupled to receive said interrupt request, said interrupt control means of said good input/output processing unit following successful execution of said self-test sequence being operative to process said interrupt request from said system interface means and reference the particular one of said interrupt control blocks from said memory module specified by the type of interrupt request.
11. The system of claim 10 wherein each input/output processing unit further includes: error detection means connected to said trouble indication line, said error detection means for signalling errors detected during the execution of different ones of said test and diagnostic routine; and, said interrupt control means being conditioned by the referenced one of said interrupt control blocks to reference a first one of said test and diagnostic routines specified by the coding of said referenced interrupt control blocks said potentially good input/output processing unit being conditioned by said first one of said test and diagnostic routines to test more extensively the circuits tested during said self-test sequence, said error detection means being operative upon detecting an error during the execu-tion of said first one of said test and diagnostic routines to force said trouble indication line to said predetermined state for signaling said system interface means of trouble in said potentially good input/output processing unit.
12. The system of claim 11 wherein said first one of said test and diagnostic routines including at least one predetermined type of instruction for generating a predetermined type of command to said system interface means; said system interface means further including command decoder means operatively connected to said port of each of said plurality of input/output processing units,said command decoder means being conditioned by said predetermined state to said initial state for condition-ing said configuration register means to switch to said configura-tion to a locked hit pattern enabling said pair to continue diagnostic tests in said locked mode.
13. The system of claim 1 wherein said system interface means further includes: timing unit for generating clock signals defining successive cycles of operation to synchronize the operation of said system; and said comparison circuit means being connected to receive said clock signals fpr comparing said sets of said output signals from said pairs of said interface ports during each of said successive cycles of operation.
14. The system of claim 13 wherein said system interface means further includes: indicator means connected to said con-figuration register means, said indicator means being conditioned by said configuration register means to forward to a display utilization device signals indicative of said different configura-tions assumed by said plurality of input/output processing units during the operation thereof.
15. The system of claim 13 wherein said system interface means further includes: command decoder means operatively connected to said port of each of said input/output processing units, said command decoder means being conditioned by a command from any one of said input/output processing units to generate signals for switching said sequence control means to said initial state for operation in said locked configuration mode.
16. The system of claim 1 wherein each port of each input/
output processing unit includes an error notification interface for signaling internal errors detected by each said input/output processing unit, and wherein said system interface means includes check circuit means connected to each said port of each input/
output processing unit, said check circuit means for detecting check errors indicating the invalidity of said output signals received from each said input/output processing unit, and status register means connected to said error notification interface and said check circuit means, said status register means for storing indications of said internal errors and said check errors for indicating potentially good and bad processing units, said sequence control means including a plurality of bistable storage devices connected to said status register means, said bistable storage devices being conditioned by said indications from said status register means in response to a miscompare signal to switch from an initial state to a first one of a number of states in a first sequence of predetermined states when said indications designate that one of said processing units of said pair was detected to have an error, and said plurality of said bistable storage devices being conditioned to switch from said initial state to a first one of a number of states of a second sequence of predetermined states when said indications designate that none of said processing units of said pair was detected to have an error, said register means being conditioned by said plurality of said bistable storage devices to switch from said initial locked configuration bit pattern to an unlocked configura-tion bit pattern to enable selectively said good and bad pro-cessing units of said pair for testing in a predetermined manner established by said first and second sequences of states for reliably establishing which processing units are bad.
17. The system of claim 16 wherein said plurality of said bistable storage devices when in a first state of said first sequence of predetermined states conditions said configuration register means to switch from said locked configuration bit pattern coded for enabling and disabling the potentially good and bad processing units respectively, and wherein said plurality of said bistable storage devices when in a first state of said second sequence of predetermined states conditions said register means to switch from said locked mode configuration bit pattern to said unlocked mode configuration bit pattern coded for enabling and disabling first and second ones of said processing units of said pair.
18. The system of claim 17 wherein said first one of said first sequence corresponds to a code of either "010" or "110"
and wherein said first one of said second sequence corresponds to a code of "110".
19. The system of claim 17 wherein each input/output pro-cessing unit includes a number of circuits including: a clock-ing unit for generating timing signals for sequencing said input/
output processing unit, said clocking unit being connected to said error notification interface; and, a microprogram controlled unit connected to said clocking unit, said microprogram controlled unit storing sequences of microinstruction words for generating control signals for directing the operation of said input/output processing unit, one of said sequences being coded to include a self-test sequence of microinstructions for exercising a majority of said number of circuits; and said system interface means fur-ther including: interrupt means connected to said sequence con-trol means; and comparison register means connected to said comparison circuit means for storing indications of said mic-comparisons, said comparison register means conditioning said interrupt means to direct via said ports an interrupt request to the pair of input/output processing units designated by said comparison register means to have produced said miscomparison, said clocking unit of said first one of said pair being enabled by said error notification interface causing said microprogram controlled unit in response to said interrupt request to refer-ence said self-test sequence of microinstruction for verifying that said first one of said processing units is operating proper-ly.
20. The system of claim 19 wherein each input/output pro-cessing unit further includes: fault detection means connected to receive a signal indication of said interrupt request from said system interface means, said fault detection means being operative to detect when said input/output processing unit is unable to execute successfully said self-test sequence of micro-instructions; and, means connecting said fault detection means to said error notification interface for signaling said system interface means of a fault condition in the absence of successful execution of said self-test sequence.
21. The system of claim 20 wherein said interrupt request is coded to specify one of a plurality of types for designating which one of a plurality of test and diagnostic routines is to be executed by one of said input/output processing units during the further testing thereof.
22. The system of claim 21 wherein said memory module includes a plurality of storage locations for storing a number of different interrupt control blocks coded to identify a pre-determined one of said test and diagnostic routines; and, wherein each input/output processing unit further includes interrupt control means coupled to receive said interrupt request, said interrupt control means following successful execution of said self-test sequence being operative to process said interrupt request from said system interface means and reference the particular one of said interrupt control blocks from said memory module specified by the type of interrupt request.
23. The system of claim 22 wherein each input/output pro-cessing unit further includes: error detection means connected to said trouble indication line, said error detection means for signaling errors detected during the execution of different ones of said test and diagnostic routine; and,said interrupt control means being conditioned by the referenced one of said interrupt control blocks to reference a first one of said test and diagno-stic routines specified by the coding of said referenced inter-rupt control blocks, said one of said input/output processing units being conditioned by said first one of said test and diagnostic routines to test more extensively the circuits tested during said self-test sequence, said error during the execute of said first one of said test and diagnostic routines to force said trouble indication line to said predetermined state for signaling said system interface means of trouble.
24. The system of claim 23 wherein said first one of said test and diagnostic routines including at least one predetermined type of instruction for generating a predetermined type of instruction for generating a predetermined type of command to said system interface means; said system interface means further including command decoder means operatively connected to said port of each of said plurality of input/output processing units, said command decoder means being conditioned by said predetermined type of command to switch said bistable storage devices from said first state of said second sequence to a second state of said second sequence for inhibiting further switching of said bistable storage devices in response to signals from said error notifica-tion interface and, each input/output processing unit further including: process control register means for storing exception conditions, said process control register means being connected to said error detection means, said error detection means of said one of said processing units being operative to condition said process control register means to store signals indicative of exception conditions during the execution of said test and diagnostic routine following the switching of said bistable storage devices to said second state.
25. The system of claim 24 wherein said first state and said second state correspond to codes of 001 and 101 respectively.
26. The system of claim 24 wherein said test and diagnostic routines include instructions for generating memory commands for reading and writing information from and to said memory module.
27. The system of claim 24 wherein said test and diagnostic routines include another one of said predetermined type of instruction for generating said predetermined type of command, said command decoder means being conditioned by said predeter-mined type of command to switch said bistable storage devices from said second state to a third state of said second sequence, said bistable storage devices conditioning said configuration register means to switch from said unlocked mode configuration bit pattern coded for enabling and disabling said first and second ones of said processing units to another unlocked mode configura-tion bit pattern coded for disabling and enabling said first and second ones of said processing units for testing both of said processing units of said pair in accordance with a sequence similar to said second sequence of predetermined states to establish reliably which one of said processing units is faulty.
28. The system of claim 27 wherein said third state corres-ponds to a code of "111".
29. The system of claim 27 wherein said interrupt means of said system interface means further includes initialization circuit means operatively connected to each of said ports, said bistable storage devices when in said third state conditioning said interrupt means to direct and interrupt request of said one of said plurality of types via said port to said pair having said miscompare and to condition said initialization circuit means to signal said pair of said interrupt requests.
30. The system of claim 29 wherein said fault detection means of said second one of said processing units of said pair is operative to detect when said second processing unit is unable to execute successfully said self-test sequence of microinstructions; and, said means connecting said fault detection means conditioning said error notification interface for signaling said system interface means of a fault condition upon unsuccessful execution of said self-test sequence.
31. The system of claim 30 wherein said bistable storage devices are conditioned by said error notification interface means to switch from said third state to a fourth state in said second sequence, said bistable storage devices conditioning said configuration register means to switch from said another unlocked mode configuration bit pattern to said unlocked mode configuration bit pattern for enabling and disabling said first and second ones of said processing units.
32. The system of claim 31 wherein said fourth state corres-ponds to a code of "110".
33. An input/output system for controlling input/output operations involving a plurality of input/output devices, said system comprising: a plurality of modules, each having an inter-face port, said plurality of modules including at least one memory module and a plurality of command modules each, including means for generating output signals including commands, said plurality of command modules including a number of pairs of input/output processing units and a multiplexer module coupled to said plurality of input/output devices; and, system inter-face means having a plurality of interface ports, each being connected to a different one of said plurality of modules for communication of sets of input and output signals by said system interface means between said module, said system interface means further including: configuration register means coupled to the ports of each of said processing units for respectively storing bit patterns coded for signals designating different configura-tions for said number of pairs of input/output processing units enabled for operation, said configuration register means being set to a locked bit configuration pattern for enabling one of said pairs of input/output processing units for normal operation in a compare mode wherein each processing unit of said locked pair processes the same input signals in an identical manner to generate identical output signals including said commands to said multiplexer and memory modules required for execution of said input/output operations in response to identical instruc-tions; comparison circuit means individually connected to the interface ports of each of said plurality of input/output pro-cessing units, said comparison circuit means for comparing sets of said output signals from pairs of said interface ports of said input/output processing units, said comparison circuit means being operative to generate signals indicative of a miscomparison between any one of said sets of output signals; and, multistate sequence control means connected to said comparison circuit means and to said configuration register means, said sequence control means being operative in response to said signals indicative of said miscomparison to switch from an initial state to a first state in a predetermined sequence, said configuration register means being conditioned by said sequence control means to switch from said locked mode configuration to a first unlocked mode configuration wherein only one input/output processing unit of said one pair is enabled for operation in a non-compare mode to permit testing of said one processing unit of said pair for reliably establishing which processing unit of said pair is faulty.
34. The system of claim 33 wherein each port of each input/
output processing unit includes an error notification interface for signaling internal errors detected by said input/output processing unit associated therewith and wherein said system interface means further includes status register means operatively coupled to said error notification interface of each processing unit for storing first signal indications of said internal errors, said sequence control means being connected to said register conditioning said sequence control means to switch from said initial state to said first state for conditioning said configura-tion register means to switch to said first unlocked mode con-figuration bit pattern for disabling said input/output processing unit of said one pair with internal errors and for enabling the other potentially good input/output processing unit of said one pair for diagnostic testing.
35. The system of claim 34 wherein said system interface means further includes check circuit means connected to said ports of each of said input/output processing units, said check circuit means being operative to generate check error signals for indicating the invalidity of said output signals received from each of said plurality of input/output processing units, said check circuit means being connected to said status register means for conditioning said status register means to store second indications of said check error signals, and said sequence control means being conditioned by said check error signals to switch from said initial state to said first state enabling deconfiguration of said input/output processing unit of said one pair with internal errors and configuration of said potentially good processing unit of said one pair for diagnostic testing.
36. The system of claim 33 wherein each port of each input/
output processing unit includes an error notification interface for signaling internal errors detected by each said input/output processing unit, and wherein said system interface means includes check circuit means connected to each said port of each input/
output processing unit, said check circuit means for detecting check errors indicating the invalidity of said input and output signals applied to and received from each said input/output processing unit, and status register means connected to said error notification interface and said check circuit means, said status register for storing indications of said internal errors and said check errors for indicating potentially good and bad processing units of said number of pairs of input/output pro-cessing units; said sequence control means including a plurality of bistable storage devices connected to said status register means, said bistable storage devices being conditioned by said indications from said status register means in response to a miscompare signal to switch from an initial state to said first state in said predetermined sequence when said indications designate that one of said processing units of said pair was detected to have an error, and said plurality of said bistable storage devices being conditioned to switch from said initial state to a first state in another predetermined sequence when said indications designate that none of said processing units of said pair was detected to have an error, said configuration register means being conditioned by said plurality of said bistable storage devices to switch from said locked mode con-figuration bit pattern to said first unlocked mode configuration bit pattern to enable selectively said good and bad processing units of said pair for testing in a manner established by said predetermined sequence and said another predetermined sequence for reliably establishing whether any one processing unit of said one pair is bad.
37. The system of claim 36 wherein said plurality of said bistable storage devices when in a first state of said pre-determined sequence conditions said configuration register means to switch from said locked mode configuration bit pattern to said first unlocked made configuration bit pattern coded for enabling and disabling the potentially good and bad processing units respectively, and wherein said plurality of said bistable storage devices when in a first state of said another predeter-mined sequence conditions said configuration bit pattern to a second unlocked mode configuration bit pattern coded for enabling and disabling first and second ones of said processing units of said pair,
38. The system of claim 37 wherein said number of said pairs include processor pairs, P0 and P1, said pairs P0 and P1 including processing units G and H and E and F respectively, said locked mode configuration bit pattern corresponding to a code "11" for enabling either processing units E and F or G and H, said first unlocked mode configuration bit pattern corres-ponding to a code "10" for enabling only processing units E or G and said second unlocked mode configuration corresponding to a code "01" for enabling only processing units F or H.
39. An input/output system for controlling input/output operations involving a plurality of input/output devices, said system comprising: a plurality of modules, each having an inter-face port, said plurality of modules including at least one memory modules and a plurality of command modules each including means for generating output signals including commands through said port, said plurality of command modules including a plurality of input/output processing means for executing input/output operations involving said plurality of input/output devices and a multiplexer module coupled to said input/output devices, each of said processing means including first and second halves, each half including an input/output processor; and, system interface means having a plurality of interface ports, each being connected to a different one of said plurality of modules for communication of sets of input and output signals by said system interface means between said modules, said system interface means further including: configuration register means coupled to the ports of each of said processing means for storing bit patterns coded for designating different configurations for said plurality of processing means, said configuration register means being set to an initial locked configuration bit pattern for enabling at least one of said plurality of processing means for operation wherein each half of said locked processing means processes the same input signals in an identical manner to generate identical output signals including said commands to said memory and multi-plexer modules required for execution of said input/output operations; comparison circuit means individually connected to the interface ports of each of said halves of said input/output processing means, said comparison circuit means for comparing sets of said output signals from halves of said interface ports of said input/output processing means, said comparison circuit means being operative to generate signals indicative of a mis-comparison between any one of said sets of output signals; and, sequence control means connected to said comparison circuits means and to said configuration register means, said sequence control means being operative in response to said signals indicative of said miscomparison to switch said configuration register means from said locked mode configuration bit pattern to an unlocked mode configuration bit pattern wherein only one half of said processing means is enabled for operation for testing of said half of said processing means pair for reliably establishing which half of said processing means is faulty.
40. The system of claim 39 wherein each port of each half includes an error notification interface for signaling internal errors detected by each said half, and wherein said system inter-face means includes check circuit means connected to each said port of each half, said check circuit means for detecting check errors indicating the invalidity of said output signals received from each said half, and status register means connected to said error notification interface and said check circuit means, said status register means for storing indications of said internal errors and said check errors for indicating potentially good and bad processors; said sequence control means including a plurality of bistable storage devices connected to said status register means, said bistable storage devices being conditioned by said indications from said status register means in response to a mis-compare signal to switch from an initial state to a first one of a number of states in a first sequence of predetermined states when said indications designate that one of said halves of said processing means was detected to have an error, and said plural-ity of said bistable storage devices being conditioned to switch from said initial state to a first one of a number of states of a second sequence of predetermined states when said indications designate that neither half of said processing means was detected to have an error, said configuration register means being condi-tioned by said plurality of said bistable storage devices to switch from said initial configuration bit pattern to an unlocked mode configuration bit pattern to enable selectively said potentially good and bad halves of said processing means for testing in a predetermined manner and established by said first and second sequences of states for reliably establishing which input/output processors are actually bad.
41. The system of claim 40 wherein said plurality of said bistable storage devices when in a first state of said first sequence of predetermined states conditions said configuration register means to switch from said locked mode configuration bit pattern to said unlocked mode configuration bit pattern coded for enabling and disabling the potentially good and bad halves respectively, and wherein said plurality of said bistable storage devices when in a first state of said second sequence of pre-determined states conditions said configuration register means to switch from said locked mode configuration bit pattern to said unlocked mode configuration bit pattern coded for enabling and disabling first and second halves of said processing means.
CA289,452A 1976-11-15 1977-10-25 Input/output processing system utilizing locked processors Expired CA1109563A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US741,632 1976-11-15
US05/741,632 US4099234A (en) 1976-11-15 1976-11-15 Input/output processing system utilizing locked processors

Publications (1)

Publication Number Publication Date
CA1109563A true CA1109563A (en) 1981-09-22

Family

ID=24981524

Family Applications (1)

Application Number Title Priority Date Filing Date
CA289,452A Expired CA1109563A (en) 1976-11-15 1977-10-25 Input/output processing system utilizing locked processors

Country Status (9)

Country Link
US (1) US4099234A (en)
JP (1) JPS5391542A (en)
AU (1) AU510225B2 (en)
CA (1) CA1109563A (en)
DE (1) DE2750299A1 (en)
FR (1) FR2371017A1 (en)
GB (1) GB1595919A (en)
IT (1) IT1090438B (en)
NL (1) NL7712493A (en)

Families Citing this family (65)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4456952A (en) * 1977-03-17 1984-06-26 Honeywell Information Systems Inc. Data processing system having redundant control processors for fault detection
US4231087A (en) * 1978-10-18 1980-10-28 Bell Telephone Laboratories, Incorporated Microprocessor support system
US4205374A (en) * 1978-10-19 1980-05-27 International Business Machines Corporation Method and means for CPU recovery of non-logged data from a storage subsystem subject to selective resets
SE421151B (en) * 1979-01-02 1981-11-30 Ibm Svenska Ab COMMUNICATION CONTROL IN A DATA PROCESSING SYSTEM
US4428044A (en) 1979-09-20 1984-01-24 Bell Telephone Laboratories, Incorporated Peripheral unit controller
US4306288A (en) * 1980-01-28 1981-12-15 Nippon Electric Co., Ltd. Data processing system with a plurality of processors
US4342083A (en) * 1980-02-05 1982-07-27 The Bendix Corporation Communication system for a multiple-computer system
JPS6053339B2 (en) * 1980-10-09 1985-11-25 日本電気株式会社 Logical unit error recovery method
EP0088789B1 (en) * 1981-09-18 1987-08-05 CHRISTIAN ROVSING A/S af 1984 Multiprocessor computer system
US4866604A (en) * 1981-10-01 1989-09-12 Stratus Computer, Inc. Digital data processing apparatus with pipelined memory cycles
US4926315A (en) * 1981-10-01 1990-05-15 Stratus Computer, Inc. Digital data processor with fault tolerant peripheral bus communications
US4488228A (en) * 1982-12-03 1984-12-11 Motorola, Inc. Virtual memory data processor
DE3442418A1 (en) * 1984-11-20 1986-05-22 Siemens AG, 1000 Berlin und 8000 München METHOD FOR OPERATING A SIGNAL-SECURE MULTIPLE COMPUTER SYSTEM WITH MULTIPLE SIGNAL-NON-SECURE IN / OUTPUT ASSEMBLIES
US4885683A (en) * 1985-09-27 1989-12-05 Unisys Corporation Self-testing peripheral-controller system
US5155678A (en) * 1985-10-29 1992-10-13 International Business Machines Corporation Data availability in restartable data base system
US4788640A (en) * 1986-01-17 1988-11-29 Intel Corporation Priority logic system
IT1213344B (en) * 1986-09-17 1989-12-20 Honoywell Information Systems FAULT TOLERANCE CALCULATOR ARCHITECTURE.
EP0273081B1 (en) * 1986-12-30 1993-03-24 International Business Machines Corporation Improved duplicated circuit arrangement for fast transmission and repairability
US5020024A (en) * 1987-01-16 1991-05-28 Stratus Computer, Inc. Method and apparatus for detecting selected absence of digital logic synchronism
US4852083A (en) * 1987-06-22 1989-07-25 Texas Instruments Incorporated Digital crossbar switch
US5051887A (en) * 1987-08-25 1991-09-24 International Business Machines Corporation Maintaining duplex-paired storage devices during gap processing using of a dual copy function
US4970640A (en) * 1987-08-28 1990-11-13 International Business Machines Corporation Device initiated partial system quiescing
EP0306211A3 (en) * 1987-09-04 1990-09-26 Digital Equipment Corporation Synchronized twin computer system
US5185877A (en) * 1987-09-04 1993-02-09 Digital Equipment Corporation Protocol for transfer of DMA data
US4907228A (en) * 1987-09-04 1990-03-06 Digital Equipment Corporation Dual-rail processor with error checking at single rail interfaces
EP0306244B1 (en) * 1987-09-04 1995-06-21 Digital Equipment Corporation Fault tolerant computer system with fault isolation
DE3874518T2 (en) * 1988-01-22 1993-04-08 Ibm ERROR DETECTION AND MESSAGE MECHANISM THROUGH A SYNCHRONOUS BUS.
WO1989008883A1 (en) * 1988-03-14 1989-09-21 Unisys Corporation Record lock processor for multiprocessing data system
US4943966A (en) * 1988-04-08 1990-07-24 Wang Laboratories, Inc. Memory diagnostic apparatus and method
US5278973A (en) * 1989-03-27 1994-01-11 Unisys Corporation Dual operating system computer
US5189665A (en) * 1989-03-30 1993-02-23 Texas Instruments Incorporated Programmable configurable digital crossbar switch
US5144692A (en) * 1989-05-17 1992-09-01 International Business Machines Corporation System for controlling access by first system to portion of main memory dedicated exclusively to second system to facilitate input/output processing via first system
US5283868A (en) * 1989-05-17 1994-02-01 International Business Machines Corp. Providing additional system characteristics to a data processing system through operations of an application program, transparently to the operating system
US5155809A (en) * 1989-05-17 1992-10-13 International Business Machines Corp. Uncoupling a central processing unit from its associated hardware for interaction with data handling apparatus alien to the operating system controlling said unit and hardware
US5369749A (en) * 1989-05-17 1994-11-29 Ibm Corporation Method and apparatus for the direct transfer of information between application programs running on distinct processors without utilizing the services of one or both operating systems
US5369767A (en) * 1989-05-17 1994-11-29 International Business Machines Corp. Servicing interrupt requests in a data processing system without using the services of an operating system
US5325517A (en) * 1989-05-17 1994-06-28 International Business Machines Corporation Fault tolerant data processing system
US5113522A (en) * 1989-05-17 1992-05-12 International Business Machines Corporation Data processing system with system resource management for itself and for an associated alien processor
US5065312A (en) * 1989-08-01 1991-11-12 Digital Equipment Corporation Method of converting unique data to system data
US5153881A (en) * 1989-08-01 1992-10-06 Digital Equipment Corporation Method of handling errors in software
US5048022A (en) * 1989-08-01 1991-09-10 Digital Equipment Corporation Memory device with transfer of ECC signals on time division multiplexed bidirectional lines
US5068780A (en) * 1989-08-01 1991-11-26 Digital Equipment Corporation Method and apparatus for controlling initiation of bootstrap loading of an operating system in a computer system having first and second discrete computing zones
US5068851A (en) * 1989-08-01 1991-11-26 Digital Equipment Corporation Apparatus and method for documenting faults in computing modules
US5251227A (en) * 1989-08-01 1993-10-05 Digital Equipment Corporation Targeted resets in a data processor including a trace memory to store transactions
ATE139632T1 (en) * 1989-08-01 1996-07-15 Digital Equipment Corp SOFTWARE ERROR HANDLING PROCEDURES
US5163138A (en) * 1989-08-01 1992-11-10 Digital Equipment Corporation Protocol for read write transfers via switching logic by transmitting and retransmitting an address
AU650242B2 (en) * 1989-11-28 1994-06-16 International Business Machines Corporation Methods and apparatus for dynamically managing input/output (I/O) connectivity
US5428769A (en) * 1992-03-31 1995-06-27 The Dow Chemical Company Process control interface system having triply redundant remote field units
GB2268817B (en) * 1992-07-17 1996-05-01 Integrated Micro Products Ltd A fault-tolerant computer system
US5537607A (en) * 1993-04-28 1996-07-16 International Business Machines Corporation Field programmable general purpose interface adapter for connecting peripheral devices within a computer system
US5752063A (en) * 1993-12-08 1998-05-12 Packard Bell Nec Write inhibited registers
US5632013A (en) * 1995-06-07 1997-05-20 International Business Machines Corporation Memory and system for recovery/restoration of data using a memory controller
JPH09212371A (en) * 1996-02-07 1997-08-15 Nec Corp Register saving and restoring system
US6820213B1 (en) 2000-04-13 2004-11-16 Stratus Technologies Bermuda, Ltd. Fault-tolerant computer system with voter delay buffer
US6687851B1 (en) 2000-04-13 2004-02-03 Stratus Technologies Bermuda Ltd. Method and system for upgrading fault-tolerant systems
US6691225B1 (en) 2000-04-14 2004-02-10 Stratus Technologies Bermuda Ltd. Method and apparatus for deterministically booting a computer system having redundant components
US7065672B2 (en) 2001-03-28 2006-06-20 Stratus Technologies Bermuda Ltd. Apparatus and methods for fault-tolerant computing using a switching fabric
US6971043B2 (en) * 2001-04-11 2005-11-29 Stratus Technologies Bermuda Ltd Apparatus and method for accessing a mass storage device in a fault-tolerant server
US6928583B2 (en) * 2001-04-11 2005-08-09 Stratus Technologies Bermuda Ltd. Apparatus and method for two computing elements in a fault-tolerant server to execute instructions in lockstep
FR2862457B1 (en) * 2003-11-13 2006-02-24 Arteris SYSTEM AND METHOD FOR TRANSMITTING A SEQUENCE OF MESSAGES IN AN INTERCONNECTION NETWORK.
US10514990B2 (en) * 2017-11-27 2019-12-24 Intel Corporation Mission-critical computing architecture
US10946866B2 (en) 2018-03-31 2021-03-16 Intel Corporation Core tightly coupled lockstep for high functional safety
US11120642B2 (en) 2018-06-27 2021-09-14 Intel Corporation Functional safety critical audio system for autonomous and industrial applications
US11520297B2 (en) 2019-03-29 2022-12-06 Intel Corporation Enhancing diagnostic capabilities of computing systems by combining variable patrolling API and comparison mechanism of variables
CN112380119A (en) * 2020-11-12 2021-02-19 上海东软载波微电子有限公司 Chip, programming debugger, system and method for locking programming debugging entry

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3252149A (en) * 1963-03-28 1966-05-17 Digitronics Corp Data processing system
US3409877A (en) * 1964-11-27 1968-11-05 Bell Telephone Labor Inc Automatic maintenance arrangement for data processing systems
US3386082A (en) * 1965-06-02 1968-05-28 Ibm Configuration control in multiprocessors
DE1524239B2 (en) * 1965-11-16 1971-07-22 Telefonaktiebolaget Lm Ericsson, Stockholm CIRCUIT ARRANGEMENT FOR MAINTAINING ERROR-FREE OPERATION IN A COMPUTER SYSTEM WITH AT LEAST TWO COMPUTER DEVICES WORKING IN PARALLEL
SE313849B (en) * 1966-03-25 1969-08-25 Ericsson Telefon Ab L M
NL153059B (en) * 1967-01-23 1977-04-15 Bell Telephone Mfg AUTOMATIC TELECOMMUNICATION SWITCHING SYSTEM.
US3864670A (en) * 1970-09-30 1975-02-04 Yokogawa Electric Works Ltd Dual computer system with signal exchange system
BE789512A (en) * 1971-09-30 1973-03-29 Siemens Ag PROCESS AND INSTALLATION FOR HANDLING ERRORS IN A DATA PROCESSING SYSTEM COMPOSED OF SEPARATE UNITS
US3812468A (en) * 1972-05-12 1974-05-21 Burroughs Corp Multiprocessing system having means for dynamic redesignation of unit functions
US3828321A (en) * 1973-03-15 1974-08-06 Gte Automatic Electric Lab Inc System for reconfiguring central processor and instruction storage combinations
US3898621A (en) * 1973-04-06 1975-08-05 Gte Automatic Electric Lab Inc Data processor system diagnostic arrangement
US3921141A (en) * 1973-09-14 1975-11-18 Gte Automatic Electric Lab Inc Malfunction monitor control circuitry for central data processor of digital communication system
US3838261A (en) * 1973-09-14 1974-09-24 Gte Automatic Electric Lab Inc Interrupt control circuit for central processor of digital communication system
US3908099A (en) * 1974-09-27 1975-09-23 Gte Automatic Electric Lab Inc Fault detection system for a telephone exchange
US3958111A (en) * 1975-03-20 1976-05-18 Bell Telephone Laboratories, Incorporated Remote diagnostic apparatus

Also Published As

Publication number Publication date
AU510225B2 (en) 1980-06-12
US4099234A (en) 1978-07-04
JPS5391542A (en) 1978-08-11
FR2371017A1 (en) 1978-06-09
GB1595919A (en) 1981-08-19
FR2371017B1 (en) 1985-01-18
NL7712493A (en) 1978-05-17
DE2750299A1 (en) 1978-05-18
AU3025677A (en) 1979-05-10
JPS62538B2 (en) 1987-01-08
IT1090438B (en) 1985-06-26

Similar Documents

Publication Publication Date Title
CA1109563A (en) Input/output processing system utilizing locked processors
EP0167540B1 (en) Processing system tolerant of loss of access to secondary storage
CA1121481A (en) Multiprocessor system
EP0185704B1 (en) Reconfigurable dual processor system and method for operating it
US4371754A (en) Automatic fault recovery system for a multiple processor telecommunications switching control
US3787816A (en) Multiprocessing system having means for automatic resource management
CA1098217A (en) Memory access system
CA1119273A (en) Input/output data processing fault detection system
CA1099820A (en) Interval timer for use in an input/output system
CA1074456A (en) Multiplexer security system
US4045661A (en) Apparatus for detecting and processing errors
JPS61500043A (en) Control channel interface circuit
JPH07200191A (en) Disk array device
JPS6235704B2 (en)
US5455940A (en) Method for abnormal restart of a multiprocessor computer of a telecommunication switching system
CA1147474A (en) Memory system in a multiprocessor system
CA1176338A (en) Input/output system for a multiprocessor system
JPH09282291A (en) System and method for canceling lock flag of common storage device
KR100206472B1 (en) Error manage & recover method of switching system
CA1142619A (en) Multiprocessor system
Rodriguez Transaction network, telephones, and terminals: Transaction network operational programs
CA1136728A (en) Multiprocessor system
CA1137582A (en) Multiprocessor system
JPS6232815B2 (en)
JPH05265790A (en) Microprocessor device

Legal Events

Date Code Title Description
MKEX Expiry