CA1074455A - Plural virtual address space processing system - Google Patents

Plural virtual address space processing system

Info

Publication number
CA1074455A
CA1074455A CA279,994A CA279994A CA1074455A CA 1074455 A CA1074455 A CA 1074455A CA 279994 A CA279994 A CA 279994A CA 1074455 A CA1074455 A CA 1074455A
Authority
CA
Canada
Prior art keywords
address
virtual address
virtual
real
common area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA279,994A
Other languages
French (fr)
Inventor
Koichi Inoue
Hajime Nonogaki
Tatsuo Urakawa
Kazuyuki Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of CA1074455A publication Critical patent/CA1074455A/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10Address translation
    • G06F12/1027Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1036Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation

Abstract

ABSTRACT OF THE DISCLOSURE

In a data processing system having a plurality of virtual address spaces, a virtual address is translated into a real address for accessing a main memory and the translation result is stored in a translation look aside buffer, as in a processing system having a single virtual address space.
Thereafter, in the case of the same virtual address as the above, the trans-lation look aside buffer is retrieved to translate the virtual address into a real address. Generally, even in the case of the same virtual addresses, if their virtual address spaces are different, the virtual addresses are translated into different real addresses. However, a control program, a control table or a common subroutine is provided in a common area in which the coordination of virtual and real addresses is always constant even in the case of different virtual address spaces. To enhance the efficiency of utilization of the translation look aside buffer, common area indicating means is provided, by which the coordination of virtual and real addresses on the translation look aside buffer is registered so that it can be used in common to a plurality of virtual address spaces.

Description

7~

~ his invention relates to a plural virtual address space pro-cessing system, ana more particularly to a plural virtual address space processing system for a data processing system of the type coordinating vir-tual and real addresses with each other corresponding to plural virtual address spaces and storing the result of coordination in a translation look aside buffer (hereinafter referred to as the table TLB), in which a common virtual register is provided Por designating an area common to the virtual address spaces and when the result of coordination of the virtual and real addresses corresponding to the common area is stored in the abovesaid table TLB, it is registered in common to the virtual address spaces though they are different~ thereby to provide for enhanced efficiency of use of the table TLB.
Recent data processing systems usually adopt the so-called .~:
virtual memory system which has a tendency that a single virtual memory system having only one address space is switched over to a plural virtual memory system having a plurality of address spaces. In the plural virtual memory system~ only one Job is permitted to exist in one virtual address space and virtual address spaces are prepared which are equal in number to the jobs of simultaneous operation. Since only one jo~ is assigned to each of the address spaces and since the address spaces do not interfere wlth one another, this system has the advantage that the operation of one job is not affected by the operation of other ~obs. Further, this system has the merit that an increase in the number of address spaces is not sub-ject to restriction by the architecture of hardware. In this case, areas common to the ~obs, i.e. areas such as control programs~ control tables for use therein and other common subroutines, are functions necessary for the jobs, so that they are provided for each virtual address space. Such areas will hereinafter be referred to as the common areas.
Also in such a plural virtual memory system as described above, processing for the coordination of the address of the virtual address space ;
" ,, .

- 1 - ~ '~ ~ ' , :' ,' . . . , ' ' , :

with a real address on a main memory is performed for each virtual adaress space as is the case with a single virtual address. And the result of such coordination is stored in a high-speed memory or table called a translation look aside buffer (TLB). In processing the coordination of the virtual address with the real is achieved by retrieving the table TLB. But in the common area prepared for each virtual address space as mentioned above, coordination of the virtual address with the real is always constant even in the case of different virtual address spaces. As a result of this, if the results of different coordinations are stored in the table TLB for respective different virtual address spaces, the efficiency of utili~ation of the table TLB is lowered.
An object of this invention is to provide a plural virtual address space processing system in which if the virtual address to be converted into a real address is in the common area, the result of coordination of the virtual address with the real address on a main memory is registered on the table TLB in such a manner that it can be used in common to different virtual address spaces, thereby to enable an efficient utilization of the table TLB. ~--Another object of this invention is to provide a plural virtual address space processing system which has common area indicating means and ~ ~ ;
in which when the virtual address to be converted into a real address is applied, the contents of the two are immediately compared with each other and in the case of coincidence, a certain indication is provided in common to different virtual address spaces.
Another object of this invention is to provide a plural virtual address space processing system in which when the common area is changed, the content of the common area indicating means is also immediately changed correspondingly.
Still another ob~ect of -this invention is to provide a plural vir~
tual address space processine system in which the result of coordination of of virtual and real addresses corresponding to the common area is registered ~ -
- 2 -on the table TLB in common to differen-t virtual address spaces so as not to remove other coordination results from the table TLB, thereby to enhance the ~
efficiency of the entire system such as reduction of the capacity of a -memory forming the table TLB.
According to the plural virtual address space processing system of this invention, in a data processing constructed so that virtual and real addresses are coordinated with each other corresponding to plural virtual address spaces, that a predetermined area in each of the plural ~;
virtual address spaces has an area common to them and the virtual address ~ :
corresponding to the common area corresponds to a real address common to ~ :
the plural virtual address spaces and adapted such that the result of coordination of the virtual and real addresses is stored in the table TLB
and that processing is executed while retrieving the table TLB, there is proviaed common area designating memory means for designating the common area and when the result of coordination of the virtual and real addresses is registered in the table ~LB, the content of the common area designating memory means is referred to and the coordination result corresponding to :~
the common area is registered in common to the plural virtual addresses.
Thus, in accordance with the present invention, there is provided : 20 a plural virtual address space processing system for a data processing ~:
system which comprises a translation mechanism for translating a virtual address into a real addres: and a memory for storing the real address trans-lated by the translation mechanism and in which in data processing, if a `
desired real address is stored in the memory, the real address i8 used for data processing and if not stored, the desired real address is obtained with :
the translation mechanism~ said plural virtual address space processing system comprising: common area indicating means for indicating the range o~ a com~
mon area in which the same virtual address is translated into the same real address in each virtual address space; and a comparator circuit ~or detecting whether or not the virtual address to be translated into the real address :~
- 3 - .

: . ., . . : , .
.:

lies in the range indicated by the common area indicating means; wherein when the real address is stored in the memory, if the virtual address cor-responding to the real address indicated as an adaress of the common area, common area identify information is stored together with the real address, and wherein if the virtual address corresponding to the real address is indicated as an address of another area than the common area, virtual address space identify information is stored together with the real address.
The invention will now be further described in conjunction with the accompanying drawings, in which:
Figure 1 is a diagram explanatory of the outline of plural virtual . :
address spaces; ~:
Figure 2 is a diagram explanatory of the outlines of a segment table and a page table; ~ ~ :
Figure 3 is a block diagram explanatory of the procedure for translating a virtual address into a real address; :
Figure 4 is a diagram illustrating an example of a common virtual ..
register CVR prepared in this invention;
Figures 5A to 5H, inclusive, are diagrams explanatory of correspon~
dence of the content designated by the common virtual register of Figure 4 .~
with the range of existence of a common area on a virtual address space; : -Figure 6 is a block diagram of a processing system illustrating .
an embodiment of this invention; and . :
Flgure 7A and ~B are bloGk~:diagrams of the address translation ..
procedure showing more in detail the processing system of Figure 6, the diagrams being interconnected at the positions of the same reference ., ~ : :
characters (a), (b), (c) and (d).
In a virtual storage system, during programming, a virtual space . ~
can be successi~ely used to remove capacity limitations imposed on a main ....
memory which can be used in practice. That is, the magnitude of the virtual -space is dependent upon the architecture of hardware. For example, in the .
:..'.' .. :

.. i - . . ............ , - . . , . : : . , . ,.: - .
; ' '., , . . '. .:: . : '' ': ' : ' ' ' case where twenty-four bits can be employed for address designation, 2 = 16,777,216 bytes-,- 16 mega bytes.
During programming, an address which is designated unconsciously of the magnitude of a real memory, that is, a virtual address, is translated into a real address since it is necessary to access a buffer memory or a main memory in practice when the program is executed. This translation is dynamically achieved by a dynamic address translation mechanism of hardware at the time of execution of the program.
In the case of a plural virtual storage system, since respective programs are respectively assigned individual virtual address spaces, identical virtual addresses may exist in the respective virtual address spaces and a plurality of identical virtual addresses exist in the system as a whole.
In Fi.gures 1 and 2, reference numerals 1-0 to l-n indicate virtual address spaces~ 2-0 to 2-n designate segment tables; and 3-00, 3-01, ....
3-10, 3~11, ... , 3-nO, 3-nl, ... , 4-0, 4-1, ... , 5-0, 5-1, ... identify page -tables. As illustrated in Figure 1, jobs are assigned the plurality of virtual address spaces 1~0 to l-n respectively corresponding to jobs. The number of the virtual address spaces is limited mainly by an operating system.
At present, it is possible to handle about 1500 address spaces. The virtual address space~ 1-0 to l-n each have two common areas A and B and an area C
called individual user area USA. The area A (a system area SYA) and the area B (a common area CMA) are prepared in common to the virtual address spaces 1-0 to l-n. ~-In order that the addresses of the virtual address spaces may have one to one correspondence to the addresses of real address spaces on the main memory, the se~ment tables 2-0 to 2-n and the page tables 3-00, 3-01, 3-10, 3-11, ..., 3-nO, 3-nl, ..., 4-D, 4-1, ..., 5-0, 5-1, ... are prepared, as shown in Figure 2. The segment tables 2-0 to 2-n respectively correspond to the individual virtual address spaces 1-0 to l-n. And, to designate or _ 5 --.

~D~

identify one of the plurality of virtual address spaces~ the leading address of the segment table is designated. For designating the leading address, use is made of, for instance, a register referred to as a segment base register (SBR).
The processing for obtaining a real address from a virtual address corresponding to a certain v ~tual address space may be considered to be performed as follows:- Based on the content of the segment base register SBR corresponding to one of the abovesaid virtual address spaces, for in- ~
stance, 1-1, and one part of the bitSof a given virtual address, one address ~ -on the segment table 2-1 shown in Figure 2 is accessed. And based on the content of the accessed address of the segment table 2-1 and one part of the bits of the abovesaid virtual address~ one address on one page table, for ;
example, 3-11, is accessed. Then, based on the content of the accessed address of the page table 3-11 and one part of the bits of the abovesaid virtual address, the real address is determined. ~he result of coordination of the virtual address and the real address thus determined is stored in the table TLB. In the subsequent processing, the table TLB is retreived at first to check the coordination o~ the virtual address and the real address and then the real address is determined. Of course, in the case where the ,~
coordination of the virtual and real addresses is not stored on the table TLB, the real address is determlned by using the segment table 2 and the page tables 3, 4 and 5 again, and its result is stored on the table TLB. At this time, since the storage capacity of the table TLB is limited, one result ;
o~ coordincation which has not been used recently is removed fro~ the table TLB to permit storing therein of the new coordination result.
Figure 3 is a diagram showing in detail the procedure of the above address translation. ~;~
As mentloned above, the virtual address space is divided into units of two staees, i.e. segment and paee, and in accordance with the kind of the division, the virtual address is also divided into a segment number SGN, a ., ,: ~ . ' ,, : , -, ' : ' ~ . ' .- ' '': " : '.

~337~5~i page number PGN and an intra-page displacement BYT.N. The segment number SGN is indicative of ~hich segment is occupied by the virtual address.
Of twenty-four bits of the virtual address EA, eight bits, for example 61~-K
byte, 8 to 15, are used to indicate the segment number. The page number PGM is indicative of which page of the segment is occupied, and is repre-sented by four bits of the virtual address EA, for instance 4~K byte page size, 16 to 19. The intra-page displacement BYT.~ is indicative of which byte is occupied, and is represented by twelve bits of the virtual address EA, for example 64-K byte segment and 4-K byte page, 20 to 31.
For each segment and each page of the virtual address space, a segment table SGT and a page table PGT are formed by an operating system.
Each entry of the segment table SGT has the leading address (of, for in- - ;
stance, twenty-one bits) of the page table PGT having reserved therein the real address of each page belonging to the segment, and other information.
Each entry of the page table PGT has information on the presence or absence of the page on the real memory and twelve higher-order bits of a real page address (of, for example, twenty-four bits).
At first, for designating the leading address of the segment table SGT, since eighteen higher-order bits of the leading address of the segment table are stored in the bits 8 to 25 of a segment base register SBR of Figure 3, the leading address of the segment table can be obtained by adding Os of six bits to the lower order of the segment base register.
On the other hand, based on the base register, the index register and the intra-page displacement designated in a program, an effective virtual address is obtained by hardware, and set in a virtual address register EAR.
This virtual address (twenty-four bits) can be considered in terms of the segment number SGN (eight bits), the page number PGN (four bits) and the intra-page displacement BYT.N (twelve bits). ;~
Then, the segment number SGN of tha virtual address is compared with the length of a segment table length SGT ADR indicated by the abovesaid :
.

segment base register SBR. In this case, if the ~ormer is larger than the latter, the segment table entry desired to be obtained does not exist in the segment table SGT, so that the address translation is stopped.
The leading address of the segment table represented by the bits 8 to 31 of the segment base register SBR and the segment number represented by the bits 8 to 15 of the virtual address register EAR are added together in a dynamic address translation adder DAT ADDER, by which the desired segment table entry is detected from the segment table SGT. In this case, when an invalid bit in the entry (~or example, a bit 31) is "1", the address trans-lation is discontinued.
Since the bits, for example, 8 to 28, of the segment table entry thus detected are indicative of the leading address of the page table, these ~bits and the page number PGN represented by the bits 16 to 19 of the virtual -address register EAR are added together in an adder ADDER and, based on the .
result of this addition, a desired page table entry is detected ~rom the page table PGT. In this case, the page number PG~ and the page table ~-length PGTL indicated by the segment table entry are compared with each other.
Where the former is larger than the latter, the page table entry desired to obtain does not exist in the page table PGT, so that the address translation -is stopped. Further, if an invalid bit (for example, a bit 12) in the page ::
table entry detected is "1", the content of the corresponding real page does not exist in the real memory, so that the address translation is also stopped.
Since the bits 0 to 11 in the page table entry are the twelve higher-order bits of the real paga, they are transferred to the bits 8 to 19 of a real address register RAR and, at the same time, the intra-page displace- ;
ment BYT.~ represented by the bits 20 to 31 of the virtual address register EAR is transferred to the bits 20 to 31 of the real address register RAR and used as twelve lower order bits of the real address.
... . ..... .. .
Thus, the address translation is complicated.
As described above, in the data processing system, the processing " ' .

is achieved for the coordination of the virtual and real addresses. As is seen from Figure 2, even if the common areas A and B existing on the virtual address spaces 1-0 to l-n are different from each other in the virtual address space 1 and accordingly the segment table 2, the real addresses are obtained by using the common page tables 4 and 5. That is, even where the virtual ad-dress spaces differ, if the virtual addresses of the areas A and B are the same, they correspond to the same real address. Therefore, when the results of coordination of the virtual and real addresses concerning the common areas A and B are stored in the table TLB, it is very wasteful if the coordination results are stored on the table TLB for all of the virtual address spaces.
That is, if the results of coordination of the virtual and real addresses that the same address is extracted in spite of different virtual address spaces are individually registered on the table TLB, other coordination re-sults which may be required in the subsequent processing are removed from the table TLB, thus remarkably lowering the efficiency of utilization of the table TLB.
To avoid this, the present invention employs such a common virtual register CVR 6 as shown in Figure 4, by which it is indicated the range on the virtual address space 1 in which the common areas A and B are positioned.
In Figure 4, reference character HBA designates a high bound address, which indicates an area corresponding to the area A shown in Figure 1. As seen from Figurea 5A to 5H, the abovesaid address indicates that the area from the ~;
address designated by the content of the above field HBA to a ma~imum virtual ~ -address (for exa~ple, 16 MB) of the virtual address space is the common area.
Reference character HV identifies a high bound address validity indicating bit, and when the high bound address validity indicating bit has the logic "1", it indicates that the address designated by the field HBA is valid. Reference character LBA denotes a low bound address, which indicates an area correspond-ing to the area B shown in Figure 1. And, as is seen from Figure 4, it is indicated that the area from the address "0" of the virtual address ~ ~ .. ' , . . . . . .
- , . ,: . ... i : ' .. . . ... , , ',,, .... : . :

space to the address indicated by the content of the abovesaid field LBA
is the common area. Reference character LV represents a low bound address ~-~
validity indicating bit and when this bit has the logic "1", it indicates that the address indicated by the field LBA is valid.
The ranges which the common areas A and B occupy on the virtual address space differ with systems, as shown in Figur~ 5A to 5H. To set the ~ -abovesaid information HV, HBA, LV and LBA in the common virtual register 6 ~ -corresponding to the modes depicted in Figure 5A to 5X, for instance, a load common virtual register instruction (hereinafter referred to as the LCVR
instruction), which is prepared in this invention, is executed.
Figure 6 illustrates the construction of an embodiment of ths invention adapted such that based on the content set in the common virtual register, the results of coordination of virtual and real addresses corres~
ponding to the common areas A and B are stored in common to the virtual -address spaces. In Figure 6, reference numeral 6 indicates a common virtual register CVR, 7 designates a translation look aside buffer TLB, 8 identifies a decoder for accessing a predetermined address of the table TLB; 9 denotes a virtual address register, in which is set the virtual address EA to be translated into a real address RA, for e~ample, when a central processing unit executes processing; 10 represents a real address register, in which is set the real address RA to be registered when the result of coordination of virtual and real addresses is written in the table TLB 7; 11 shows a virtual address space identify information register, in which is set identify infor-mation ID indicative of the virtual address space to which the coordination result corresponds when the coordination result is~registered on the table TLB 7 or read out therefrom; 12 refers to a logical address holding register, in which is temporarily held one portion of the content of the register 9 when the table TLB is read out; 13 indicates a first coincidence detector circuit, which checks coincidence of one porition of bits of the virtual address EA read out from the table TLB with the content of the holding re-gister 12; 14 indicates a second coincidence detector circuit, which checks coincidence of the indentify information ID read out from the table TLB 7 with the identif~ information set in the register 11 when the former infor- :
mation is read out from the table TLB 7; V designates a validity indicating bit, which indicates that the result of coordination of the virtual and real addresses registered on the table TLB 7 is valid when the validity indicating -bit has the logic "l"; 15 identifies an AND circuit, whose output of the logic "1" indicates that the real address RA corresponding to the virtual address EA set on the virtual address register 9 exists in the table TLB 7 (TI,B HIT);
16 denotes a comparator circuit provided according to this invention, uhich ~.
circuit checks whether or not the virtual address EA set in the virtual address register 9 corresponds to the addresses in the common areas A and B set in the common virtual register CVR 6; and 17 represents an identify information modify circuit, which modifies the identify information set in the register 11, that is, the information designating the virtual address space, into a predetermined pattern when the comparator circuit 16 has the logic "1".
To access a memory when the central processing unit executes processing, it is necessary to translate the v:irtual address EA into the real address RA. To this end, the first step is to access the table TLB 7. That is, the virtual address EA to be translated is set in the virtual address register 9 and, for example, bits 8 to 11 of the virtual address EA are held in the holding register 12 and, with bits:12 to 19, the table TLB 7 is access-ed to be read out. By this operation, the identify information ID indlcating the virtual address epace to which the information previously registeredj that is, the result of coordination of the virtual and real addresses, and the present coordination result correspond, and the validity indicating bit V ~
are read out from the corresponding address of the table TLB 7. The coordina- : -: tion result is representative of the coordination of flth to 11th bits of the virtual address with 8th to l9th bits of the real address. Accordingly, when the 8th to 11th bits of the virtual address thus read out and the content '': ''' . "
: ,:
- 11 - '.

. : , . . .: ,, : .:. .

~7'~

of the holding register 12 are coincident with each other, it is indicated that the ~th to l9th bits of the real address read out correspond to the virtu-al address to be translated. Consequently, the coincidence detector circuit 13 checks the above coincidence, and produces an output of the logic "1" when it detects the coincidence. Further, in the above said translation, the cen-tral processing unit sets iden~ify information in the register 11 for indicat-ing the virtual address space to which the virtual address set in the virtual addressregister 9 corresponds. And the coincidence detector circuit 1~ checks whether the identify information ID read out from the table TLB 7 and the con-tent of the register 11 are coincident with each other or not, and if coinci-dent, produces an output of the logic "l". Further, the validity bit V is read out from the table TLB 7, and applied to the AND circuit 15. Accordingly, the state in which the AND circuit 15 produces the ou~put of the lo~ic "1l' im- -plies the following facts:- C~ The coordination of the virtual address cor-responding to that EA set in the register 9 with the real address exists on the table TLB 7; ~ the coordination is valid; and ~ the coordination corresponds to the desired virtual address space. As a result of this, a sighal TLB HIT
is generated and, the real address RA read out at this moment is employed as a translated real address for accessing the memory.
At this time, if the AND circuit 15 does not turn on, it implies that the coordination of the desired virtual address with the real address does not exist on the table TLB 7. In this case, the read address is extracted by the segment table SGT and the page table PT and the coordination result is regis-tered on the table TLB 7. That is, the extracted real address is set in the register lO, and registered on the table TLB 7 by using the virtual address EA set in the register 9. Needless to say, in this case, the identify inform-ation ID indicating the virtual address space is set in the register ll, and registered on the table TLB 7. Further, the validity indicating b~t V is written in the form of the logic "l".

In this case, however, if the virtual address EA set in the register 9 ~ -. , . , , : . , : . . . ~ : . . .

~c~

lies in the address given by the content of the common virtual register 6, the comparator circuit 16 produces the logic "1", by which the identify information ID set in the register 11 is modified by the modify circuit 17 into a predeter- -mined pattern and is registered on the table TLB 7. Of course, in the case where the virtual address EA set in the register 9 does not lie in the above-said common area, the identify information ID set in the register 11 is regist-ered as it is on the table TLB 7.
In this state, in the processing by the central processing unit, the virtual address EA is set in the register 9 for extracting the real address and the table TLB 7 is accessed to be read out. At this timel if the virtual address EA set in the register 9 lies in the address given by the content of the common virtual register 6, the comparator circuit 16 produces an output of the logic "1" as is the case with the above. Accordingly, in this case, too, the identify information ID set in the register 11 is modified by the modify circuit 17 into a predetermined pattern and supplied to the coincidence detector circuit 14, In the abovesaid accessing for readout, the table TLB 7 is accessed with the virtual address EA set in the register 9, by which the identify information ID is read out from the corresponding address on the table TLB 7. Needless to say, the identify information ID thus read out is a predetermined pattern written in the previous registration. Therefor, the coincidence detector circuit 14 provides a coincidence output even if the virtual address spaces are different. That is, the AND circuit 15 produces the signal TLB HIT and it is regarded the desired coordination of virtual and real add~esses exists on the table TLB 7, and the real address RA thus read out is utilized. This means the following fact:- Even when the virtual address spaces are diferent, if the virtual address EA to be translated cor-responds to the common area A or B shown in Figure 1, the coordination result is registered in common to the virtual address spaces, not for each of them.
Turning now to Figures 7A and 7B, the operation of the system of this 3~ invention will hereinafter be described in detail. Figures 7A and 7B show . . . .. . . . . .. .
.; . ~ . .. . . .
.. , , ' . ~
.

~7~

the table TLB, the address translation mechanism and the common virtual regis-ter.
The identify information ID of the virtual address space written in each element of the table TLB is administered in terms of hardware, and a segment table origin stack (hereinafter referred to as the STO stack) holds segment table origin addresses of plural spaces in the TLB at the same time.
The STO stack is a high-speed memory which stores the coordination of the segment table leading address of each address space indicated by a segment base register SBR with the identify information ID of hardware.
Upon switching of the virtual address space by the operating system, the ST0 stack is referred to at first. If informa~ion of the same value as -the segment table leading address exists in the STO stack, the virtual address space is already registered in the STO stack, so that the identify information ID of the STO stack is valid. But in the absence of the abovesaid information, the virtual address space is newly registered, by which the identify informat- -ion ID for the virtual address space is obtained. And this identify inform-ation ID is stored in an identify register IDR. Thus, it is possible to re-markably reduce the probability that the content of the table TLB becomes in-valid at each switching of the virtual address space.
In Figures 7A and 7B, when to translate a virtual address into a real address, reference is made to the table TLB prior to the translation by the use of the segment table SGT and the page table PGT.
Then, when the table TLB has been accessed with the address ~the page number PGN) of the bits 12 to 1~ of the virtual address register EAR, this address is decoded and any one of, for instance, 256 entries, is selected. In such a case, an output TLB HIT is obtained from an AND gate Al by satisfying the conditions that the validity indica~iDg bit V representativ0 of validity ~-of the selected entry, that a ~-bit pattern from the identify register IDR and the identify information ID in the entry are collated with each other in a comparator CMPl to obtain a coincidence output and that the bits 8 to 11 of the ~;
~'''' '' .' -1~- . ~
. , ::
, .;
': ' ' , ' ' . :,:

virtual address register EAR and the virtual address EA in the entry are col-lated with each other in a comparator CMP2 to ob~ain a coincidence output. An entry in the table TLB selected at the same time is set in a TLB data register TDR and, by the output TLB HIT, a gate is opened, by which the real address RA in the entry is set in bits ~ to 19 of a real address register RAR and, at the same time, bits 20 to 31 of the virtual address register EAR are set as low-order bits of the real address register RAR.
On the other hand, before the table TLB is accessed with the virtual address, the high bound address HBA represented with bits 8 to 15 of the common virtual register CVR and the address ~the segment number SGN) represented with bits 8 to 15 of the virtual address register EAR are compared with each other in a comparator CMP3 and, further, the low bound address LBA represented with bits 24 to 31 of the common virtual register CVR and the address ~the segment -number SGN) represented with bits 8 to 15 of the virtual address register EAR
are compared with each other in a comparator CMP4, When both validity indicat-ing bits HV and LV are "1" and the common area is indicated, a common indicat-ing signal CMN is produced, by which an identify information modify circuit IDM is changed over to modi~y the 4-bit pattern into all "0". That is, of sixteen patterns obtainable with four bits, "0" is used in the case of the com-mon area and the remaining "1" to ~15" are used for entries of other virtual address spaces~
: .
Further, in the case of reading the identify information ID of the com-mon area in the en~ry of the table TLB, the abovesaid all "O" is read therein, so that when the two are compared with each other in the comparator CMPl, a ~-coincidence output is produced to obtain the real address of the common area.
Next, where the TLB entry is not the entry for this virtual address, ;~
the output TLB HIT is not produced, so that the real page address is obtained by immediately re~erring to the segment table SGT with the segment number SGN
and the page number PGN represented by the high-order bits of the virtual ad-dress EA.

'' ~ ' '' . . " ' ' .. ' ~ ' ~' ... ..
. . , : .
.

That is, the segment table leading address indicated by the segment base register SBR and the segment number SGN of the virtual address resister EAR are added together in a dynamic address translation adder DAT ADDER and the result of addition is set in a table address register TAR. Then, the segment table SGT stored in a main memory MS is accessed with the abovesaid result used as an address.
The width of data read out from the main memory MS is 8-byteJ and this is set in a storage data register SDR. Since bits 0 to 31 (even) and bits .
32 to 63 (odd) of the data from 4-byte segment table entries, "odd" or "even"
is selected depending upon whether the bit 29 is "1" or "0", and a segment entry gate SGE is opened to transfer the 4-byte data to a table entry register TER.
Next, bits 8 to 28 of the table entry register TER and the page number PGN represented with bits 16 to 19 of the virtual address regis~er EAR are added together in the adder DAT ADDER and the result of the addition is se~ in the table address register TAR. And this result is used as an address for ac- - .
cessing the page table PGT in the main memory MS to read out therefrom a table .-entryJ which is set in the storage data register SDR. In this case~ the data :
width of the page table is 2-byte and ei~her one of groups of bits 0 to 15 and 20 bits 16 to 31, or either one of groups of bits 32 to 47 and bits 47 to 62 of ~;
the data bits set in the register SDR is selected depending upon whe~her the -~
bit positions 29 to 30 are "00", "01", "10", or "11". Then, the entry gate : ;
PGE is opened to transfer the 2-byte data to bits 0 to 15 of the table entry register TER. :
The bits 0 to 11 of the table entry register TER are transferred to bits .:
8 to 19 of the real address register RAR and, at the same time, the low-order ; .
bits 20 to 31 o~ the virtual address register EAR are transferred as they are to the low-order bits 20 to 31 of the real address register RAR. ~hen the low-order bits of the virtual address register EAR are set in some other register, they are transferred therefrom.

' , . . .

.
.. .

~)'7~

The data of the real address register RAR is used as a translated real address for accessing the memory.
At the same time, the coordination of the virtual and real page address- -es is registered in the entry of the table TLB, along with the identify infor-mation ID.
In this case, the ILB data register TDR performs the -function of read-ing out the entry from the table TLB to set the entire bit byte width as des-cribed above and, at the same time, also serve to assemble data for registra-tion in the table TLB after the dynamic address translation. That is, the vir-~ual address EA, the real address RA, the identify information ID and the val-idity indicating bit V respectively set four bi~s 8 to 11 of the virtual address register EAR, twelve bits 0 to 11 of the table entry register TER, four bits of the identify register IDR and "1" from the generator in the TLB data regist- ~
er TDR by opening a TLB registration gate TLB Enroll. ;
When the entry to be registered in the table TLB has been assembled in the TLB data register TDR, a TLB write gate TLB WRT is opened by using the cycle of registration, through which gate the abovesaid entry is written in one of 256 entries of the table TLB. If 256 entries are all occupied9 the previous entry is removed by newly writing the abovesaid entry. In the case -~
of using two tables TLB of primary and alternate blocks, the entry is writte~
in a selected one of them.
For indicating that a certain coordination result in the table TLB
co~responds to the common area, it is also possible to employ such a method which i5 exactly the same as ordinary methods in connection with the virtual -address space identification but adds a specific bit for each coordination in the table TLB. With this method, another bit is added to the table TLB
and when new address coordination is stored therein, if it corresponds to the --common area, the abovesaid bit is made "1". And where the abovesaid bit is "1" as a result of retrieval of the table TLB, the output from the coincidence detector circuit in Figure 5 is made "1" regardless of the result of its coin-.

~D'74~5~
cidence detecting operation.
As has been described in the foregoing, according to this inventionl when the result of address coordination corresponds to the common area A or B, it is registered on the table TLB in common to different virtual spaces, there~
by to efficiently u~ilize the table TLB and hence enhance the efficiency of the system.
It will be apparent that many modifications and variations may be ef-fected without departing from the scope of novel concepts of this invention.

. ''.': '' ' ,::
. -',,: -.

~ : "'.". .' ' '`'; ' ' ' ' .'~''' ':' ' ,.,~;,: ,.. .
" .' ' ' . " :
'. ~
" . ' `, ~ ', :'' '.
: ,' .
':

:, ', - ~ ' ~ ,"', :' : ' , . , ~, .. ... .

Claims (5)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A plural virtual address space processing system for a data processing system which comprises a translation mechanism for translating a virtual address into a real address and a memory for storing the real address translated by the translation mechanism and in which in data processing, if a desired real add-ress is stored in the memory, the real address is used for data processing and if not stored, the desired real address is obtained with the translation mech-anism, said plural virtual address space processing system comprising: common area indicating means for indicating the range of a common area in which the same virtual address is translated into the same real address in each virtual address space; and a comparator circuit for detecting whether or not the vir-tual address to be translated into the real address lies in the range indicated by the common area indicating means; wherein when the real address is stored in the memory, if the virtual address corresponding to the real address indi-cated as an address of the common area, common area identify information is stored together with the real address, and wherein if the virtual address cor-responding to the real address is indicated as an address of another area than the common area, virtual address space identify information is stored together with the real address.
2. A plural virtual address space processing system according to claim 1, wherein the common area indicating means is constructed so that the content of its indication can be rewritten according to programs.
3. A plural virtual address space processing system according to claim 1, wherein the common area identify information is a specific bit which is added to a bit pattern used for the virtual address space identify information.
4. A plural virtual address space processing system according to claim 1, wherein the comparator circuit for detecting whether or not the virtual address lies in the common area is means for respectively comparing a high bound ad-dress and a low bound address forming the common area indicating means in con-nection with the associated part forming the virtual address.
5. A plural virtual address space processing system according to claim 1, 3 or 4, wherein when the virtual address is detected by the comparator circuit to lie in the common area, switching means of a virtual address space identify information modify circuit is actuated to modify the bit pattern used as the virtual address space identify information.
CA279,994A 1976-06-08 1977-06-07 Plural virtual address space processing system Expired CA1074455A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6680776A JPS52149444A (en) 1976-06-08 1976-06-08 Multiplex virtual space processing data processing system

Publications (1)

Publication Number Publication Date
CA1074455A true CA1074455A (en) 1980-03-25

Family

ID=13326494

Family Applications (1)

Application Number Title Priority Date Filing Date
CA279,994A Expired CA1074455A (en) 1976-06-08 1977-06-07 Plural virtual address space processing system

Country Status (5)

Country Link
US (1) US4145738A (en)
JP (1) JPS52149444A (en)
CA (1) CA1074455A (en)
DE (1) DE2725718C2 (en)
ES (1) ES459518A1 (en)

Families Citing this family (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4136385A (en) * 1977-03-24 1979-01-23 International Business Machines Corporation Synonym control means for multiple virtual storage systems
JPS5454536A (en) * 1977-10-08 1979-04-28 Fujitsu Ltd Data processor
US4376297A (en) * 1978-04-10 1983-03-08 Signetics Corporation Virtual memory addressing device
US4170039A (en) * 1978-07-17 1979-10-02 International Business Machines Corporation Virtual address translation speed up technique
US4215402A (en) * 1978-10-23 1980-07-29 International Business Machines Corporation Hash index table hash generator apparatus
US4251860A (en) * 1978-10-23 1981-02-17 International Business Machines Corporation Virtual addressing apparatus employing separate data paths for segment and offset portions of a virtual address and utilizing only the offset portion to calculate virtual address
US4264953A (en) * 1979-03-30 1981-04-28 Honeywell Inc. Virtual cache
US4332010A (en) * 1980-03-17 1982-05-25 International Business Machines Corporation Cache synonym detection and handling mechanism
US4355355A (en) * 1980-03-19 1982-10-19 International Business Machines Corp. Address generating mechanism for multiple virtual spaces
JPS5764383A (en) * 1980-10-03 1982-04-19 Toshiba Corp Address converting method and its device
US4520441A (en) * 1980-12-15 1985-05-28 Hitachi, Ltd. Data processing system
US4410941A (en) * 1980-12-29 1983-10-18 Wang Laboratories, Inc. Computer having an indexed local ram to store previously translated virtual addresses
US4374417A (en) * 1981-02-05 1983-02-15 International Business Machines Corp. Method for using page addressing mechanism
US4407016A (en) * 1981-02-18 1983-09-27 Intel Corporation Microprocessor providing an interface between a peripheral subsystem and an object-oriented data processor
JPS57143782A (en) * 1981-03-03 1982-09-06 Toshiba Corp Information processor
US4432053A (en) * 1981-06-29 1984-02-14 Burroughs Corporation Address generating apparatus and method
US4453212A (en) * 1981-07-13 1984-06-05 Burroughs Corporation Extended address generating apparatus and method
US4495565A (en) * 1981-11-09 1985-01-22 At&T Bell Laboratories Computer memory address matcher and process
JPS6047623B2 (en) * 1982-02-12 1985-10-22 株式会社日立製作所 Address translation method
US4539637A (en) * 1982-08-26 1985-09-03 At&T Bell Laboratories Method and apparatus for handling interprocessor calls in a multiprocessor system
US4714990A (en) * 1982-09-18 1987-12-22 International Computers Limited Data storage apparatus
USRE37305E1 (en) * 1982-12-30 2001-07-31 International Business Machines Corporation Virtual memory address translation mechanism with controlled data persistence
US4626988A (en) * 1983-03-07 1986-12-02 International Business Machines Corporation Instruction fetch look-aside buffer with loop mode control
US4602368A (en) * 1983-04-15 1986-07-22 Honeywell Information Systems Inc. Dual validity bit arrays
US4901230A (en) * 1983-04-25 1990-02-13 Cray Research, Inc. Computer vector multiprocessing control with multiple access memory and priority conflict resolution method
US4636942A (en) * 1983-04-25 1987-01-13 Cray Research, Inc. Computer vector multiprocessing control
US4661900A (en) * 1983-04-25 1987-04-28 Cray Research, Inc. Flexible chaining in vector processor with selective use of vector registers as operand and result registers
US4577274A (en) * 1983-07-11 1986-03-18 At&T Bell Laboratories Demand paging scheme for a multi-ATB shared memory processing system
US4714993A (en) * 1983-10-18 1987-12-22 International Business Machines Corporation Apparatus and method for effecting dynamic address translation in a microprocessor implemented data processing system
JPS6091462A (en) * 1983-10-26 1985-05-22 Toshiba Corp Arithmetic controller
US4589092A (en) * 1983-12-12 1986-05-13 International Business Machines Corporation Data buffer having separate lock bit storage array
US4731740A (en) * 1984-06-30 1988-03-15 Kabushiki Kaisha Toshiba Translation lookaside buffer control system in computer or virtual memory control scheme
JPS61190638A (en) * 1985-02-20 1986-08-25 Hitachi Ltd File control system for virtual computer
US4754398A (en) * 1985-06-28 1988-06-28 Cray Research, Inc. System for multiprocessor communication using local and common semaphore and information registers
US4745545A (en) * 1985-06-28 1988-05-17 Cray Research, Inc. Memory reference control in a multiprocessor
US4774653A (en) * 1985-08-07 1988-09-27 Hewlett-Packard Company Hybrid hardware/software method and apparatus for virtual memory address translation using primary and secondary translation buffers
JPH0658649B2 (en) * 1985-10-28 1994-08-03 株式会社日立製作所 Area management method in virtual memory device
US5230045A (en) * 1986-11-12 1993-07-20 Xerox Corporation Multiple address space system including address translator for receiving virtual addresses from bus and providing real addresses on the bus
US5123101A (en) * 1986-11-12 1992-06-16 Xerox Corporation Multiple address space mapping technique for shared memory wherein a processor operates a fault handling routine upon a translator miss
EP0282213A3 (en) * 1987-03-09 1991-04-24 AT&T Corp. Concurrent context memory management unit
US5278840A (en) * 1987-07-01 1994-01-11 Digital Equipment Corporation Apparatus and method for data induced condition signalling
US5008811A (en) * 1988-02-10 1991-04-16 International Business Machines Corp. Control mechanism for zero-origin data spaces
US4945480A (en) * 1988-02-10 1990-07-31 International Business Machines Corporation Data domain switching on program address space switching and return
US4943913A (en) * 1988-02-10 1990-07-24 International Business Machines Corporation Operating system accessing control blocks by using home address space segment table to control instruction and operand fetch and store operations
JPH01255945A (en) * 1988-04-06 1989-10-12 Hitachi Ltd Address converter in virtual computer
GB8825764D0 (en) * 1988-11-03 1988-12-07 Lucas Ind Plc Computer memory addressing system
US5095420A (en) * 1988-11-21 1992-03-10 International Business Machines Method and system for performing virtual address range mapping in a virtual storage data processing system
US5142638A (en) * 1989-02-07 1992-08-25 Cray Research, Inc. Apparatus for sharing memory in a multiprocessor system
DE4019961C2 (en) * 1989-06-23 1994-11-24 Hitachi Ltd Controller for accessing an address translation memory in a processor system
JPH0679296B2 (en) * 1989-09-22 1994-10-05 株式会社日立製作所 Multiple virtual address space access method and data processing device
US5497474A (en) * 1993-02-25 1996-03-05 Franklin Electronic Publishers, Incorporated Data stream addressing
US5666556A (en) * 1993-12-30 1997-09-09 Intel Corporation Method and apparatus for redirecting register access requests wherein the register set is separate from a central processing unit
US6385712B1 (en) * 1999-10-25 2002-05-07 Ati International Srl Method and apparatus for segregation of virtual address space
GB2357166B (en) * 1999-12-07 2001-10-31 Marconi Comm Ltd Memory access system
US6560687B1 (en) * 2000-10-02 2003-05-06 International Business Machines Corporation Method of implementing a translation lookaside buffer with support for a real space control
US7366352B2 (en) * 2003-03-20 2008-04-29 International Business Machines Corporation Method and apparatus for performing fast closest match in pattern recognition
US7227994B2 (en) * 2003-03-20 2007-06-05 International Business Machines Corporation Method and apparatus for imbedded pattern recognition using dual alternating pointers
JP4085328B2 (en) * 2003-04-11 2008-05-14 ソニー株式会社 Information processing apparatus and method, recording medium, program, and imaging apparatus
US20070011429A1 (en) * 2005-07-07 2007-01-11 Vasudevan Sangili Virtual memory key generation

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL294416A (en) * 1962-06-22
JPS532296B2 (en) * 1973-03-19 1978-01-26
US3825904A (en) * 1973-06-08 1974-07-23 Ibm Virtual memory system
JPS5315778B2 (en) * 1973-07-18 1978-05-27
JPS5434577B2 (en) * 1974-06-28 1979-10-27

Also Published As

Publication number Publication date
US4145738A (en) 1979-03-20
JPS52149444A (en) 1977-12-12
ES459518A1 (en) 1978-10-01
DE2725718A1 (en) 1977-12-15
DE2725718C2 (en) 1985-05-02

Similar Documents

Publication Publication Date Title
CA1074455A (en) Plural virtual address space processing system
CA1313424C (en) Nonhierarchical program authorization mechanism
CA2022656C (en) Translation look-aside buffer for a computer memory system
US4068303A (en) Address translation managing system with translation pair purging
US4300192A (en) Method and means for storing and accessing information in a shared access multiprogrammed data processing system
US4459661A (en) Channel address control system for a virtual machine system
EP0058844B1 (en) Address generator for multiple virtual address spaces
CA1261479A (en) Direct input/output in a virtual memory system
US4564903A (en) Partitioned multiprocessor programming system
EP0149389B1 (en) Address translation control system
JPH01207856A (en) Address space control mechanism
US5437016A (en) Apparatus and method for translating logical addresses for virtual machines
US4991082A (en) Virtual storage system and method permitting setting of the boundary between a common area and a private area at a page boundary
US4409655A (en) Hierarchial memory ring protection system using comparisons of requested and previously accessed addresses
US5519860A (en) Central processor index sort followed by direct record sort and write by an intelligent control unit
EP0175398A2 (en) Data processing system comprising a memory access controller which is provided for combining descriptor bits of different descriptors associated with virtual addresses
EP0425771A2 (en) An efficient mechanism for providing fine grain storage protection intervals
JPS5818708B2 (en) Method and apparatus for storing and accessing information in a shared access multi-program data processing system
EP0250876B1 (en) Apparatus and method for page replacement in a data-processing system having a virtual memory
CA1308202C (en) Access register translation means for address generating mechanism for multiple virtual spaces
EP0533190B1 (en) Data processing system with address translation function for different page sizes
EP0285309A2 (en) Memory protection apparatus for use in an electronic calculator
JPS5925303B2 (en) Multiple virtual memory control method in multiple virtual computer system
JPS5830320Y2 (en) Multiple virtual space processing data processing device
JPH06139147A (en) Cache memory system

Legal Events

Date Code Title Description
MKEX Expiry